Another overhaul of the R-C extraction code. This fixes a known

long-standing problem, in which the resistance extraction attempts
to determine the device type of each device.  Which is stupid,
because the original extraction process has already done this, and
the information is readily available in the .ext file.  This update
allows "extresist" to get all the device information from the .ext
file, so there is no guesswork and no extra time spent trying.
Unfortunately, it does not solve the problem I expected it to solve,
which is the disappearance of _dss and moscap devices from gf180mcu
netlists.  More work to do. . .

VERSION

@@ -1 +1 @@
-8.3.656
+8.3.657

extflat/EFread.c

@@ -333,6 +333,26 @@ readfile:
 		r.r_xtop = (int)(0.5 + (float)atoi(argv[5]) * locScale);
 		r.r_ytop = (int)(0.5 + (float)atoi(argv[6]) * locScale);
 
+		if (!strcmp(argv[2], "Short"))
+		{
+		    /* Device name "Short" is a reserved name indicating
+		     * that the device does not get output but acts as a
+		     * short between the first two terminals.  Consequently,
+		     * it acts like an "equiv" statement.
+		     */
+		    int argstart = 7;
+		    /* "Short" devices should not have parameters, but just in
+		     * case, skip over any that are found.
+		     */
+		    while (strchr(argv[argstart], '=') != NULL) argstart++;
+		    if (argstart + 4 >= argc)
+			efReadError("Bad terminal description for Short device\n");
+		    else
+			efBuildEquiv(def, argv[argstart + 1], argv[argstart + 4],
+				resist, isspice);
+		    break;
+		}
+
 		if (efBuildDevice(def, (char)n, argv[2], &r, argc - 7, &argv[7]) != 0)
 		{
 		    efReadError("Incomplete terminal description for device\n");

extract/ExtBasic.c

@@ -2665,30 +2665,6 @@ extOutputDevices(def, transList, outFile)
 	if (!strcmp(devptr->exts_deviceName, "Ignore"))
 	    continue;
 
-	/* Model type "Short" in the techfile indicates a device    */
-	/* to short across the first two nodes (the gate and the    */
- 	/* source).  This solves the specific issue of a transistor */
-	/* extended drain where the drain is a resistor but the	    */
-	/* resistor is part of the model and should not be output.  */
-
-	if (!strcmp(devptr->exts_deviceName, "Short"))
-	{
-	    fprintf(outFile, "equiv ");
-
-	    /* To do:  Use parameters to specify which terminals   */
-	    /* are shorted.					   */
-
-	    /* gate */
-	    node = (NodeRegion *)ExtGetRegion(reg->treg_tile, reg->treg_dinfo);
-	    fprintf(outFile, "\"%s\" ", extNodeName((LabRegion *)node));
-
-	    /* First non-gate terminal */
-	    node = (NodeRegion *)extTransRec.tr_termnode[0];
-	    fprintf(outFile, "\"%s\"\n", extNodeName((LabRegion *)node));
-
-	    continue;
-	}
-
 	/* Original-style FET record backward compatibility */
 	if (devptr->exts_deviceClass != DEV_FET)
 	    fprintf(outFile, "device ");

resis/ResJunct.c

@@ -135,6 +135,8 @@ ResNewSubDevice(tile, tp, xj, yj, direction, PendingList)
     ri = (resInfo *) TiGetClientPTR(tp);
     resDev = ri->deviceList;
 
+    if (resDev == NULL) return;		/* Should not happen? */
+
     if (resDev->rd_fet_subs == (resNode *)NULL)
     {
 	resptr = (resNode *) mallocMagic((unsigned)(sizeof(resNode)));

resis/ResMain.c

@@ -1417,19 +1417,30 @@ ResExtractNet(node, resisdata, cellname)
 
     ResDissolveContacts(ResContactList);
 
-    /* Add "resInfo" fields to tiles */
+    /* Fracture the plane to change maximum horizontal stripes to a
+     * format better suited to tracking the path of current through
+     * the wiring.
+     */
 
     for (pNum = PL_TECHDEPBASE; pNum < DBNumPlanes; pNum++)
     {
     	Plane	*plane = ResUse->cu_def->cd_planes[pNum];
 	Rect	*rect  = &ResUse->cu_def->cd_bbox;
 	ResFracture(plane, rect);
-	(void) DBSrPaintClient((Tile *) NULL, plane, rect,
-	 		&DBAllButSpaceAndDRCBits,
-			(ClientData) CLIENTDEFAULT, ResAddPlumbing,
-			(ClientData) &ResDevList);
     }
 
+    /* Add "resInfo" fields to device tiles. */
+    for (thisDev = DevTiles; thisDev; thisDev = thisDev->nextDev)
+	ResAddDevPlumbing(thisDev, &ResDevList);
+
+    /* Add "resInfo" fields to any untouched tiles. */
+    for (pNum = PL_TECHDEPBASE; pNum < DBNumPlanes; pNum++)
+	DBSrPaintClient((Tile *)NULL, 
+		ResUse->cu_def->cd_planes[pNum],
+		&TiPlaneRect, &DBAllButSpaceAndDRCBits,
+		(ClientData)CLIENTDEFAULT, ResAddPlumbing,
+		(ClientData)NULL);
+
     /* If this is a top-level cell, then determine where connections
      * are made into the cell from ports.  Otherwise, determine points
      * of entry by looking at how all parent cells connect to this

resis/resis.h

@@ -549,6 +549,7 @@ extern int	      		ResExtCombineParallel();
 extern int 			dbSrConnectStartFunc();
 extern int			ResEach();
 extern int			ResAddPlumbing();
+extern void			ResAddDevPlumbing();
 extern int			ResRemovePlumbing();
 extern float			ResCalculateChildCapacitance();
 extern ResDevTile		*DBTreeCopyConnectDCS();