Additional modification to write out a resistor or capacitor value
as-is, without a parameter name and before any device model name or substrate pin, according to CDL syntax, if the parameter has been specified without a parameter name (e.g., "r=" instead of "r=r"). Corrected an error in the extract code which put the substrate node name in front of parameters instead of after. This was previously unexercised because only in CDL format does a resistor or capacitor model have parameters listed by name.
This commit is contained in:
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acdfb256a1
commit
8c323803b7
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@ -126,6 +126,50 @@ GetHierNode(
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return(nn->efnn_node);
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}
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/*
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* ----------------------------------------------------------------------------
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*
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* spcHierWriteValue ---
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*
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* Special case of spcHierWriteParams() below. Only check for 'r' or 'c'
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* parameters which have no parameter name. Write out the given value,
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* which in the case of CDL format is written out after the pins but before
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* everything else, arbitrarily.
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*
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* ----------------------------------------------------------------------------
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*/
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void
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spcHierWriteValue(
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HierContext *hc,
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Dev *dev) /* Dev being output */
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{
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DevParam *plist;
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plist = efGetDeviceParams(EFDevTypes[dev->dev_type]);
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while (plist != NULL)
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{
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switch (plist->parm_type[0])
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{
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case 'r':
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if (*(plist->parm_name) == '\0')
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{
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fprintf(esSpiceF, " ");
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esSIvalue(esSpiceF, (double)(dev->dev_res));
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}
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break;
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case 'c':
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if (*(plist->parm_name) == '\0')
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{
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fprintf(esSpiceF, " ");
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esSIvalue(esSpiceF, (double)(dev->dev_cap));
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}
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break;
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}
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plist = plist->parm_next;
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}
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}
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/*
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* ----------------------------------------------------------------------------
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*
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@ -164,6 +208,7 @@ spcHierWriteSubParam(
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dev->dev_type, esSpiceF);
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retvalue = TRUE;
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}
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break;
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}
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plist = plist->parm_next;
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}
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@ -423,12 +468,18 @@ spcHierWriteParams(
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* scale * esScale * 1.0E-6);
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break;
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case 'r':
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)(dev->dev_res));
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if (*(plist->parm_name) != '\0')
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{
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)(dev->dev_res));
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}
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break;
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case 'c':
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)(dev->dev_cap));
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if (*(plist->parm_name) != '\0')
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{
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)(dev->dev_cap));
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}
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break;
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}
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plist = plist->parm_next;
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@ -509,7 +560,10 @@ esOutputHierResistor(
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bool subdone = FALSE;
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if (esFormat == CDL)
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{
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spcHierWriteValue(hc, dev);
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subdone = spcHierWriteSubParam(hc, dev);
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}
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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@ -1037,7 +1091,10 @@ spcdevHierVisit(
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else
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{
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if (esFormat == CDL)
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{
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spcHierWriteValue(hc, dev);
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subdone = spcHierWriteSubParam(hc, dev);
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}
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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if (esScale < 0)
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@ -1086,7 +1143,10 @@ spcdevHierVisit(
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else
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{
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if (esFormat == CDL)
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{
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spcHierWriteValue(hc, dev);
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subdone = spcHierWriteSubParam(hc, dev);
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}
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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if (esScale < 0)
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@ -2030,6 +2030,48 @@ topVisit(
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fprintf(esSpiceF, "\n");
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}
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/*
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* ----------------------------------------------------------------------------
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*
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* spcWriteValue ---
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*
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* Special handling for CDL format: Output any resistor or capacitor value,
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* value only, no parameter name.
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*
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* ----------------------------------------------------------------------------
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*/
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bool
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spcWriteValue(
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Dev *dev, /* Dev being output */
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HierName *hierName) /* Hierarchical path down to this dev */
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{
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DevParam *plist;
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plist = efGetDeviceParams(EFDevTypes[dev->dev_type]);
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while (plist != NULL)
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{
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switch (plist->parm_type[0])
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{
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case 'r':
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if (*(plist->parm_name) == '\0')
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{
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fprintf(esSpiceF, " ");
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esSIvalue(esSpiceF, (double)dev->dev_res);
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}
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break;
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case 'c':
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if (*(plist->parm_name) == '\0')
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{
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fprintf(esSpiceF, " ");
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esSIvalue(esSpiceF, (double)dev->dev_res);
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}
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break;
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}
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plist = plist->parm_next;
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}
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}
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/*
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* ----------------------------------------------------------------------------
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*
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@ -2365,12 +2407,18 @@ spcWriteParams(
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* scale * esScale * 1.0E-6);
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break;
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case 'r':
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)dev->dev_res);
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if (*(plist->parm_name) != '\0')
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{
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)dev->dev_res);
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}
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break;
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case 'c':
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)dev->dev_cap);
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if (*(plist->parm_name) != '\0')
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{
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fprintf(esSpiceF, " %s=", plist->parm_name);
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esSIvalue(esSpiceF, (double)dev->dev_cap);
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}
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break;
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}
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plist = plist->parm_next;
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@ -2442,7 +2490,10 @@ esOutputResistor(
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{
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bool subdone = FALSE;
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if (esFormat == CDL)
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{
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spcWriteValue(dev, hierName);
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subdone = spcWriteSubParam(dev, hierName);
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}
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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if (esScale < 0)
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@ -3021,7 +3072,10 @@ spcdevVisit(
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else
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{
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if (esFormat == CDL)
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{
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spcWriteValue(dev, hierName);
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subdone = spcWriteSubParam(dev, hierName);
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}
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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if (esScale < 0)
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@ -3066,7 +3120,10 @@ spcdevVisit(
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else
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{
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if (esFormat == CDL)
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{
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spcWriteValue(dev, hierName);
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subdone = spcWriteSubParam(dev, hierName);
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}
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fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
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if (esScale < 0)
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@ -2918,8 +2918,6 @@ extOutputDevices(def, transList, outFile)
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else if (hasModel) /* SPICE semiconductor resistor */
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{
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fprintf(outFile, " %d %d", length, width);
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if (subsName != NULL)
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fprintf(outFile, " \"%s\"", subsName);
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}
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else /* regular resistor */
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fprintf(outFile, " %g", dres / 1000.0); /* mOhms -> Ohms */
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@ -2932,6 +2930,11 @@ extOutputDevices(def, transList, outFile)
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fprintf(outFile, " \"%s\"", (subsName == NULL) ?
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"None" : subsName);
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}
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else if (hasModel)
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{
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if (subsName != NULL)
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fprintf(outFile, " \"%s\"", subsName);
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}
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break;
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case DEV_CAP:
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@ -3027,8 +3030,6 @@ extOutputDevices(def, transList, outFile)
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}
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else
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fprintf(outFile, " %d %d", length, width);
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if (subsName != NULL)
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fprintf(outFile, " \"%s\"", subsName);
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}
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extOutputDevParams(reg, devptr, outFile, length, width,
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@ -3039,6 +3040,8 @@ extOutputDevices(def, transList, outFile)
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fprintf(outFile, " \"%s\"", (subsName == NULL) ?
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"None" : subsName);
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}
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else if (subsName != NULL)
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fprintf(outFile, " \"%s\"", subsName);
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}
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else
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{
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