Additional modification to write out a resistor or capacitor value

as-is, without a parameter name and before any device model name or
substrate pin, according to CDL syntax, if the parameter has been
specified without a parameter name (e.g., "r=" instead of "r=r").
Corrected an error in the extract code which put the substrate node
name in front of parameters instead of after.  This was previously
unexercised because only in CDL format does a resistor or capacitor
model have parameters listed by name.

ext2spice/ext2hier.c

@@ -126,6 +126,50 @@ GetHierNode(
     return(nn->efnn_node);
 }
 
+/*
+ * ----------------------------------------------------------------------------
+ *
+ * spcHierWriteValue ---
+ *
+ * Special case of spcHierWriteParams() below.  Only check for 'r' or 'c'
+ * parameters which have no parameter name.  Write out the given value,
+ * which in the case of CDL format is written out after the pins but before
+ * everything else, arbitrarily.
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+void
+spcHierWriteValue(
+    HierContext *hc,
+    Dev *dev)           /* Dev being output */
+{
+    DevParam *plist;
+
+    plist = efGetDeviceParams(EFDevTypes[dev->dev_type]);
+    while (plist != NULL)
+    {
+	switch (plist->parm_type[0])
+	{
+	    case 'r':
+		if (*(plist->parm_name) == '\0')
+		{
+		    fprintf(esSpiceF, " ");
+		    esSIvalue(esSpiceF, (double)(dev->dev_res));
+		}
+		break;
+	    case 'c':
+		if (*(plist->parm_name) == '\0')
+		{
+		    fprintf(esSpiceF, " ");
+		    esSIvalue(esSpiceF, (double)(dev->dev_cap));
+		}
+		break;
+	}
+	plist = plist->parm_next;
+    }
+}
+
 /*
  * ----------------------------------------------------------------------------
  *
@@ -164,6 +208,7 @@ spcHierWriteSubParam(
 				dev->dev_type, esSpiceF);
 		    retvalue = TRUE;
 		}
+		break;
 	}
 	plist = plist->parm_next;
     }
@@ -423,12 +468,18 @@ spcHierWriteParams(
 				* scale * esScale * 1.0E-6);
 		break;
 	    case 'r':
-		fprintf(esSpiceF, " %s=", plist->parm_name);
+		if (*(plist->parm_name) != '\0')
-		esSIvalue(esSpiceF, (double)(dev->dev_res));
+		{
+		    fprintf(esSpiceF, " %s=", plist->parm_name);
+		    esSIvalue(esSpiceF, (double)(dev->dev_res));
+		}
 		break;
 	    case 'c':
-		fprintf(esSpiceF, " %s=", plist->parm_name);
+		if (*(plist->parm_name) != '\0')
-		esSIvalue(esSpiceF, (double)(dev->dev_cap));
+		{
+		    fprintf(esSpiceF, " %s=", plist->parm_name);
+		    esSIvalue(esSpiceF, (double)(dev->dev_cap));
+		}
 		break;
 	}
 	plist = plist->parm_next;
@@ -509,7 +560,10 @@ esOutputHierResistor(
 	bool subdone = FALSE;
 
 	if (esFormat == CDL)
+	{
+	    spcHierWriteValue(hc, dev);
 	    subdone = spcHierWriteSubParam(hc, dev);
+	}
 
 	fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
 
@@ -1037,7 +1091,10 @@ spcdevHierVisit(
 	    else
 	    {
 		if (esFormat == CDL)
+		{
+		    spcHierWriteValue(hc, dev);
 		    subdone = spcHierWriteSubParam(hc, dev);
+		}
 		fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
 
 		if (esScale < 0)
@@ -1086,7 +1143,10 @@ spcdevHierVisit(
 	    else
 	    {
 		if (esFormat == CDL)
+		{
+		    spcHierWriteValue(hc, dev);
 		    subdone = spcHierWriteSubParam(hc, dev);
+		}
 		fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
 
 		if (esScale < 0)

ext2spice/ext2spice.c

@@ -2030,6 +2030,48 @@ topVisit(
     fprintf(esSpiceF, "\n");
 }
 
+/*
+ * ----------------------------------------------------------------------------
+ *
+ * spcWriteValue ---
+ *
+ * Special handling for CDL format:  Output any resistor or capacitor value,
+ * value only, no parameter name.
+ *
+ * ----------------------------------------------------------------------------
+ */
+
+bool
+spcWriteValue(
+    Dev *dev,		/* Dev being output */
+    HierName *hierName)	/* Hierarchical path down to this dev */
+{
+    DevParam *plist;
+
+    plist = efGetDeviceParams(EFDevTypes[dev->dev_type]);
+    while (plist != NULL)
+    {
+	switch (plist->parm_type[0])
+	{
+	    case 'r':
+		if (*(plist->parm_name) == '\0')
+		{
+		    fprintf(esSpiceF, " ");
+		    esSIvalue(esSpiceF, (double)dev->dev_res);
+		}
+		break;
+	    case 'c':
+		if (*(plist->parm_name) == '\0')
+		{
+		    fprintf(esSpiceF, " ");
+		    esSIvalue(esSpiceF, (double)dev->dev_res);
+		}
+		break;
+	}
+	plist = plist->parm_next;
+    }
+}
+
 /*
  * ----------------------------------------------------------------------------
  *
@@ -2365,12 +2407,18 @@ spcWriteParams(
 				* scale * esScale * 1.0E-6);
 		break;
 	    case 'r':
-		fprintf(esSpiceF, " %s=", plist->parm_name);
+		if (*(plist->parm_name) != '\0')
-		esSIvalue(esSpiceF, (double)dev->dev_res);
+		{
+		    fprintf(esSpiceF, " %s=", plist->parm_name);
+		    esSIvalue(esSpiceF, (double)dev->dev_res);
+		}
 		break;
 	    case 'c':
-		fprintf(esSpiceF, " %s=", plist->parm_name);
+		if (*(plist->parm_name) != '\0')
-		esSIvalue(esSpiceF, (double)dev->dev_cap);
+		{
+		    fprintf(esSpiceF, " %s=", plist->parm_name);
+		    esSIvalue(esSpiceF, (double)dev->dev_cap);
+		}
 		break;
 	}
 	plist = plist->parm_next;
@@ -2442,7 +2490,10 @@ esOutputResistor(
     {
 	bool subdone = FALSE;
 	if (esFormat == CDL)
+	{
+	    spcWriteValue(dev, hierName);
 	    subdone = spcWriteSubParam(dev, hierName);
+	}
 	fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
 
 	if (esScale < 0)
@@ -3021,7 +3072,10 @@ spcdevVisit(
 	    else
 	    {
 		if (esFormat == CDL)
+		{
+		    spcWriteValue(dev, hierName);
 		    subdone = spcWriteSubParam(dev, hierName);
+		}
 		fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
 
 		if (esScale < 0)
@@ -3066,7 +3120,10 @@ spcdevVisit(
 	    else
 	    {
 		if (esFormat == CDL)
+		{
+		    spcWriteValue(dev, hierName);
 		    subdone = spcWriteSubParam(dev, hierName);
+		}
 		fprintf(esSpiceF, " %s", EFDevTypes[dev->dev_type]);
 
 		if (esScale < 0)

extract/ExtBasic.c

@@ -2918,8 +2918,6 @@ extOutputDevices(def, transList, outFile)
 		else if (hasModel)	/* SPICE semiconductor resistor */
 		{
 		    fprintf(outFile, " %d %d", length, width);
-		    if (subsName != NULL)
-			fprintf(outFile, " \"%s\"", subsName);
 		}
 		else		/* regular resistor */
 		    fprintf(outFile, " %g", dres / 1000.0); /* mOhms -> Ohms */
@@ -2932,6 +2930,11 @@ extOutputDevices(def, transList, outFile)
 		    fprintf(outFile, " \"%s\"", (subsName == NULL) ?
 				"None" : subsName);
 		}
+		else if (hasModel)
+		{
+		    if (subsName != NULL)
+			fprintf(outFile, " \"%s\"", subsName);
+		}
 		break;
 
 	    case DEV_CAP:
@@ -3027,8 +3030,6 @@ extOutputDevices(def, transList, outFile)
 			}
 			else
 			    fprintf(outFile, " %d %d", length, width);
-			if (subsName != NULL)
-			    fprintf(outFile, " \"%s\"", subsName);
 		    }
 
 		    extOutputDevParams(reg, devptr, outFile, length, width,
@@ -3039,6 +3040,8 @@ extOutputDevices(def, transList, outFile)
 			fprintf(outFile, " \"%s\"", (subsName == NULL) ?
 				"None" : subsName);
 		    }
+		    else if (subsName != NULL)
+			fprintf(outFile, " \"%s\"", subsName);
 		}
 		else
 		{