Corrected two errors related to extraction:

(1) All parasitic extraction:  The "defaultperimeter" and the
"defaultsideoverlap" commands were failing to exempt types other
than space from the list of edges from which fringing capacitance
is evaluated.  This led to incorrectly considering the boundary
between types such as poly and nfet, or between metal1 and rm1,
to be sidewall areas.  The "default" statements are supposed to
consider the most common usage, so the code has been changed to
make sure that only edges from material to space are considered.
In the rare case that a material-to-material edge in the same
plane should be considered a sidewall, the non-default statements
can be used instead.
(2) Hierarchical parasitic extraction:  Magic was incorrectly
adding capacitances for subcells which had been output already
when handling subcircuit connections during "ext2spice".  This
duplicate counting has been eliminated.

extract/ExtTech.c

@@ -1368,7 +1368,7 @@ ExtTechSimplePerimCap(argc, argv)
 
     if (ExtCurStyle->exts_planeOrderStatus != seenPlaneOrder)
     {
-	TechError("Cannot parse area cap line without plane ordering!\n");
+	TechError("Cannot parse perimeter cap line without plane ordering!\n");
 	return;
     }
 
@@ -1376,9 +1376,14 @@ ExtTechSimplePerimCap(argc, argv)
     TTMaskSetMask(allExtractTypes, &types);
     plane1 = DBTechNoisyNamePlane(argv[2]);
 
-    TTMaskCom2(&nottypes, &types);
+    /* As part of the "simple perimeter" simplifications, "nottypes" can
+     * only be space.  This prevents perimeter edges from being seen
+     * between, e.g., poly and transistor gates, or metal and metal
+     * resistors.
+     */
+    TTMaskSetOnlyType(&nottypes, TT_SPACE);
+
     TTMaskAndMask(&types, &DBPlaneTypes[plane1]);
-    TTMaskAndMask(&nottypes, &DBPlaneTypes[plane1]);
 
     capVal = aToCap(argv[argc - 1]);
 
@@ -1632,7 +1637,7 @@ ExtTechSimpleOverlapCap(argv)
 
     if (ExtCurStyle->exts_planeOrderStatus != seenPlaneOrder)
     {
-	TechError("Cannot parse area cap line without plane ordering!\n");
+	TechError("Cannot parse overlap cap line without plane ordering!\n");
 	return;
     }
 
@@ -1732,7 +1737,7 @@ ExtTechSimpleSideOverlapCap(argv)
 
     if (ExtCurStyle->exts_planeOrderStatus != seenPlaneOrder)
     {
-	TechError("Cannot parse area cap line without plane ordering!\n");
+	TechError("Cannot parse side overlap cap line without plane ordering!\n");
 	return;
     }
 
@@ -1740,9 +1745,14 @@ ExtTechSimpleSideOverlapCap(argv)
     TTMaskSetMask(allExtractTypes, &types);
     plane1 = DBTechNoisyNamePlane(argv[2]);
 
-    TTMaskCom2(&nottypes, &types);
+    /* As part of the "simple sideoverlap" simplifications, "nottypes"
+     * can only be space.  This prevents perimeter edges from being
+     * seen between, e.g., poly and transistor gates, or metal and
+     * metal resistors.
+     */
+    TTMaskSetOnlyType(&nottypes, TT_SPACE);
+
     TTMaskAndMask(&types,    &DBPlaneTypes[plane1]);
-    TTMaskAndMask(&nottypes, &DBPlaneTypes[plane1]);
 
     DBTechNoisyNameMask(argv[3], &ov);
     TTMaskSetMask(allExtractTypes, &ov);