3257 lines
108 KiB
Plaintext
3257 lines
108 KiB
Plaintext
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/* --------------------------------------------------------------------*
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* *
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* scmos.tech -- MOSIS Scalable CMOS (SCMOS) Magic technology file. *
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* *
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* MOSIS distribution Version 8.2 *
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* *
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* Defines the MOSIS 0.6/0.8/1.0/1.2/2.0 micron Scalable CMOS *
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* (SCMOS) technology. *
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* *
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* (C) Copyright 1992, 1993, 1994, 1995 by *
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* *
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* Jen-I Pi pi@isi.edu *
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* The MOSIS Service *
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* USC Information Sciences Institute *
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* 4676 Admiralty Way *
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* Marina del Rey, CA 90292 *
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* voice: (310) 822-1511 x640, fax: (310)823-5624 *
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* *
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* All Rights Reserved. *
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* Last Modified Date: 04/26/1995 *
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* *
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* Permission to use, copy, modify, and distribute this technology *
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* file and its associated documentation for any purpose and without *
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* fee is hereby granted, provided that the above copyright notice *
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* appears in all copies and that both that copyright notice and this *
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* permission notice appear in supporting documentation, and that the *
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* name of the University of Southern California not be used in *
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* advertising or publicity pertaining to distribution of this *
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* technology file without specific, written prior permission. *
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* The University of Southern California makes no representations *
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* about the suitability of this technology file for any purpose. *
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* This technology file is provided "as is" without express or implied *
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* warranty and the University of Southern California retains the *
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* right to change its content at any time without notice any other *
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* party. *
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* *
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* THE UNIVERSITY OF SOUTHERN CALIFORNIA DISCLAIMS ALL WARRANTIES WITH *
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* REGARD TO THIS TECHNOLOGY FILE, INCLUDING ALL IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE UNIVERSITY OF *
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* SOUTHERN CALIFORNIA BE LIABLE FOR ANY SPECIAL, INDIRECT OR *
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS *
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* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, *
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* NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN *
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS TECHNOLOGY FILE. *
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* *
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* ------------------------------------------------------------------- */
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/* --------------------------------------------------------------------*
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* Some of the characteristics of this technology are: *
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* *
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* 1. 3 levels of metal - for HP's CMOS26B (lambda=0.5) and CMOS26G *
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* (lambda=0.4) and CMOS14TB (lambda=0.35 or 0.3) processes *
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* 3 levels of metal stack via - for IBM's CMSX2185 (lambda=0.4) *
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* process *
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* 2 levels of metal interconnection for all other technologies *
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* 2. 2 levels of poly - for ORBIT's low-noise analog process *
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* second poly is used for poly-capacitor or electrode fet (efet) *
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* 3. Vertical NPN transistor, BCCD device, Floating-gate device for *
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* ORBIT's low-noise anaolog process *
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* 4. All contacts are composite (with the necessary enclosure) *
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* 5. No stacked contacts (all contacts are to 1st-level metal) *
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* 6. An open layer is added for fabrication of micromachined devices *
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* as in Janet C. Marshall's paper in IEEE Circuit and Devices, *
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* Vol. 8, N0. 6, 1992. *
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* This layer is currently NOT available for standard MOSIS SCMOS *
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* techonology installation. You need to define OPEN with the C- *
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* preprocessor for installation. See README file for detail... *
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* 7 A pstop layer is used also in micromachineing device fabrication *
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* to stop the EDP etchant as used in Marshall's article. *
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* 8 A Cap-well (cwell) for HP's CMOS34 (lambda=0.6) process, It is *
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* used for consctruction of linear capacitors *
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* Must be drawn explicitly *
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* 9. Wells (Pwell or Nwell) can be implicit or explicit in the layout *
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* and both types of diffusion must have well contacts *
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*10. Painting Nwell over N-type diffusion will result in P-type *
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* diffusion *
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*11. Scalable with Default to be 2.0 micron rules for Nwell process *
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*12. Substrate contacts must be 3 units away from gates *
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*13. Stacked via supported through special compiled option -DSTACKVIA *
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* for IBM process. *
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* *
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* Revision 8.2.8 (pi) *
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* fix CCD CIF input style for "bd" layer. *
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* 12/13/95 pi@isi.edu *
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* Revision 8.2.7 (pi) *
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* Add Magic 6.4.4 new extraction plane orders. *
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* 07/25/95 pi@isi.edu *
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* Revision 8.2.5 (pi) *
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* Fix some typos... *
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* 05/12/95 pi@isi.edu *
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* Revision 8.2.4 (pi) *
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* Fix CBA generation for pbase and add extension rules for pbase *
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* as resistors. *
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* Gratitude goes to Tetsuya Kajita (kaj@ssac.yamatake.co.jp) *
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* 04/26/95 pi@isi.edu *
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* Revision 8.2.3 (pi) *
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* fix for SUBMICRON DRC rule. *
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* Thanks goes to Toby Schaffer (jtschaff@eos.ncsu.edu) *
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* 04/06/95 pi@isi.edu *
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* Revision 8.2.2 (pi) *
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* add XP GDS official number to fix CIF input problem for "pad". *
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* Thanks goes to Brian Kingsbury (bedk@ICSI.Berkeley.EDU). *
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* 04/03/95 pi@isi.edu *
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* Revision 8.2.1 (pi) *
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* Some fixes for CMOS14B CIF output section. *
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* 03/21/95 pi@isi.edu *
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* Revision 8.2.0 (pi) *
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* support for HP CMOS26G and CMOS14TB process. *
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* 03/15/95 pi@isi.edu *
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* Revision 8.1.1 (pi) *
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* add connection of "ndiff" to "psd". Thank goes to Alireza Moini*
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* (moini@eleceng.adelaide.edu.au). *
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* 12/21/94 pi@isi.edu *
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* Revision 8.1.0 (pi) *
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* major revision of bipolar transistor rules. It now support *
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* both ORBIT 2.0 and 1.2 micron processes. NOTE: active layer *
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* for pbase is now generated in CIF file explicitly. *
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* 10/31/94 pi@isi.edu *
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* Revision 8.0.7 (pi) *
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* remove both VTI and IBM support *
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* 10/10/94 pi@isi.edu *
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* Revision 8.0.7 (pi) *
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* compose for high-voltage transistors corrected. Thank goes to *
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* Bob Durie (bobd@ee.cornell.edu) *
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* 8/25/94 pi@isi.edu *
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* Revision 8.0.6 (pi) *
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* DRC rule 2.2 add allNOhmic to allNOhmic and allPOhmic to *
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* allPOhmic rule. Thank goes to Shih-Lien Lu. *
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* (sllu@caleb.ECE.ORST.EDU) *
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* 6/28/94 pi@isi.edu *
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* Revision 8.0.5 (pi) *
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* DRC rule 3.5 reverse back to old style to avoid a mischeck on *
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* corners. Thank goes to Wen-King Su. *
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* (wen-king@vlsi.cs.caltech.edu) *
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* 4/20/94 pi@isi.edu *
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* Revision 8.0.4 (pi) *
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* SCPE20(ORB) extraction P-well sheet resistance fixed. Thank *
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* goes to Nagendra Shivakumar (nshivaku@phyast.nhn.uoknor.edu). *
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* 3/04/94 pi@isi.edu *
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* Revision 8.0.3 (pi) *
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* Wellcap drawing problem fixed. Thank goes to Mario Aranha *
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* (mario@cad4.lbl.gov). *
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* 2/03/94 pi@isi.edu *
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* Revision 8.0.2 (pi) *
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* CIF read fix for linear capacitor. Thank goes to Issy Kipnis *
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* (kipnis@cad4.lbl.gov). *
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* 2/03/94 pi@isi.edu *
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* Revision 8.0.1 (pi) *
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* DRC updates for separate diffusion width check. Thank goes to *
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* John Poulton (jp@cs.unc.edu). *
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* 10/04/93 pi@isi.edu *
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* Revision 8.0.0 (pi) *
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* DRC revision 8 installed and layer support for High-Voltage *
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* MOSFETs for SCNA16 process. *
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* 10/04/93 pi@isi.edu *
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* Revision 7.4.0 (pi) *
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* Brand new extraction section and other fixes :-) *
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* 10/01/93 pi@isi.edu *
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* Revision 7.3.3 (pi) *
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* pbc surrounding rule fixed. 4.1.c fixed also *
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* 6/01/93 pi@isi.edu *
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* Revision 7.3.2 (pi) *
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* exchnage CCD and CBA calma (GDS) number to the correct setting *
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* 4/27/93 pi@isi.edu *
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* Revision 7.3.1 (pi) *
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* Various DRC rule changes contributed by Barry Boes at AuE *
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* (boes@corona.AuE.com). *
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* allNDiff/allPOhmic in connection section update, thanks go to *
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* Brian Kingsbury from Bekerley (bedk@icsi.berkeley.edu). *
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* 3/30/93 pi@isi.edu *
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* Revision 7.3.0 (pi) *
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* add three new layers intended for ESD preotection devices *
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* remove the temporary "pad2" layer, now all pads use "pad" *
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* CIFin and CIFout now in templates, thank goes to Shih-Lien Lu *
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* at Origon State Univ. sllu@caleb.ECE.ORST.EDU. *
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* Some design rule changes (relabeling for doc)... *
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* 3/19/93 pi@isi.edu *
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* Revision 7.2.2 (pi) *
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* change all "bloat-min" select generation back to "bloat-or" *
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* restore all lambda=0.8 style since some people use ORBIT's run *
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* though MOSIS does NOT provide HP's process anymore *
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* 3/09/93 pi@isi.edu *
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* Revision 7.2.1 (pi) *
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* add missing Cifinput "pbase" layer for lambda=1.0(oldnwell) *
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* style. Thank goes to Brian Von Herzen at Synaptics, Inc. *
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* 2/18/93 pi@isi.edu *
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* Revision 7.2.0 (pi) *
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* A serious bug in CIF well generation is fixed... *
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* 1/14/93 pi@isi.edu *
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* Revision 7.1.4 (pi) *
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* Remove lambda=1.5 and lambda=0.8 technology which are not *
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* provided by MOSIS any more. *
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* 1/12/93 pi@isi.edu *
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* Revision 7.1.3 (pi) *
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* Add pstop layer and the corresponding CIFin CIFout stuff *
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* Reverse the last change about CCA layer under pad for CMOS26B *
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* 1/08/93 pi@isi.edu *
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* Revision 7.1.2 (pi) *
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* Various problem fix... and make the "open" layer as an option *
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* Reverse the last change about CCA layer under pad for CMOS26B *
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* 12/29/92 pi@isi.edu *
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* Revision 7.1.1 (pi) *
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* A series bug fix for HP's CMOS26B pad layers - remove CCA CIF *
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* layer. Thank goes to ndu@aue.com *
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* 12/12/92 pi@isi.edu *
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* Revision 7.1.0 (pi) *
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* A new layer "open" for micromachined device fabracation. *
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* Thanks goes to Janet Marchall from NIST. *
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* (marshall@sed.eeel.nist.gov) *
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* 12/15/92 pi@isi.edu *
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* Revision 7.0.4 (pi) *
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* C-preprocessing fix. Thanks goes to Jeffrey C. Gealow form *
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* MIT (jgealow@mtl.mit.edu). *
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* 10/20/92 pi@isi.edu *
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* Revision 7.0.3 (pi) *
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* Colorversatec support. Thanks got to Jeffrey C. Gealow form *
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* MIT (jgealow@mtl.mit.edu). *
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* 10/8/92 pi@isi.edu *
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* Revision 7.0.2 (pi) *
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* Separate 'spacing allWell...' rule into two rules to avoid *
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* well adjacency problem... *
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* 10/2/92 pi@isi.edu *
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* Revision 7.0.1 (pi) *
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* CIFoutput for "pad2" layer, CCA contact fix, CIFinput for HP's *
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* 1.0 um process... *
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* 9/28/92 pi@isi.edu *
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* Revision 7.0 (pi) *
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* Major revision which includes *
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* HP's cap_well and well-capacitance, NPN & BCCD DRC rules... *
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* 9/22/92 pi@isi.edu *
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* Revision 6.2.0 (pi) *
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* Merging 'scmos26.tech' into scmos.tech *
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* 9/7/92 pi@isi.edu *
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* Revision 6.1.4 (pi) *
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* Select CIF layers generation is revised based on Brian *
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* Kingsbury's (bedk@icsi.berkeley.edu) notice of inconsistency *
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* 9/4/92 pi@isi.edu *
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* Revision 6.1.3 (pi) *
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* Install MITRE's (Mike Butler) fix for CIFinput "cap" layer and *
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* poly1/poly2 crossing in DRC section *
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* 9/3/92 pi@isi.edu *
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* Revision 6.1.2 (pi) *
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* Fixed metal2 contact on falt surface bug for poly2 layer *
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* 8/3/92 pi@lepton.isi.edu *
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* Revision 6.1.1 (pi) *
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* fixed CIFoutput CSP layer bug for lambda=0.8(gen) technology *
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* 4/13/92 pi@lepton.isi.edu *
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* Revision 6.1.0 (pi) *
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* add implant plane for Buried CCD devices *
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* both cifin and cifoutput are changed correspondingly *
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* Revision 6.0.2 (pi) *
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* remove bug for nbdc not generate CMF in cifoutput section *
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* Revision 6.0.1 (sllu) *
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* added CX for collector layer *
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* Revised for Magic Version 6. *
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* Revision 6.0 90/05/11 20:12:34 pi *
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* include color versatech support *
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* eliminated active2 plane *
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* (rule version # 5.01 (S. Lu) = rule 5.0 + mod. for cc spacing *
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* (rule version # 5.0 (Shih-Lien Lu sllu@MOSIS.EDU) 8/15/89) *
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* (rule 5.0 = rule 4.01 + new layers for analog process *
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* (rule 4.01 = rule 4.0 + comments + cifout style lambda=0.8(pwell) *
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* (correction made by L. McMurchie of UW) *
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* (rule 4.0 = rule 3.1 + new layer : electrode) *
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* (rule 3.1 = rule 3.0 + new cifout method for select layers ) *
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* (design can be more compact now with this version ) *
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* (layout should be upward compatible:: you old layout will not) *
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* (flag any drc violations) *
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* (rule 3.0 = rule 2.0 + rev #6 + new cifin section for new nwell) *
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* *
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* (rule version # 2.0 10/28/87) *
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* (rule 2.0 = rule 1.9 + modification to extract section *
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* (rule 1.9 = rule 1.82 + additions of two more CIF in/output styles *
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* (rule 1.82 = rule 1.81+ modification of drc #4.1 & cifoutput of *
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* wells *
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* (rule 1.81 = rule 1.8 + modification on line 1761 *
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* (rule 1.8 = rule 1.7 + Rev 5 of the SCMOS rules) *
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* (difference from rule 1.7: *
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* (1) well width = 9 lambda *
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* (2) N well process accepts both N and P selects *
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* ------------------------------------------------------------------- */
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/* Definition for actives */
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/* NOTE: Some version of cpp may have problem with two consective tabs
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* or even two consective space... So we put only single space
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* here... */
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|||
|
|
#define allNDiff ndiff,ndc/a
|
|||
|
|
#define allPDiff pdiff,pdc/a
|
|||
|
|
#define allNActive ndiff,ndc/a,nfet,enfet,nffet,wcap
|
|||
|
|
#define allPActive pdiff,pdc/a,pfet,epfet,pffet
|
|||
|
|
#define allNOhmic nsd,nsc/a
|
|||
|
|
#define allPOhmic psd,psc/a
|
|||
|
|
#define allOhmic allNOhmic,allPOhmic
|
|||
|
|
#define allBiNDiff emit,emc/a,col,clc/a
|
|||
|
|
#define allBiPDiff pbase,pbc/a
|
|||
|
|
#define allBiDiff allBiNDiff,allBiPDiff
|
|||
|
|
#define allCCDiff bd,nbd,nbdc/a
|
|||
|
|
#define allDiff allNDiff,allPDiff
|
|||
|
|
#define allActive allNActive,allPActive,allOhmic
|
|||
|
|
#define PNplus ndiff,pdiff,ndc/a,pdc/a
|
|||
|
|
#define allHVNDiff hndiff,hndc/a
|
|||
|
|
#define allHVPDiff hpdiff,hpdc/a
|
|||
|
|
#define allHVNOhmic hnsd,hnsc/a
|
|||
|
|
#define allHVPOhmic hpsd,hpsc/a
|
|||
|
|
#define allHVDiff allHVNDiff,allHVPDiff
|
|||
|
|
#define allHVOhmic allHVNOhmic,allHVPOhmic
|
|||
|
|
|
|||
|
|
/* first poly without those overlapped with the second */
|
|||
|
|
#define allP poly,pc/a
|
|||
|
|
#define allP1 poly,pc/a,nfet,pfet,wcap
|
|||
|
|
/* all first poly */
|
|||
|
|
#define allPoly allP1,cap,capc/a,nffet,pffet
|
|||
|
|
/* second poly without those overlapped with the first */
|
|||
|
|
#define allP2 poly2,ec/a,enfet,epfet
|
|||
|
|
/* all second poly */
|
|||
|
|
#define allPoly2 allP2,cap,capc/a,nffet,pffet,hnfet,hpfet
|
|||
|
|
|
|||
|
|
/* MOSFETs */
|
|||
|
|
#define NFet nfet,enfet,nffet
|
|||
|
|
#define PFet pfet,epfet,pffet
|
|||
|
|
#define allFet NFet,PFet
|
|||
|
|
|
|||
|
|
/* Definitions for contacts */
|
|||
|
|
#define DiffCut pdc,ndc,psc,nsc
|
|||
|
|
#define HVDiffCut hpdc,hndc,hpsc,hnsc
|
|||
|
|
#define PolyCut pc
|
|||
|
|
#define CapCut ec,capc
|
|||
|
|
#define BiCut clc,emc,pbc
|
|||
|
|
#define allCut DiffCut,HVDiffCut,PolyCut,CapCut,nbdc
|
|||
|
|
|
|||
|
|
/* Definitions for metals */
|
|||
|
|
#define DiffMetal pdc/m1,ndc/m1,psc/m1,nsc/m1
|
|||
|
|
#define HVDiffMetal hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1
|
|||
|
|
#define PolyMetal pc/m1,ec/m1,capc/m1
|
|||
|
|
#define BiMetal clc/m1,emc/m1,pbc/m1
|
|||
|
|
#define CCDMetal nbdc/m1
|
|||
|
|
#define allMetal1 DiffMetal,HVDiffMetal,PolyMetal,BiMetal,CCDMetal,m1,m2c/m1,gc
|
|||
|
|
#define allMetal2 m2,m2c/m2,m3c/m2,pad
|
|||
|
|
#define allMetal3 m3,m3c/m3
|
|||
|
|
|
|||
|
|
/* All types containing metal, on their respective home planes */
|
|||
|
|
#define homeMetal1 allCut,m1,m2c,gc
|
|||
|
|
|
|||
|
|
/* Definitions for wells */
|
|||
|
|
#define allWell nwell,pwell
|
|||
|
|
#define allNwell nwell,nsc,nsd
|
|||
|
|
#define allPwell pwell,psc,psd
|
|||
|
|
#define allHVNwell hnwell,hnsc,hnsd
|
|||
|
|
#define allHVPwell hpwell,hpsc,hpsd
|
|||
|
|
|
|||
|
|
|
|||
|
|
tech
|
|||
|
|
format 28
|
|||
|
|
scmos
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
#if V4 || V5
|
|||
|
|
version
|
|||
|
|
version 8.2.8
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
description "MOSIS Scalable CMOS Technology for HP CMOS26G and CMOS14B processes"
|
|||
|
|
#else /* TIGHTMETAL */
|
|||
|
|
#ifdef IBMTECH
|
|||
|
|
description "MOSIS Scalable CMOS Technology for IBM"
|
|||
|
|
#else /* IBMTECH */
|
|||
|
|
#ifdef HPTECH
|
|||
|
|
description "MOSIS Scalable CMOS Technology for Tight Metal Rules"
|
|||
|
|
#else
|
|||
|
|
#ifndef WELL_ROUTE_CHECK
|
|||
|
|
description "MOSIS Scalable CMOS Technology for Standard Rules"
|
|||
|
|
#else
|
|||
|
|
description "MOSIS Scalable CMOS Technology for Standard Rules (No routing through wells)"
|
|||
|
|
#endif
|
|||
|
|
#endif /* HPTECH */
|
|||
|
|
#endif /* IBMTECH */
|
|||
|
|
#endif /* TIGHTMETAL */
|
|||
|
|
end
|
|||
|
|
#endif /* V4 */
|
|||
|
|
|
|||
|
|
planes
|
|||
|
|
well,w
|
|||
|
|
implant,i
|
|||
|
|
active,a
|
|||
|
|
metal1,m1
|
|||
|
|
metal2,m2
|
|||
|
|
#ifdef STACKVIA
|
|||
|
|
v2oxide,v2x
|
|||
|
|
#endif
|
|||
|
|
metal3,m3
|
|||
|
|
oxide,ox
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
types
|
|||
|
|
/* primary layers -16 */
|
|||
|
|
|
|||
|
|
well pwell,pw
|
|||
|
|
well nwell,nw
|
|||
|
|
well capwell,cwell,cw
|
|||
|
|
well highvoltnwell,hvnwell,hnwell,hnw
|
|||
|
|
well highvoltpwell,hvpwell,hpwell,hpw
|
|||
|
|
active polysilicon,red,poly,p
|
|||
|
|
active electrode,poly2,el,p2
|
|||
|
|
active capacitor,polycap,pcap,cap
|
|||
|
|
active wellcapacitor,wellcap,wcap
|
|||
|
|
active ndiffusion,ndiff,green
|
|||
|
|
active pdiffusion,pdiff,brown
|
|||
|
|
active highvoltndiffusion,hvndiff,hndiff
|
|||
|
|
active highvoltpdiffusion,hvpdiff,hpdiff
|
|||
|
|
metal1 metal1,m1,blue
|
|||
|
|
metal2 metal2,m2,purple
|
|||
|
|
metal3 metal3,m3,cyan
|
|||
|
|
|
|||
|
|
/* MOSFETs -8 */
|
|||
|
|
|
|||
|
|
active ntransistor,nfet
|
|||
|
|
active ptransistor,pfet
|
|||
|
|
active entransistor,enfet
|
|||
|
|
active eptransistor,epfet
|
|||
|
|
active doublentransistor,nfloating-gate,nfloatg,nfg,nffet
|
|||
|
|
active doubleptransistor,pfloating-gate,pfloatg,pfg,pffet
|
|||
|
|
active highvoltntransistor,hvnfet,hnfet
|
|||
|
|
active highvoltptransistor,hvpfet,hpfet
|
|||
|
|
|
|||
|
|
/* NPN transistor layers -3 */
|
|||
|
|
|
|||
|
|
active collector,coll,col,co,cl
|
|||
|
|
active emitter,emit,em
|
|||
|
|
active pbase,pb
|
|||
|
|
|
|||
|
|
/* layers for BCCD devices -2 */
|
|||
|
|
|
|||
|
|
implant bccdiffusion,bd
|
|||
|
|
active nbccdiffusion,nbd
|
|||
|
|
|
|||
|
|
/* Contacts between interconnection layers -13 */
|
|||
|
|
|
|||
|
|
active polycontact,pcontact,polycut,pc
|
|||
|
|
active ndcontact,ndiffcut,ndc
|
|||
|
|
active pdcontact,pdiffcut,pdc
|
|||
|
|
active highvoltndcontact,hndiffcut,hndc
|
|||
|
|
active highvoltpdcontact,hpdiffcut,hpdc
|
|||
|
|
active capcontact,ccontact,capc,cc
|
|||
|
|
active electrodecontact,econtact,ec,poly2contact,p2c
|
|||
|
|
active collectorcontact,colcontact,colc,coc,clc
|
|||
|
|
active emittercontact,emitcontact,emc
|
|||
|
|
active pbasecontact,pbcontact,pbc
|
|||
|
|
active nbccdiffcontact,nbdc
|
|||
|
|
metal1 m2contact,m2cut,m2c,via,v
|
|||
|
|
#ifdef STACKVIA
|
|||
|
|
v2x m3contact,m3cut,m3c,via2,v2
|
|||
|
|
#else
|
|||
|
|
metal2 m3contact,m3cut,m3c,via2,v2
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Well contacts -8 */
|
|||
|
|
/* pohmic and nohmic are included for compatibility */
|
|||
|
|
/* nwc, pwc, etc ... are included for compatibility */
|
|||
|
|
|
|||
|
|
active psubstratepcontact,ppcontact,ppc,pwcontact,pwc,psc
|
|||
|
|
active nsubstratencontact,nncontact,nnc,nwcontact,nwc,nsc
|
|||
|
|
active psubstratepdiff,ppdiff,pohmic,ppd,psd
|
|||
|
|
active nsubstratendiff,nndiff,nohmic,nnd,nsd
|
|||
|
|
|
|||
|
|
active highvoltpsubcontact,hpwcontact,hpsc
|
|||
|
|
active highvoltnsubcontact,hnwcontact,hnsc
|
|||
|
|
active highvoltpsubdiff,hpohmic,hpsd
|
|||
|
|
active highvoltnsubdiff,hnohmic,hnsd
|
|||
|
|
|
|||
|
|
/* Special tiles needed for ESD protection design -3 */
|
|||
|
|
active nplusdoping,ndoping,ndop
|
|||
|
|
active pplusdoping,pdoping,pdop
|
|||
|
|
metal1 genericcontact,gcontact,gc
|
|||
|
|
|
|||
|
|
/* Special tiles needed for micromachine fab. in CMOS -2 */
|
|||
|
|
oxide substrateopen,subopen,open
|
|||
|
|
oxide pdiffusionstop,pdiffstop,pstop
|
|||
|
|
|
|||
|
|
/* Additional stuff, used in pads. -2 */
|
|||
|
|
|
|||
|
|
metal2 pad
|
|||
|
|
oxide glass
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
contact
|
|||
|
|
/* polys */
|
|||
|
|
ec poly2 metal1
|
|||
|
|
cc cap metal1
|
|||
|
|
pc poly metal1
|
|||
|
|
/* active contacts */
|
|||
|
|
ndc ndiff metal1
|
|||
|
|
pdc pdiff metal1
|
|||
|
|
nsc nsd metal1
|
|||
|
|
psc psd metal1
|
|||
|
|
hndc hndiff metal1
|
|||
|
|
hpdc hpdiff metal1
|
|||
|
|
hnsc hnsd metal1
|
|||
|
|
hpsc hpsd metal1
|
|||
|
|
/* bipolar contacts */
|
|||
|
|
clc col metal1
|
|||
|
|
emc emit metal1
|
|||
|
|
pbc pbase metal1
|
|||
|
|
/* BCCD contact */
|
|||
|
|
nbdc nbd metal1
|
|||
|
|
/* vias */
|
|||
|
|
m2c metal1 metal2
|
|||
|
|
#ifdef STACKVIA
|
|||
|
|
m3c metal2 m3c metal3
|
|||
|
|
#else
|
|||
|
|
m3c metal2 metal3
|
|||
|
|
#endif
|
|||
|
|
/*
|
|||
|
|
pad metal1 metal2 metal3
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
styles
|
|||
|
|
styletype mos
|
|||
|
|
|
|||
|
|
/* wells */
|
|||
|
|
cwell 10
|
|||
|
|
nwell 12
|
|||
|
|
pwell 13
|
|||
|
|
hnwell 18
|
|||
|
|
hpwell 11
|
|||
|
|
/* poly */
|
|||
|
|
poly 1
|
|||
|
|
poly2 14
|
|||
|
|
/* diffusions */
|
|||
|
|
ndiff 2
|
|||
|
|
pdiff 4
|
|||
|
|
psd 5
|
|||
|
|
nsd 3
|
|||
|
|
hndiff 2
|
|||
|
|
hndiff 11
|
|||
|
|
hpdiff 4
|
|||
|
|
hpdiff 18
|
|||
|
|
hpsd 5
|
|||
|
|
hpsd 11
|
|||
|
|
hnsd 3
|
|||
|
|
hnsd 18
|
|||
|
|
ndop 2
|
|||
|
|
ndop 38
|
|||
|
|
pdop 4
|
|||
|
|
pdop 38
|
|||
|
|
/* transistors */
|
|||
|
|
nfet 6
|
|||
|
|
nfet 7
|
|||
|
|
pfet 8
|
|||
|
|
pfet 9
|
|||
|
|
|
|||
|
|
enfet 6
|
|||
|
|
enfet 30
|
|||
|
|
/* enfet 14 */
|
|||
|
|
epfet 8
|
|||
|
|
epfet 31
|
|||
|
|
/* epfet 14 */
|
|||
|
|
|
|||
|
|
nffet 6
|
|||
|
|
nffet 7
|
|||
|
|
/* nffet 14 */
|
|||
|
|
nffet 30
|
|||
|
|
pffet 8
|
|||
|
|
pffet 9
|
|||
|
|
/* pffet 14 */
|
|||
|
|
pffet 31
|
|||
|
|
|
|||
|
|
hnfet 6
|
|||
|
|
hnfet 7
|
|||
|
|
hnfet 30
|
|||
|
|
|
|||
|
|
hpfet 8
|
|||
|
|
hpfet 9
|
|||
|
|
hpfet 31
|
|||
|
|
/* base */
|
|||
|
|
pbase 15
|
|||
|
|
pbc 15
|
|||
|
|
pbc 20
|
|||
|
|
pbc 32
|
|||
|
|
/* emitter */
|
|||
|
|
emit 16
|
|||
|
|
emc 16
|
|||
|
|
emc 20
|
|||
|
|
emc 32
|
|||
|
|
/* collector */
|
|||
|
|
col 3
|
|||
|
|
clc 3
|
|||
|
|
clc 20
|
|||
|
|
clc 32
|
|||
|
|
/* capacitors */
|
|||
|
|
cap 1
|
|||
|
|
cap 14
|
|||
|
|
wcap 6
|
|||
|
|
wcap 10
|
|||
|
|
cc 1
|
|||
|
|
cc 14
|
|||
|
|
cc 20
|
|||
|
|
cc 32
|
|||
|
|
/* metals */
|
|||
|
|
metal1 20
|
|||
|
|
metal2 21
|
|||
|
|
metal3 22
|
|||
|
|
/* generic contact */
|
|||
|
|
gc 19
|
|||
|
|
/* poly contacts */
|
|||
|
|
pcontact 26
|
|||
|
|
pcontact 32
|
|||
|
|
ec 14
|
|||
|
|
ec 20
|
|||
|
|
ec 32
|
|||
|
|
/* diffusion contacts */
|
|||
|
|
ndc 2
|
|||
|
|
ndc 20
|
|||
|
|
ndc 32
|
|||
|
|
pdc 4
|
|||
|
|
pdc 20
|
|||
|
|
pdc 32
|
|||
|
|
psc 5
|
|||
|
|
psc 20
|
|||
|
|
psc 32
|
|||
|
|
nsc 3
|
|||
|
|
nsc 20
|
|||
|
|
nsc 32
|
|||
|
|
/* high-voltage diffusion contacts */
|
|||
|
|
hndc 2
|
|||
|
|
hndc 20
|
|||
|
|
hndc 32
|
|||
|
|
hndc 11
|
|||
|
|
hpdc 4
|
|||
|
|
hpdc 20
|
|||
|
|
hpdc 32
|
|||
|
|
hpdc 18
|
|||
|
|
hpsc 5
|
|||
|
|
hpsc 20
|
|||
|
|
hpsc 32
|
|||
|
|
hpsc 11
|
|||
|
|
hnsc 3
|
|||
|
|
hnsc 20
|
|||
|
|
hnsc 32
|
|||
|
|
hnsc 18
|
|||
|
|
/* vias */
|
|||
|
|
m2contact 20
|
|||
|
|
m2contact 21
|
|||
|
|
m2contact 33
|
|||
|
|
m3contact 21
|
|||
|
|
m3contact 22
|
|||
|
|
m3contact 37
|
|||
|
|
/* pads and overglass */
|
|||
|
|
pad 20
|
|||
|
|
pad 21
|
|||
|
|
pad 33
|
|||
|
|
pad 34
|
|||
|
|
glass 34
|
|||
|
|
/* CCDs */
|
|||
|
|
bd 17
|
|||
|
|
nbd 17
|
|||
|
|
nbd 3
|
|||
|
|
nbdc 3
|
|||
|
|
nbdc 17
|
|||
|
|
nbdc 20
|
|||
|
|
nbdc 32
|
|||
|
|
/* MEMs */
|
|||
|
|
open 2
|
|||
|
|
open 20
|
|||
|
|
pstop 8
|
|||
|
|
/* System */
|
|||
|
|
error_p 42
|
|||
|
|
error_s 42
|
|||
|
|
error_ps 42
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
compose
|
|||
|
|
/* MOSFET combination rules */
|
|||
|
|
compose nfet poly hndiff
|
|||
|
|
compose pfet poly hpdiff
|
|||
|
|
compose nfet poly ndiff
|
|||
|
|
compose pfet poly pdiff
|
|||
|
|
compose hnfet poly2 hndiff
|
|||
|
|
compose hpfet poly2 hpdiff
|
|||
|
|
compose enfet poly2 ndiff
|
|||
|
|
compose epfet poly2 pdiff
|
|||
|
|
compose nffet nfet poly2
|
|||
|
|
compose pffet pfet poly2
|
|||
|
|
compose nffet enfet poly
|
|||
|
|
compose pffet epfet poly
|
|||
|
|
compose cap poly poly2
|
|||
|
|
/* Transistor combination rules */
|
|||
|
|
paint clc col clc
|
|||
|
|
paint emc emit emc
|
|||
|
|
paint emc pbase emc
|
|||
|
|
/* Poly2 capacitor combination rules */
|
|||
|
|
paint poly2 poly cap
|
|||
|
|
paint poly poly2 cap
|
|||
|
|
paint poly cap cap
|
|||
|
|
paint poly2 cap cap
|
|||
|
|
paint cap poly cap
|
|||
|
|
paint cap poly2 cap
|
|||
|
|
/* ILLEGAL declaration by 7.3 standards */
|
|||
|
|
/* paint poly ec cc */
|
|||
|
|
paint ec poly cc
|
|||
|
|
/* These rules allow nwell to be painted over an area to
|
|||
|
|
* flip all the p-well types to n-well types. Pwell can be
|
|||
|
|
* painted to flip in the reverse. */
|
|||
|
|
paint pdc pwell ndc
|
|||
|
|
paint pfet pwell nfet
|
|||
|
|
paint epfet pwell enfet
|
|||
|
|
paint pffet pwell nffet
|
|||
|
|
paint pdiff pwell ndiff
|
|||
|
|
paint nsd pwell psd
|
|||
|
|
paint nsc pwell psc
|
|||
|
|
paint ndc nwell pdc
|
|||
|
|
paint nfet nwell pfet
|
|||
|
|
paint enfet nwell epfet
|
|||
|
|
paint nffet nwell pffet
|
|||
|
|
paint ndiff nwell pdiff
|
|||
|
|
paint psd nwell nsd
|
|||
|
|
paint psc nwell nsc
|
|||
|
|
|
|||
|
|
paint pdc hpwell hndc
|
|||
|
|
paint epfet hpwell hnfet
|
|||
|
|
paint pffet hpwell hnfet
|
|||
|
|
paint pdiff hpwell hndiff
|
|||
|
|
paint nsd hpwell hpsd
|
|||
|
|
paint nsc hpwell hpsc
|
|||
|
|
paint ndc hnwell hpdc
|
|||
|
|
paint enfet hnwell hpfet
|
|||
|
|
paint nffet hnwell hpfet
|
|||
|
|
paint ndiff hnwell hpdiff
|
|||
|
|
paint psd hnwell hnsd
|
|||
|
|
paint psc hnwell hnsc
|
|||
|
|
/* BCCD layers combination rules */
|
|||
|
|
/* paint bd ndiff 0 implant */
|
|||
|
|
/*
|
|||
|
|
erase nbd bd ndiff
|
|||
|
|
erase nbd ndiff bd
|
|||
|
|
erase nbdc/a bd ndc/a
|
|||
|
|
*/
|
|||
|
|
/* Well capacitor combination rules */
|
|||
|
|
paint nfet cwell wcap
|
|||
|
|
paint poly wcap wcap
|
|||
|
|
paint ndiff wcap wcap
|
|||
|
|
paint wcap poly wcap
|
|||
|
|
paint wcap ndiff wcap
|
|||
|
|
erase wcap poly ndiff
|
|||
|
|
erase wcap ndiff poly
|
|||
|
|
erase wcap cwell nfet
|
|||
|
|
paint cwell nfet wcap active
|
|||
|
|
erase wcap nfet cwell well
|
|||
|
|
|
|||
|
|
/* Generic contact */
|
|||
|
|
paint gc m1 gc
|
|||
|
|
|
|||
|
|
/* For pads */
|
|||
|
|
paint pad m1 pad
|
|||
|
|
paint pad m2 pad
|
|||
|
|
paint pad m3 pad
|
|||
|
|
paint pad m2c pad
|
|||
|
|
|
|||
|
|
/* These rules allow nwell to be painted over an area to
|
|||
|
|
* flip all the p-well types to n-well types. Pwell can be
|
|||
|
|
* painted to flip in the reverse. */
|
|||
|
|
paint hpdc hpwell hndc
|
|||
|
|
paint hpfet hpwell hnfet
|
|||
|
|
paint hpdiff hpwell hndiff
|
|||
|
|
paint hnsd hpwell hpsd
|
|||
|
|
paint hnsc hpwell hpsc
|
|||
|
|
paint hndc hnwell hpdc
|
|||
|
|
paint hnfet hnwell hpfet
|
|||
|
|
paint hndiff hnwell hpdiff
|
|||
|
|
paint hpsd hnwell hnsd
|
|||
|
|
paint hpsc hnwell hnsc
|
|||
|
|
|
|||
|
|
paint hpdc pwell ndc
|
|||
|
|
paint hpfet pwell enfet
|
|||
|
|
paint hpdiff pwell ndiff
|
|||
|
|
paint hnsd pwell psd
|
|||
|
|
paint hnsc pwell psc
|
|||
|
|
paint hndc nwell pdc
|
|||
|
|
paint hnfet nwell epfet
|
|||
|
|
paint hndiff nwell pdiff
|
|||
|
|
paint hpsd nwell nsd
|
|||
|
|
paint hpsc nwell nsc
|
|||
|
|
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
connect
|
|||
|
|
#ifndef WELL_ROUTE_CHECK
|
|||
|
|
/* This creates a tech file where the wells are not connected therefore
|
|||
|
|
enabling extractions to check whether the wells are used accidentaly
|
|||
|
|
to route signals or power. To check for these cases you have to compare
|
|||
|
|
the netlists generated with the normal tech file with those generated
|
|||
|
|
with the special one (eg. using gemini).
|
|||
|
|
*/
|
|||
|
|
allNwell allNwell
|
|||
|
|
allPwell allPwell
|
|||
|
|
#endif
|
|||
|
|
allHVNwell allHVNwell
|
|||
|
|
allHVPwell allHVPwell
|
|||
|
|
/* for capacitor-well */
|
|||
|
|
allNDiff cwell
|
|||
|
|
/* for all metals */
|
|||
|
|
allMetal1 allMetal1
|
|||
|
|
allMetal2 allMetal2
|
|||
|
|
allMetal3 allMetal3
|
|||
|
|
/* for all polys */
|
|||
|
|
allP1 allP1
|
|||
|
|
allPoly2 allPoly2
|
|||
|
|
/* for all diffusions/well plugs */
|
|||
|
|
/* Ndiffusion and Ohmic wells dont connect !! */
|
|||
|
|
/* you get a diode instead */
|
|||
|
|
allNDiff,ndop allPOhmic,pdop,pstop
|
|||
|
|
allPDiff,pdop,pstop allNOhmic,ndop
|
|||
|
|
allHVNDiff,ndop allHVPOhmic,pdop,pstop
|
|||
|
|
allHVPDiff,pdop,pstop allHVNOhmic,ndop
|
|||
|
|
ndiff ndc
|
|||
|
|
pdiff pdc
|
|||
|
|
hndiff hndc
|
|||
|
|
hpdiff hpdc
|
|||
|
|
/* for BCCD device */
|
|||
|
|
nbd nbdc
|
|||
|
|
/* for NPN transistor */
|
|||
|
|
pbase pbc
|
|||
|
|
collector clc,nwell
|
|||
|
|
emitter emc
|
|||
|
|
/* for new generic contact */
|
|||
|
|
gc allActive,allOhmic,allHVDiff,metal1
|
|||
|
|
gc allP1
|
|||
|
|
gc allPoly2
|
|||
|
|
/* for pad */
|
|||
|
|
pad allMetal1
|
|||
|
|
pad allMetal2
|
|||
|
|
pad allMetal3
|
|||
|
|
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
/* WARNING ::::: automatic generation of wells does not guarantee */
|
|||
|
|
/* rules on width and spacing of wells are followed !! */
|
|||
|
|
/* It is strongly recommanded that designers layout their own wells */
|
|||
|
|
|
|||
|
|
/* PWELL styles cannot generate CBA and CCD correctly */
|
|||
|
|
/* BOTH NWELL and GEN can do CCD and CBA */
|
|||
|
|
/* ONLY GEN can be used for micro-machining fabrication */
|
|||
|
|
|
|||
|
|
cifoutput
|
|||
|
|
/* default: fab on 2.0 micron (Nwell) rules each magic unit is 100 */
|
|||
|
|
/* centimicrons */
|
|||
|
|
/* SCN technology : Both CSN and CSP are generated to reduce field */
|
|||
|
|
/* poly sheet resistance */
|
|||
|
|
|
|||
|
|
#ifdef STANDARD
|
|||
|
|
#include "cif_template/objs/CIFout"
|
|||
|
|
#endif /* STANDARD */
|
|||
|
|
|
|||
|
|
#ifdef TIGHTMETAL
|
|||
|
|
#include "cif_template/objs/TMCIFout"
|
|||
|
|
#endif /* TIGHTMETAL */
|
|||
|
|
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
#include "cif_template/objs/SUBCIFout"
|
|||
|
|
#endif /* SUBMICRON */
|
|||
|
|
|
|||
|
|
#ifdef IBMTECH
|
|||
|
|
#include "cif_template/objs/IBMCIFout"
|
|||
|
|
#endif /* IBMTECH */
|
|||
|
|
|
|||
|
|
style plot /* pplot output style */
|
|||
|
|
scalefactor 100 50
|
|||
|
|
layer CM2 m2,m2c/m2,pad/m2
|
|||
|
|
labels m2
|
|||
|
|
layer CM1 pad
|
|||
|
|
grow 100
|
|||
|
|
or m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1
|
|||
|
|
labels m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1,pad/m1
|
|||
|
|
layer CP poly,pc/active,nfet,pfet
|
|||
|
|
labels poly,nfet,pfet
|
|||
|
|
layer CND ndiff,ndc,nfet,pwc,psd
|
|||
|
|
labels ndiff
|
|||
|
|
layer CPD pdiff,pdc,pfet,nwc,nsd
|
|||
|
|
labels pdiff
|
|||
|
|
layer CNP
|
|||
|
|
bloat-or nsd,nwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0
|
|||
|
|
layer CPP
|
|||
|
|
bloat-or psd,pwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0
|
|||
|
|
layer CV m2c
|
|||
|
|
squares 100 200 300
|
|||
|
|
layer CC ndc,pdc,pc,pwc,nwc
|
|||
|
|
squares 200
|
|||
|
|
layer CNW nwell
|
|||
|
|
grow 400
|
|||
|
|
shrink 400
|
|||
|
|
layer CG pad
|
|||
|
|
shrink 600
|
|||
|
|
or glass
|
|||
|
|
labels glass
|
|||
|
|
|
|||
|
|
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
/* -------------------------------------------------------------------- *
|
|||
|
|
* In the CIFinput section, the order of layer specifications is very *
|
|||
|
|
* important. Each layer overrides any of the previous layers. There *
|
|||
|
|
* are places where one layer is generated over an area that is too *
|
|||
|
|
* large, but with the knowledge that later layers will "take over" *
|
|||
|
|
* the extraneous area, leaving the first layer only where it belongs. *
|
|||
|
|
* This happens for various flavors of diffusion, for example. *
|
|||
|
|
* Note: when reading in CMOS, wells are created in the Magic files. *
|
|||
|
|
* They can be eliminated manually if desired. *
|
|||
|
|
* ---------------------------------------------------------------------*/
|
|||
|
|
cifinput
|
|||
|
|
|
|||
|
|
#ifdef STANDARD
|
|||
|
|
#include "cif_template/objs/CIFin"
|
|||
|
|
#endif /* STANDARD */
|
|||
|
|
|
|||
|
|
#ifdef TIGHTMETAL
|
|||
|
|
#include "cif_template/objs/TMCIFin"
|
|||
|
|
#endif /* TIGHTMETAL */
|
|||
|
|
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
#include "cif_template/objs/SUBCIFin"
|
|||
|
|
#endif /* SUBMICRON */
|
|||
|
|
|
|||
|
|
#ifdef IBMTECH
|
|||
|
|
#include "cif_template/objs/IBMCIFin"
|
|||
|
|
#endif /* IBMTECH */
|
|||
|
|
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
mzrouter
|
|||
|
|
style irouter
|
|||
|
|
layer m2 32 64 256 1
|
|||
|
|
layer m1 64 32 256 1
|
|||
|
|
layer poly 128 128 512 1
|
|||
|
|
contact m2contact metal1 metal2 1024
|
|||
|
|
contact pcontact metal1 poly 2056
|
|||
|
|
notactive poly pcontact
|
|||
|
|
style garouter
|
|||
|
|
layer m2 32 64 256 1
|
|||
|
|
layer m1 64 32 256 1
|
|||
|
|
contact m2contact metal1 metal2 1024
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* SCMOS rules revision 7 */
|
|||
|
|
drc
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Well */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
|
|||
|
|
/* 1.1 */
|
|||
|
|
/* Now use "edge" for width DRC... A test only for rule1 */
|
|||
|
|
/* Other rules may follow in the near future... */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
edge4way (~nwell)/w nwell 12 nwell nwell 12\
|
|||
|
|
"N-Well width must be at least 12 (MOSIS rule #1.1)"
|
|||
|
|
edge4way (~pwell)/w pwell 12 pwell pwell 12\
|
|||
|
|
"P-Well width must be at least 12 (MOSIS rule #1.1)"
|
|||
|
|
#else
|
|||
|
|
edge4way (~nwell)/w nwell 10 nwell nwell 10\
|
|||
|
|
"N-Well width must be at least 10 (MOSIS rule #1.1)"
|
|||
|
|
edge4way (~pwell)/w pwell 10 pwell pwell 10\
|
|||
|
|
"P-Well width must be at least 10 (MOSIS rule #1.1)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* original "width" rule which use 'width'command:
|
|||
|
|
width allWell 10 \
|
|||
|
|
"Well width must be at least 10 (MOSIS rule #1.1)"
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* 1.2 */
|
|||
|
|
/* Now use "edge4way" for spacing DRC... A test only for rule1 */
|
|||
|
|
/* Other rules may follow in the near future... */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
edge4way nwell ~(nwell)/w 18 (~nwell)/w (~nwell)/w 18\
|
|||
|
|
"N-Well spacing must be at least 18 (MOSIS rule #1.2)"
|
|||
|
|
edge4way pwell (~pwell)/w 18 (~pwell)/w (~pwell)/w 18\
|
|||
|
|
"P-Well spacing must be at least 18 (MOSIS rule #1.2)"
|
|||
|
|
#else
|
|||
|
|
edge4way nwell (~nwell)/w 9 (~nwell)/w (~nwell)/w 9\
|
|||
|
|
"N-Well spacing must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
edge4way pwell (~pwell)/w 9 (~pwell)/w (~pwell)/w 9\
|
|||
|
|
"P-Well spacing must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* original spacing rule which use 'spacing' command:
|
|||
|
|
spacing allWell allWell 9 touching_ok \
|
|||
|
|
"Well spacing must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* NOTE: rule 1.2 is equivalent to the following three rules where
|
|||
|
|
the third is a new one. This rule is added to force designers
|
|||
|
|
to be cautious about the wells...
|
|||
|
|
|
|||
|
|
spacing nwell nwell 9 touching_ok \
|
|||
|
|
"N-well spacing must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
spacing pwell pwell 9 touching_ok \
|
|||
|
|
"P-well spacing must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
spacing nwell pwell 9 touching_ok \
|
|||
|
|
"Well spacing must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* 1.3 is not checked */
|
|||
|
|
/* NOTE: for digital ckts where wells are not explicitly put, *
|
|||
|
|
* auto-generation may not ensure the minimul spacing and width *
|
|||
|
|
* rule: this happens usually when two geometries are in diagonal *
|
|||
|
|
* positions. *
|
|||
|
|
* NOTE: when both pwell and nwell are submitted they cannot *
|
|||
|
|
* overlap this is assured with the compose section - painting one *
|
|||
|
|
* well over another will erase the original well. */
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Active */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
|
|||
|
|
/* 2.1 */
|
|||
|
|
/* Test active width separately... */
|
|||
|
|
width allNActive 3 \
|
|||
|
|
"N-type Diffusion width must be at least 3 (MOSIS rule #2.1a)"
|
|||
|
|
width allPActive 3 \
|
|||
|
|
"P-type Diffusion width must be at least 3 (MOSIS rule #2.1b)"
|
|||
|
|
width allOhmic 3 \
|
|||
|
|
"Ohmic diffusion width must be at least 3 (MOSIS rule #2.1c)"
|
|||
|
|
|
|||
|
|
/* 2.2 */
|
|||
|
|
spacing allNActive allNActive 3 touching_ok \
|
|||
|
|
"Diffusion spacing must be at least 3 (MOSIS rule #2.2)"
|
|||
|
|
spacing allPActive allPActive 3 touching_ok \
|
|||
|
|
"Diffusion spacing must be at least 3 (MOSIS rule #2.2)"
|
|||
|
|
spacing allNOhmic allNOhmic 3 touching_ok \
|
|||
|
|
"Diffusion spacing must be at least 3 (MOSIS rule #2.2)"
|
|||
|
|
spacing allPOhmic allPOhmic 3 touching_ok \
|
|||
|
|
"Diffusion spacing must be at least 3 (MOSIS rule #2.2)"
|
|||
|
|
|
|||
|
|
/* 2.3 without explicit well definition: 6+6 and 5+5 respectively */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
spacing allNDiff allPDiff 12 touching_illegal \
|
|||
|
|
"P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #2.3b)"
|
|||
|
|
#else
|
|||
|
|
spacing allNDiff allPDiff 10 touching_illegal \
|
|||
|
|
"P-type diffusion must be 10 away from N-type diffusion (MOSIS rule #2.3a)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* 2.3 + 2.4 without explicit well definition: 6+3 and 5+3 respectively */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
spacing allNDiff allNOhmic 9 touching_illegal \
|
|||
|
|
"N-type diffusion must be 9 away from N-substrate contact (MOSIS rule #2.3b,4b)"
|
|||
|
|
spacing allPDiff allPOhmic 9 touching_illegal \
|
|||
|
|
"P-type diffusion must be 9 away from P-substrate contact (MOSIS rule #2.3b,4b)"
|
|||
|
|
#else
|
|||
|
|
spacing allNDiff allNOhmic 8 touching_illegal \
|
|||
|
|
"N-type diffusion must be 8 away from N-substrate contact (MOSIS rule #2.3a,4a)"
|
|||
|
|
spacing allPDiff allPOhmic 8 touching_illegal \
|
|||
|
|
"P-type diffusion must be 8 away from P-substrate contact (MOSIS rule #2.3a,4a)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* 2.4 3 + 3 */
|
|||
|
|
spacing allNOhmic allPOhmic 6 touching_illegal \
|
|||
|
|
"Opposite well contacts must be separated by 6 (MOSIS rule #2.4)"
|
|||
|
|
|
|||
|
|
/* 2.3 with explicit well: 6 and 5 respectively */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
spacing allNActive nwell 6 touching_illegal \
|
|||
|
|
"N-diffusion and N-well must be separated by 6 (MOSIS rule #2.3b)"
|
|||
|
|
spacing allPActive pwell 6 touching_illegal \
|
|||
|
|
"P-diffusion and P-well must be separated by 6 (MOSIS rule #2.3b)"
|
|||
|
|
#else
|
|||
|
|
spacing allNActive nwell 5 touching_illegal \
|
|||
|
|
"N-diffusion and N-well must be separated by 5 (MOSIS rule #2.3a)"
|
|||
|
|
spacing allPActive pwell 5 touching_illegal \
|
|||
|
|
"P-diffusion and P-well must be separated by 5 (MOSIS rule #2.3a)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* 2.4 with explicit well */
|
|||
|
|
spacing allNOhmic pwell 3 touching_illegal \
|
|||
|
|
"N-substrate diffusion and P-well must be separated by 3 (MOSIS rule #2.4)"
|
|||
|
|
spacing allPOhmic nwell 3 touching_illegal \
|
|||
|
|
"P-substrate diffusion and N-well must be separated by 3 (MOSIS rule #2.4)"
|
|||
|
|
|
|||
|
|
/* MOSIS extension rule for diffusion and substrate contact of */
|
|||
|
|
/* opposite type. We could do without this rule, but it is now */
|
|||
|
|
/* added for safety reason. */
|
|||
|
|
spacing allNActive allPOhmic 4 touching_ok \
|
|||
|
|
"Opposite diffusion spacing must be at least 4 (MOSIS extension rule)"
|
|||
|
|
spacing allPActive allNOhmic 4 touching_ok \
|
|||
|
|
"Opposite diffusion spacing must be at least 4 (MOSIS extension rule)"
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Poly */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
|
|||
|
|
/* 3.1 */
|
|||
|
|
width allPoly 2 \
|
|||
|
|
"Polysilicon width must be at least 2 (MOSIS rule #3.1)"
|
|||
|
|
|
|||
|
|
/* 3.2 */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
spacing allPoly allPoly 3 touching_ok \
|
|||
|
|
"Polysilicon spacing must be at least 3 (MOSIS rule #3.2b)"
|
|||
|
|
#else
|
|||
|
|
spacing allPoly allPoly 2 touching_ok \
|
|||
|
|
"Polysilicon spacing must be at least 2 (MOSIS rule #3.2a)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* 3.3 */
|
|||
|
|
edge4way nfet,pfet poly,pc/act 2 poly,pc/act 0 0 \
|
|||
|
|
"Poly must overhang transistor by at least 2 (MOSIS rule #3.3)"
|
|||
|
|
|
|||
|
|
/* 3.4 */
|
|||
|
|
edge4way nfet,enfet ndiff,ndc/a 3 allNActive ndiff,ndc/a 3 \
|
|||
|
|
"Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)"
|
|||
|
|
edge4way pfet,epfet pdiff,pdc/a 3 allPActive ndiff,ndc/a 3 \
|
|||
|
|
"Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)"
|
|||
|
|
|
|||
|
|
/* 3.3 + 3.4 */
|
|||
|
|
edge4way nfet,pfet space 1 poly 0 0 \
|
|||
|
|
"Transistor overhang is missing (MOSIS rule #3.3,4)"
|
|||
|
|
edge4way enfet,epfet space 1 poly2 0 0 \
|
|||
|
|
"Transistor overhang is missing (MOSIS rule #3.3,4)"
|
|||
|
|
edge4way nffet,pffet space 1 poly 0 0 \
|
|||
|
|
"Transistor overhang is missing (MOSIS rule #3.3,4)"
|
|||
|
|
edge4way nffet,pffet space 1 poly2 0 0 \
|
|||
|
|
"Transistor overhang is missing (MOSIS rule #3.3,4)"
|
|||
|
|
|
|||
|
|
/* 3.5 */
|
|||
|
|
edge4way allDiff,allOhmic poly,pc 1 space/a 0 1 \
|
|||
|
|
"Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)"
|
|||
|
|
edge4way poly,pc allDiff,allOhmic 1 space/a 0 1 \
|
|||
|
|
"Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)"
|
|||
|
|
edge poly,pc space/a 1 space/a space/a 1 \
|
|||
|
|
"Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)"
|
|||
|
|
edge allOhmic,allDiff space/a 1 space/a space/a 1 \
|
|||
|
|
"Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)"
|
|||
|
|
/*
|
|||
|
|
These following checks will miss the corner, so we add something above
|
|||
|
|
|
|||
|
|
edge4way allDiff,allOhmic poly,pc 1 space space 1 \
|
|||
|
|
"Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5.a)"
|
|||
|
|
spacing allDiff,allOhmic poly,pc 1 touching_illegal \
|
|||
|
|
"Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5.b)"
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Extra transistor rules */
|
|||
|
|
/* These rules is really NOT necessary because others have already
|
|||
|
|
taken care of it. It is here for future reference...
|
|||
|
|
|
|||
|
|
edge4way poly,pc/act pfet 3 pfet 0 0 \
|
|||
|
|
"Transistors must be at least 3 units wide (MOSIS rule #2)"
|
|||
|
|
edge4way poly,pc/act nfet 3 nfet 0 0 \
|
|||
|
|
"Transistors must be at least 3 units wide (MOSIS rule #2)"
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Select */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 4.1 */
|
|||
|
|
spacing PFet allNOhmic 3 touching_illegal \
|
|||
|
|
"Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.a)"
|
|||
|
|
spacing NFet allPOhmic 3 touching_illegal \
|
|||
|
|
"Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.b)"
|
|||
|
|
|
|||
|
|
edge4way allPOhmic space/act 3 ~(NFet)/act allPOhmic,allNDiff 3 \
|
|||
|
|
"Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.c)"
|
|||
|
|
|
|||
|
|
edge4way allNOhmic space/act 3 ~(PFet)/act allNOhmic,allPDiff 3 \
|
|||
|
|
"Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.d)"
|
|||
|
|
|
|||
|
|
edge4way allPOhmic ~(ndiff,ndc,psc,psd)/act 4 ~(nfet,enfet)/act ~(ndiff,ndc,psc,psd)/act 4 \
|
|||
|
|
"Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.e)"
|
|||
|
|
|
|||
|
|
edge4way allNOhmic ~(pdiff,pdc,nsc,nsd)/act 4 ~(pfet,epfet)/act ~(pdiff,pdc,nsc,nsd)/act 4 \
|
|||
|
|
"Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.f)"
|
|||
|
|
|
|||
|
|
/* 4.2 */
|
|||
|
|
/* This one is very difficult.... Most likely done by CIF output */
|
|||
|
|
edge4way ~(allPActive)/act pdiff,pdc,pfet 4 ~(allNOhmic)/act allPActive 2 \
|
|||
|
|
"Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.a)"
|
|||
|
|
edge4way ~(allNActive)/act ndiff,ndc,nfet 4 ~(allPOhmic)/act allNActive 2 \
|
|||
|
|
"Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.b)"
|
|||
|
|
|
|||
|
|
/* 4.3 -- guaranteed automatically by CIF generator. */
|
|||
|
|
/* 4.4 -- guaranteed automatically by CIF generator except diag. where
|
|||
|
|
this rule is not crucial */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Contact to Poly */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
|
|||
|
|
/* 5B.1 + 5B.2 + 5B.3 */
|
|||
|
|
width pc 4 \
|
|||
|
|
"Poly contact width must be at least 4 (MOSIS rule #5B.1,2,3)"
|
|||
|
|
|
|||
|
|
/* 5B.4 is guaranteed by 5B.1,2,3 with rule 7.2 (metal1 spacing) */
|
|||
|
|
|
|||
|
|
/* 5B.5 --
|
|||
|
|
* Watch out here: a spacing "touching_ok" rule CANNOT be used here:
|
|||
|
|
* it will miss certain checks.
|
|||
|
|
*/
|
|||
|
|
edge4way allPoly ~(allPoly)/act 3 ~pc/act ~(allPoly)/act 3 \
|
|||
|
|
"Poly contact must be at least 3 from other poly (MOSIS rule #5B.4,5)"
|
|||
|
|
|
|||
|
|
/* 5B.6 --
|
|||
|
|
* This is mostly handled by 3.5 already, but need rule here to handle
|
|||
|
|
* case of pc abutting transistor.
|
|||
|
|
*/
|
|||
|
|
spacing pc allActive 1 touching_illegal \
|
|||
|
|
"Poly contact must be 1 unit from diffusion (MOSIS rule #5B.6)"
|
|||
|
|
|
|||
|
|
/* 5B.7 -- not implemented */
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Contact to Active */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
|
|||
|
|
/* 6B.1 + 6B.2 + 6B.3 */
|
|||
|
|
width ndc,pdc 4 \
|
|||
|
|
"Diffusion contact width must be at least 4 (MOSIS rule #6B.1,2,3)"
|
|||
|
|
width nsc,psc 4 \
|
|||
|
|
"Substrate contact width must be at least 4 (MOSIS rule #6B.1,2,3)"
|
|||
|
|
|
|||
|
|
/* 6B.2 this is here to explicit check the contact spacing rule 3. */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
spacing nsc pdc 1 touching_illegal \
|
|||
|
|
"Substrate contact must be 1 unit from diffusion contact (MOSIS rule #6B.2b)"
|
|||
|
|
spacing psc ndc 1 touching_illegal \
|
|||
|
|
"Substrate contact must be 1 unit from diffusion contact (MOSIS rule #6B.2b)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/*
|
|||
|
|
edge4way psc (~psc)/a 1 psd psd 1 \
|
|||
|
|
"Substrate contact must overlapped by diffusion by at least 1 (MOSIS 26G rule)"
|
|||
|
|
edge4way nsc (~nsc)/a 1 nsd nsd 1 \
|
|||
|
|
"Substrate contact must overlapped by diffusion by at least 1 (MOSIS 26G rule)"
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* 6B.4 & 6B.5 --
|
|||
|
|
* Watch out here: a spacing "touching_ok" rule CANNOT be used here:
|
|||
|
|
* it will miss certain checks.
|
|||
|
|
*/
|
|||
|
|
edge4way allActive ~(allActive)/act 4 ~(ndc,pdc,nsc,psc)/act \
|
|||
|
|
~(allActive)/act 4 \
|
|||
|
|
"Diffusion contacts must be 4 from other diffusions (MOSIS rule #6B.4,5)"
|
|||
|
|
|
|||
|
|
/* 6B.6 */
|
|||
|
|
spacing DiffCut allFet 1 touching_illegal \
|
|||
|
|
"Diffusion contacts cannot touch transistors (MOSIS rule #6B.6)"
|
|||
|
|
|
|||
|
|
/* 6B.7 */
|
|||
|
|
spacing DiffCut poly 1 touching_illegal \
|
|||
|
|
"Diffusion contact to field poly must be at least 1 (MOSIS rule #6B.7)"
|
|||
|
|
|
|||
|
|
/* 6.8 -- not implemented */
|
|||
|
|
|
|||
|
|
/* 6B.9 */
|
|||
|
|
spacing DiffCut pc/act 2 touching_illegal \
|
|||
|
|
"Poly contacts must be 2 away from diffusion contacts (MOSIS rule #6B.9)"
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Contacts must all be rectangular (no adjacent contacts */
|
|||
|
|
/* of same type) because of the way their contact is generated by */
|
|||
|
|
/* CIFoutput section rules. This is handled using the corner checks */
|
|||
|
|
/* in the rules below. Overlaps between contacts must be exact */
|
|||
|
|
/* overlaps. The only exception is overpad, which doesn't matter. */
|
|||
|
|
|
|||
|
|
edge4way m3c/m3 ~m3c/m3 1 ~m3c/m3 (~m3c,m3c)/m3 1 \
|
|||
|
|
"Metal3 contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way m2c/m2 ~m2c/m2 1 ~m2c/m2 (~m2c,m2c)/m2 1 \
|
|||
|
|
"Metal2 contacts must be rectangular (Magic rules)"
|
|||
|
|
|
|||
|
|
edge4way ndc/m1 ~ndc/m1 1 ~ndc/m1 (~ndc,ndc)/m1 1 \
|
|||
|
|
"N-diffusion contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way pdc/m1 ~pdc/m1 1 ~pdc/m1 (~pdc,pdc)/m1 1 \
|
|||
|
|
"P-diffusion contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way psc/m1 ~psc/m1 1 ~psc/m1 (~psc,psc)/m1 1 \
|
|||
|
|
"P-substrate contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way nsc/m1 ~nsc/m1 1 ~nsc/m1 (~nsc,nsc)/m1 1 \
|
|||
|
|
"N-substrate contacts must be rectangular (Magic rules)"
|
|||
|
|
|
|||
|
|
edge4way pc/m1 ~pc/m1 1 ~pc/m1 (~pc,pc)/m1 1 \
|
|||
|
|
"Polysilicon contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way ec/m1 ~ec/m1 1 ~ec/m1 (~ec,ec)/m1 1 \
|
|||
|
|
"Electrode contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way cc/m1 ~cc/m1 1 ~cc/m1 (~cc,cc)/m1 1 \
|
|||
|
|
"Capacitor contacts must be rectangular (Magic rules)"
|
|||
|
|
|
|||
|
|
edge4way emc/m1 ~emc/m1 1 ~emc/m1 (~emc,emc)/m1 1 \
|
|||
|
|
"Emitter contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way clc/m1 ~clc/m1 1 ~clc/m1 (~clc,clc)/m1 1 \
|
|||
|
|
"Collector contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way pbc/m1 ~pbc/m1 1 ~pbc/m1 (~pbc,pbc)/m1 1 \
|
|||
|
|
"P-base Contacts must be rectangular (Magic rules)"
|
|||
|
|
edge4way nbdc/m1 ~nbdc/m1 1 ~nbdc/m1 (~nbdc,nbdc)/m1 1 \
|
|||
|
|
"CCD-diffusion Contacts must be rectangular (Magic rules)"
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Metal 1 */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 7.1 + 7.2 */
|
|||
|
|
width allMetal1,pad/m1 3 \
|
|||
|
|
"First-level metal width must be at least 3 (MOSIS rule #7.1)"
|
|||
|
|
#ifdef TIGHTMETAL
|
|||
|
|
spacing allMetal1,pad/m1 allMetal1,pad/m1 2 touching_ok \
|
|||
|
|
"First-level metal spacing must be at least 2 (MOSIS rule #7.2)"
|
|||
|
|
#else
|
|||
|
|
spacing allMetal1,pad/m1 allMetal1,pad/m1 3 touching_ok \
|
|||
|
|
"First-level metal spacing must be at least 3 (MOSIS rule #7.2)"
|
|||
|
|
#endif /* TIGHTMETAL */
|
|||
|
|
|
|||
|
|
/* 7.3 + 7.4 */
|
|||
|
|
/* guaranteed with 4x4 poly and diffusion contacts */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Via */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
|
|||
|
|
/* 8.1 + 8.2 + 8.3 */
|
|||
|
|
width m2c 4 \
|
|||
|
|
"Contact width must be at least 4 (MOSIS rule #8.1,2,3)"
|
|||
|
|
|
|||
|
|
/* 8.4 + 8.5 */
|
|||
|
|
/* Vias have to be on flat surface */
|
|||
|
|
/* Don't allow poly or diffusion edges underneath metal2 contacts: */
|
|||
|
|
/* this rule is only valid for standard processes, not for those */
|
|||
|
|
/* processes use planarized interconnection technology. */
|
|||
|
|
#ifdef STANDARD
|
|||
|
|
edge4way allPoly ~(allPoly)/a 1 ~m2c/m2 ~(allPoly)/a 1 \
|
|||
|
|
"Via must be on a flat surface (MOSIS rule #8.4,5)" metal2
|
|||
|
|
edge4way allPoly2 ~(allPoly2)/a 1 ~m2c/m2 ~(allPoly2)/a 1 \
|
|||
|
|
"Via must be on a flat surface (MOSIS rule #8.4,5)" metal2
|
|||
|
|
edge4way allActive ~(allActive)/a 1 ~m2c/m2 ~(allActive)/a 1 \
|
|||
|
|
"Via must be on a flat surface (MOSIS rule #8.4,5)" metal2
|
|||
|
|
|
|||
|
|
edge4way ~(allPoly)/a allPoly 1 ~m2c/m2 allPoly 1 \
|
|||
|
|
"Via must be on a flat surface (MOSIS rule #8.4,5)" metal2
|
|||
|
|
edge4way ~(allPoly2)/a allPoly2 1 ~m2c/m2 allPoly2 1 \
|
|||
|
|
"Via must be on a flat surface (MOSIS rule #8.4,5)" metal2
|
|||
|
|
edge4way ~(allActive)/a allActive 1 ~m2c/m2 allActive 1 \
|
|||
|
|
"Via must be on a flat surface (MOSIS rule #8.4,5)" metal2
|
|||
|
|
#endif /* STANDARD */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Metal 2 */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 9.1 */
|
|||
|
|
width allMetal2 3 \
|
|||
|
|
"Second-level metal width must be at least 3 (MOSIS rule #9.1)"
|
|||
|
|
|
|||
|
|
/* 9.2 */
|
|||
|
|
#ifdef TIGHTMETAL
|
|||
|
|
spacing allMetal2 allMetal2 3 touching_ok \
|
|||
|
|
"Second-level metal spacing must be at least 3 (MOSIS rule #9.2b)"
|
|||
|
|
#else
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
spacing allMetal2 allMetal2 3 touching_ok \
|
|||
|
|
"Second-level metal spacing must be at least 3 (MOSIS rule #9.2b)"
|
|||
|
|
#else
|
|||
|
|
spacing allMetal2 allMetal2 4 touching_ok \
|
|||
|
|
"Second-level metal spacing must be at least 4 (MOSIS rule #9.2a)"
|
|||
|
|
#endif /* SUBMICRON */
|
|||
|
|
#endif /* TIGHTMETAL */
|
|||
|
|
|
|||
|
|
/* 9.3 */
|
|||
|
|
/* achieved with via size of 4x4 */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Overglass */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Rules for overglass (10.1-5) are not check because they are */
|
|||
|
|
/* either */
|
|||
|
|
/* 1. absolute micron rules, and */
|
|||
|
|
/* 2. vender/process dependent. */
|
|||
|
|
/* except the metal overlap of overglass rule (10.3) can be handled */
|
|||
|
|
/* case by case in CIFoutput section. */
|
|||
|
|
/* NOTE: glass layer is NOT usually used. Use "pad" layer for pad */
|
|||
|
|
/* and the corresponding overglass will be generated automatically. */
|
|||
|
|
|
|||
|
|
/* MOSIS rules to make sure there are m2 under glass - for those */
|
|||
|
|
/* users who like to use explicit "glass" layer... */
|
|||
|
|
/* */
|
|||
|
|
/* edge4way space glass 1 allMetal2 0 0 \ */
|
|||
|
|
/* "There must be metal 2 under the glass opening" metal2 */
|
|||
|
|
/* */
|
|||
|
|
/* I am removing this rule simply we have metal3 now and there's no */
|
|||
|
|
/* way to tell which process the pad is intended for. Basically, I */
|
|||
|
|
/* am enforcing the use of "pad" layer... */
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Open and Pstop */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* The open layer is actually a combination of overglass and */
|
|||
|
|
/* contacts to expose the intrinsic silicon surface for future */
|
|||
|
|
/* etchimg process for micromachining device fabrication. */
|
|||
|
|
/* Since lots of applications are possible, there is no rules */
|
|||
|
|
/* enforced by Magic. Designers aimed at micromachining devices */
|
|||
|
|
/* must do DRC themself :-) */
|
|||
|
|
/* See the following reference for detail: */
|
|||
|
|
/* "High-Level CAD Melds Micromachined Devices with Foundaries", */
|
|||
|
|
/* Janet C. Marshall, M. Parameswaran, Mona E. Zaghloul, and */
|
|||
|
|
/* Michael Gaitan, IEEE Circuit and Devices, Vol. 8, No. 6, */
|
|||
|
|
/* pp. 10-17, 1992 */
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Poly2 as Capacitor */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 11.1 */
|
|||
|
|
/* The exact rule asks for 3 lambda minimum width for 'capacitor'. */
|
|||
|
|
/* But there are overlaps of poly/eletrode structures such that 2 */
|
|||
|
|
/* is fine, such as the overlaps in floating gates. So we are risk- */
|
|||
|
|
/* ing a little here... */
|
|||
|
|
width cap,capc/a 2 \
|
|||
|
|
"Electrode capacitor width must be at least 3 (MOSIS rule #11.1)"
|
|||
|
|
|
|||
|
|
/* 11.2 + 12.2 */
|
|||
|
|
spacing allPoly2 allPoly2 3 touching_ok \
|
|||
|
|
"Second-level poly spacing must be at least 3 (MOSIS rule #11.2,12.2)"
|
|||
|
|
|
|||
|
|
/* 11.3 */
|
|||
|
|
edge4way cap,cc space 1 0 0 0 \
|
|||
|
|
"Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)"
|
|||
|
|
edge4way cap,cc poly 2 poly poly 2 \
|
|||
|
|
"Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)"
|
|||
|
|
edge4way cap,cc poly2 2 poly2 poly2 2 \
|
|||
|
|
"Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)"
|
|||
|
|
|
|||
|
|
/* 11.4 */
|
|||
|
|
edge4way nw,pw,cw ~(nw,pw,cw)/w 2 ~(cap,cc)/a ~(nw,pw,cw)/w 2 \
|
|||
|
|
"Cap must be on a flat surface (MOSIS rule #11.4)" active
|
|||
|
|
edge4way ~(nw,pw,cw)/w nw,pw,cw 2 ~(cap,cc)/a nw,pw,cw 2 \
|
|||
|
|
"Cap must be on a flat surface (MOSIS rule #11.4)" active
|
|||
|
|
edge4way cap ~(cap)/a 2 allFet,poly,poly2,space/a,cc/a \
|
|||
|
|
allDiff,poly 2 "Cap must be on a flat surface (MOSIS rule #11.4)" active
|
|||
|
|
|
|||
|
|
/* 11.5 */
|
|||
|
|
/* Done by 11.3 and 11.4 */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Poly2 as Transistor */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 12.1 */
|
|||
|
|
width allPoly2 2 \
|
|||
|
|
"Electrode width must be at least 2 (MOSIS rule #12.1)"
|
|||
|
|
|
|||
|
|
/* 12.2 */
|
|||
|
|
/* Done by 11.2 */
|
|||
|
|
|
|||
|
|
/* 12.3 */
|
|||
|
|
edge4way enfet,epfet poly2,ec/a 2 poly2,ec/a 0 0 \
|
|||
|
|
"Poly2 must overhang transistor by at least 2 (MOSIS rule #12.3)"
|
|||
|
|
edge4way nffet,pffet cap 2 cap 0 0 \
|
|||
|
|
"Cap must overhang transistor by at least 2 (MOSIS rule #12.3)"
|
|||
|
|
edge4way nffet ~(cap,nffet,enfet,nfet)/a 2 cap 0 0 \
|
|||
|
|
"Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)"
|
|||
|
|
edge4way pffet ~(cap,pffet,epfet,pfet)/a 2 cap 0 0 \
|
|||
|
|
"Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)"
|
|||
|
|
|
|||
|
|
/* 12.4 */
|
|||
|
|
edge4way allDiff,allOhmic el 1 space/a 0 1 \
|
|||
|
|
"Poly2 and diffusion must be separated by at least 1 (MOSIS rule #12.4)"
|
|||
|
|
|
|||
|
|
/* 12.5 */
|
|||
|
|
|
|||
|
|
/* 12.6 */
|
|||
|
|
spacing allPoly2 pc,ndc,pdc 2 touching_illegal \
|
|||
|
|
"Poly2 spacing to poly or diffusion contact must be at least 3 (MOSIS rule #12.6)"
|
|||
|
|
/*
|
|||
|
|
edge4way poly2,ec/a epfet 3 epfet 0 0 \
|
|||
|
|
"Transistors must be at least 3 units wide (MOSIS rule #2)"
|
|||
|
|
edge4way poly2,ec/a enfet 3 enfet 0 0 \
|
|||
|
|
"Transistors must be at least 3 units wide (MOSIS rule #2)"
|
|||
|
|
edge4way cap,capc/a pffet 3 pffet 0 0 \
|
|||
|
|
"Transistors must be at least 3 units wide (MOSIS rule #2)"
|
|||
|
|
edge4way cap,capc/a nffet 3 nffet 0 0 \
|
|||
|
|
"Transistors must be at least 3 units wide (MOSIS rule #2)"
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Poly2 Contact */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 13.1 + 13.2 */
|
|||
|
|
width ec,capc 4 \
|
|||
|
|
"Electrode contact width must be at least 4 (MOSIS rule #13.1)"
|
|||
|
|
|
|||
|
|
/* 13.3 */
|
|||
|
|
/* Done by 11.3 */
|
|||
|
|
|
|||
|
|
/* 13.4 */
|
|||
|
|
edge4way ec/a space 1 poly2 poly2 1 \
|
|||
|
|
"Electrode contact must be overlaped by poly2 (MOSIS rule #13.4)"
|
|||
|
|
edge4way ec/a poly2 1 poly2 poly2 1 \
|
|||
|
|
"Electrode contact must be overlaped by poly2 by 1 (MOSIS rule #13.4)"
|
|||
|
|
|
|||
|
|
/* 13.5 */
|
|||
|
|
edge4way allDiff,allOhmic ec 2 space/a 0 2 \
|
|||
|
|
"Poly2 and diffusion contact must be separated by at least 2 (MOSIS rule #13.5)"
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Via 2 */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 14.1 + 14.2 + 14.3 */
|
|||
|
|
/* By CIF output generation */
|
|||
|
|
width m3c 4 \
|
|||
|
|
"Third-level metal contact width must be at least 4 (MOSIS rule #14.1,2,3)"
|
|||
|
|
|
|||
|
|
/* 14.4 */
|
|||
|
|
/* guaranteed by 4x4 m2c and 4x4 m3c */
|
|||
|
|
/* Via2, i.e "m3c" can overlap anything except m2c layer */
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Metal 3 */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 15.1 */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
width allMetal3 5 \
|
|||
|
|
"Third-level metal width must be at least 5 (MOSIS rule #15.1b)"
|
|||
|
|
#else
|
|||
|
|
width allMetal3 6 \
|
|||
|
|
"Third-level metal width must be at least 6 (MOSIS rule #15.1a)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* 15.2 */
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
spacing allMetal3 allMetal3 3 touching_ok \
|
|||
|
|
"Third-level metal spacing must be at least 3 from other third-level metal (MOSIS rule #15.2b)"
|
|||
|
|
#else
|
|||
|
|
spacing allMetal3 allMetal3 4 touching_ok \
|
|||
|
|
"Third-level metal spacing must be at least 4 from other third-level metal (MOSIS rule #15.2a)"
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* 15.3 */
|
|||
|
|
edge4way m3c/m3 ~m3c/m3 1 m3 m3 1 \
|
|||
|
|
"Mimimum metal3 overlap of via must be at least 1 (MOSIS rule #15.3)"
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* NPN Bipolar */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 16.1 */
|
|||
|
|
/* As always, composite contacts are 4x4, where the actual */
|
|||
|
|
/* transistor contacts are 2x2 by CIF output generator */
|
|||
|
|
width clc,pbc,emc 4 \
|
|||
|
|
"Transistor contact width must be at least 4 (MOSIS rule #16.1)"
|
|||
|
|
|
|||
|
|
/* 16.2 */
|
|||
|
|
/* Done by 16.1 4x4 emc and CIF output generation */
|
|||
|
|
|
|||
|
|
/* 16.3 */
|
|||
|
|
/* This rule is guaranteed by the way the CIF output generates */
|
|||
|
|
/* N-Select for emitter (expand by 2 lambda), so we have Pbase */
|
|||
|
|
/* overlap of emitter(or emc) by 2+2 =4 */
|
|||
|
|
edge4way emc/a,emit pbase 4 pbase pbase 4 \
|
|||
|
|
"Pbase overlap of emitter must be at least 4 (MOSIS rule #16.3)"
|
|||
|
|
|
|||
|
|
/* 16.4 */
|
|||
|
|
/* NOTE; NO need to make this an edge rule... */
|
|||
|
|
spacing pbc emc/a,emit 7 touching_illegal \
|
|||
|
|
"Base must be 7 (4+2+1) away from emitter (MOSIS rule #16.3,4,11)"
|
|||
|
|
|
|||
|
|
/* 16.5 */
|
|||
|
|
/* This rule is guaranteed by requiring that base contact has */
|
|||
|
|
/* at least 3 (1+2) lambda base enclosure... */
|
|||
|
|
/* edge4way pbc/a pb,space 3 pb pb,space 3 */
|
|||
|
|
edge4way pbc (~pbc)/a 3 pb,pbc/a pb,pbc/a 3 \
|
|||
|
|
"Pbase overlap of base contact must be at least 3 (MOSIS rule #16.5)"
|
|||
|
|
|
|||
|
|
/* 16.6 */
|
|||
|
|
/* This rule is guaranteed by the CIF output generation of P-select */
|
|||
|
|
|
|||
|
|
/* 16.6 */
|
|||
|
|
/* This rule is enforced by checking whether collector is out of */
|
|||
|
|
/* Nwell and the fact that collector width is required to be at */
|
|||
|
|
/* least 6 */
|
|||
|
|
width col,clc/a 6 \
|
|||
|
|
"Collector width must be at least 6 (MOSIS rule #16.6)"
|
|||
|
|
|
|||
|
|
/* 16.7 */
|
|||
|
|
/* Explicit Nwell required for Bipolar transistors... */
|
|||
|
|
edge4way pbase space/a 6 nwell space/a 6 \
|
|||
|
|
"Nwell overlap of Pbase must be at least 6 (MOSIS rule #16.7)" well
|
|||
|
|
|
|||
|
|
/* 16.8 */
|
|||
|
|
edge4way pbase (~pbase)/a 4 ~(col,clc)/a ~(col,clc)/a 4 \
|
|||
|
|
"Pbase must be at least 4 away from collector (MOSIS rule #16.8)"
|
|||
|
|
|
|||
|
|
/* 16.9 */
|
|||
|
|
edge4way clc (~clc)/a 1 col col 1 \
|
|||
|
|
"Collector overlap of contact must be at least 1 (MOSIS rule #16.9)"
|
|||
|
|
|
|||
|
|
/* 16.10 */
|
|||
|
|
/* This rule is guaranteed by making sure that collector is within */
|
|||
|
|
/* PBase and the corresponding CIF output generation */
|
|||
|
|
|
|||
|
|
/* 16.11 */
|
|||
|
|
edge4way nw ~(nw)/w 3 ~(col,clc)/a ~(nw)/w 3 \
|
|||
|
|
"N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active
|
|||
|
|
edge4way ~(nw)/w nw 3 ~(col,clc)/a nw 3 \
|
|||
|
|
"N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active
|
|||
|
|
|
|||
|
|
/* This is a special rule to guarantee the emitter width */
|
|||
|
|
width em,emc/a 4 \
|
|||
|
|
"Emitter width must be at least 4 (Magic Bipolar Transistor rule)"
|
|||
|
|
|
|||
|
|
/* This is a special rule for multi-emitters transistor according */
|
|||
|
|
/* to rule 16.2 and 2.2 */
|
|||
|
|
spacing em,emc/a em,emc/a 7 touching_ok \
|
|||
|
|
"Unrelated emitter must be at least 7 apart (Magic Bipolar transistor rule)"
|
|||
|
|
|
|||
|
|
/* The following rules are added for pbase resistor implementation. */
|
|||
|
|
/* They are not in the official SCMOS design rules since I have no */
|
|||
|
|
/* foundry rules available at this moment and the numbers here is */
|
|||
|
|
/* considered to be conservative... */
|
|||
|
|
width pbase,pbc/a 4 \
|
|||
|
|
"Pbase width must be at least 4 (MOSIS extension rule)"
|
|||
|
|
|
|||
|
|
spacing pbase,pbc/a pbase,pbc/a 4 touching_ok \
|
|||
|
|
"Pbase spacing must be at least 4 (MOSIS extension rule)"
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Capacitor Well */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* These are DRC rules for Capacitor Well (CWell) according to HP's */
|
|||
|
|
/* 1.2um linear capacitor process pi@isi.edu 9/18/92 */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
|
|||
|
|
/* 17.1 */
|
|||
|
|
width cwell 10 \
|
|||
|
|
"Cap-well width must be at least 10 (MOSIS rule #17.1)"
|
|||
|
|
|
|||
|
|
/* 17.2 */
|
|||
|
|
spacing cwell cwell 9 touching_ok \
|
|||
|
|
"Cap-well spacing must be at least 9 (MOSIS rule #17.2)"
|
|||
|
|
spacing cwell nwell 9 touching_illegal \
|
|||
|
|
"Cap-well spacing must be at least 9 (MOSIS rule #17.2)"
|
|||
|
|
|
|||
|
|
/* 17.3 */
|
|||
|
|
edge4way cwell space 5 ~(allNActive)/a ~(allNActive)/w 5 \
|
|||
|
|
"Cap-well spacing to external active must be at least 5 (MOSIS rule #17.3)" active
|
|||
|
|
edge4way cwell space 3 ~(allPOhmic)/a ~(allPOhmic)/w 3 \
|
|||
|
|
"P-substrate diffusion and Cap-well must be separated by 3 (MOSIS rule #17.3)" active
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* 17.4 */
|
|||
|
|
/* Need to do this check from the Cap-well plane - in order Not */
|
|||
|
|
/* to conflict with the general rules for N-diffusion */
|
|||
|
|
edge4way space cwell 3 (space,poly,pc)/a 0 0 \
|
|||
|
|
"Cap-well overlap of diffusion must be at least 3 (MOSIS rule #17.4)" active
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Well-capacitor */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* These are DRC rules for Well-capacitor (wcap) according to HP's */
|
|||
|
|
/* 1.2um linear capacitor process pi@isi.edu 9/18/92 */
|
|||
|
|
/* Rule 18.5 and 18.6 are preliminary, they are conservative here! */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 18.1 */
|
|||
|
|
width wcap 3 \
|
|||
|
|
"Well-capacitor must be at least 3 (MOSIS rule #18.1)"
|
|||
|
|
|
|||
|
|
/* 18.2 */
|
|||
|
|
/* achieved by rule 3.5 */
|
|||
|
|
|
|||
|
|
/* 18.3 */
|
|||
|
|
edge4way wcap space 1 poly poly 1 \
|
|||
|
|
"Well-capacitor overhang is missing (MOSIS rule #18.3)"
|
|||
|
|
|
|||
|
|
/* 18.4 */
|
|||
|
|
edge4way wcap ndiff 3 ndiff ndiff 3 \
|
|||
|
|
"N-diffusion overlap of well-capacitor must be at least 3 (MOSIS rule #18.4)"
|
|||
|
|
|
|||
|
|
/* 18.5 */
|
|||
|
|
/* achieved by rule 5B.6 */
|
|||
|
|
spacing wcap pc 2 touching_illegal \
|
|||
|
|
"Well-capacitor spacing to poly contact must be at least 2 (MOSIS rule #18.5)"
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* 18.6 */
|
|||
|
|
/* similar to rule 6A.4 or 6B.6 */
|
|||
|
|
spacing wcap ndc 4 touching_illegal \
|
|||
|
|
"Well-capacitor spacing to diffusion contact must be at least 4 (MOSIS rule #18.6)"
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* Buried CCD */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 19.1 */
|
|||
|
|
/* Have to do it seperately... */
|
|||
|
|
width nbd,nbdc,bd/a 4 \
|
|||
|
|
"CCD channel width must be at least 4 (MOSIS rule #19.1)"
|
|||
|
|
width nbdc 4 \
|
|||
|
|
"CCD contact width must be at least 4 (MOSIS rule #19.1)"
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* 19.2 */
|
|||
|
|
/* The 4 lambda spacing is a conservative guess here... */
|
|||
|
|
/* This following rule will NOT work! Need to check 2 planes */
|
|||
|
|
/* separately.... */
|
|||
|
|
/*
|
|||
|
|
spacing bd/a,nbd,nbdc bd/a,nbd,nbdc 4 touching_ok \
|
|||
|
|
"CCD channel spacing must be at least 4 (MOSIS rule #19.2)"
|
|||
|
|
*/
|
|||
|
|
edge4way nbd,nbdc ~(bd,nbd,nbdc)/a 4 (bd,space)/i 0 0 \
|
|||
|
|
"CCD channel spacing must be at least 4 (MOSIS rule #19.2)" implant
|
|||
|
|
edge4way nbd,nbdc ~(poly,nbd,nbdc)/a 4 ~(poly,nbd,nbdc)/a ~(poly,nbd,nbdc)/a 4 \
|
|||
|
|
"CCD channel spacing must be at least 4 (MOSIS rule #19.2)" active
|
|||
|
|
|
|||
|
|
/* 19.3 + 19.4 + 19.5 */
|
|||
|
|
/* guaranteed by the CIF output generation */
|
|||
|
|
|
|||
|
|
/* 19.6 */
|
|||
|
|
/* This first one check poly and electrode overhang */
|
|||
|
|
edge4way bd space 2 nbd,poly,cap,el 0 0 \
|
|||
|
|
"CCD channel overhang is missing (MOSIS rule #19.6)" active
|
|||
|
|
/* There is a problem with capacitor overhang, I have no way to do */
|
|||
|
|
/* it now... */
|
|||
|
|
|
|||
|
|
/* MOSIS extension BCCD layout rule */
|
|||
|
|
spacing nbdc poly,el 1 touching_illegal \
|
|||
|
|
"CCD-diffusion contact spacing to poly must be at least 1 (MOSIS CCD rule)"
|
|||
|
|
edge4way nbd poly,el 1 bd 0 0 \
|
|||
|
|
"Missing Buried CCD Difussion layer (MOSIS CCD rule)" implant
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* High-Voltage MOSFETs */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* These are DRC rules for AMI 1.5 micron process for high-voltage */
|
|||
|
|
/* MOSFETs pi@isi.edu 10/01/92 */
|
|||
|
|
/* */
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* 20.1 */
|
|||
|
|
/* Well spacing for different potential must be 12 lambda away now. */
|
|||
|
|
/* These rules correspond to 1.1 + 1.2 rules */
|
|||
|
|
/* width rule is as usual */
|
|||
|
|
edge (~hnwell)/w hnwell 10 hnwell hnwell 10\
|
|||
|
|
"High-Voltage N-Well width must be at least 10 (MOSIS rule #1.1)"
|
|||
|
|
edge (~hpwell)/w hpwell 10 hpwell hpwell 10\
|
|||
|
|
"High-Voltage P-Well width must be at least 10 (MOSIS rule #1.1)"
|
|||
|
|
/* spacing rules are new */
|
|||
|
|
edge hnwell space,pw,hpw 9 space,pw,hpw space,pw,hpw 9\
|
|||
|
|
"High-Voltage N-Well spacing to N-Well must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
edge hpwell space,nw,hnw 9 space,nw,hnw space,nw,hnw 9\
|
|||
|
|
"High-Voltage P-Well spacing to P-Well must be at least 9 (MOSIS rule #1.2)"
|
|||
|
|
edge hnwell space,pw,hpw,nw 12 space,pw,hpw,nw space,pw,hpw,nw 12\
|
|||
|
|
"High-Voltage N-Well spacing must be at least 12 (MOSIS rule #20.1)"
|
|||
|
|
edge hpwell space,nw,hnw,pw 12 space,nw,hnw,pw space,nw,hnw,pw 12\
|
|||
|
|
"High-Voltage P-Well spacing must be at least 12 (MOSIS rule #20.1)"
|
|||
|
|
|
|||
|
|
/* 20.2 */
|
|||
|
|
/* High-Voltage Active spacing must be at least 5 lambda away */
|
|||
|
|
/* This rule corresponds to 2.2 rule */
|
|||
|
|
#define allHVNActive hndiff,hndc/a,hnfet
|
|||
|
|
#define allHVPActive hpdiff,hpdc/a,hpfet
|
|||
|
|
edge4way ~(allHVDiff)/a allHVDiff 3 allHVDiff allHVDiff 3\
|
|||
|
|
"High-Voltage Diffusion width must be at least 3 (MOSIS rule #2.1)"
|
|||
|
|
spacing allHVNActive allHVNActive 5 touching_ok \
|
|||
|
|
"High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)"
|
|||
|
|
spacing allHVPActive allHVPActive 5 touching_ok \
|
|||
|
|
"High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)"
|
|||
|
|
|
|||
|
|
/* 20.3 */
|
|||
|
|
/* High-Voltage transistors spacing to Well edge must be 7 lambda */
|
|||
|
|
/* This rule corresponds to rule 2.3 */
|
|||
|
|
/* without explicit well definition */
|
|||
|
|
spacing hndiff,hndc/a hpdiff,hpdc/a 14 touching_illegal \
|
|||
|
|
"P-type diffusion must be 14 away from N-type diffusion (MOSIS rule #20.3)"
|
|||
|
|
spacing hndiff,hndc/a allPDiff 12 touching_illegal \
|
|||
|
|
"P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)"
|
|||
|
|
spacing hpdiff,hpdc/a allNDiff 12 touching_illegal \
|
|||
|
|
"P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)"
|
|||
|
|
|
|||
|
|
/* with explicit well definition */
|
|||
|
|
spacing hndiff,hnfet,hndc/a hnwell 7 touching_illegal \
|
|||
|
|
"HVN-diffusion and HVN-well must be separated by 7 (MOSIS rule #20.3)"
|
|||
|
|
spacing hpdiff,hpfet,hpdc/a hpwell 7 touching_illegal \
|
|||
|
|
"HVP-diffusion and HVP-well must be separated by 7 (MOSIS rule #20.3)"
|
|||
|
|
spacing allNOhmic hpwell 3 touching_illegal \
|
|||
|
|
"N-substrate diffusion and HVP-well must be separated by 3 (MOSIS rule #2.4+20.3)"
|
|||
|
|
spacing allPOhmic hnwell 3 touching_illegal \
|
|||
|
|
"P-substrate diffusion and HVN-well must be separated by 3 (MOSIS rule #2.4+20.3)"
|
|||
|
|
|
|||
|
|
/* 20.4 */
|
|||
|
|
/* Poly1 must not be used as an transistor for high-voltage design */
|
|||
|
|
/* guaranteed by the composition rules */
|
|||
|
|
|
|||
|
|
/* 20.5 */
|
|||
|
|
/* High-Voltage Active overlap of contact is now 2 lambda */
|
|||
|
|
/* This rule corresponds to rule 6B.2 */
|
|||
|
|
edge (~hndc)/a hndc/a 6 hndc/a hndc/a 6\
|
|||
|
|
"High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)"
|
|||
|
|
edge (~hpdc)/a hpdc/a 6 hpdc/a hpdc/a 6\
|
|||
|
|
"High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)"
|
|||
|
|
|
|||
|
|
/* 20.6 */
|
|||
|
|
/* High-Voltage transistor channel length must be at least 4 lambda */
|
|||
|
|
edge hpdiff,hpdc/a hpfet 4 hpfet 0 0 \
|
|||
|
|
"High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)"
|
|||
|
|
edge hndiff,hndc/a hnfet 4 hnfet 0 0 \
|
|||
|
|
"High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)"
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* ---------------------------------------------------------------- */
|
|||
|
|
/* overlapping rules */
|
|||
|
|
exact_overlap m3c,m2c,ndc,pdc,pc,psc,nsc,ec,capc,clc,emc,pbc,hndc,hpdc,hnsc,hpsc
|
|||
|
|
no_overlap pfet,nfet pfet,nfet
|
|||
|
|
no_overlap epfet,enfet epfet,enfet
|
|||
|
|
no_overlap pffet,nffet pffet,nffet
|
|||
|
|
no_overlap hpfet,hnfet hpfet,hnfet
|
|||
|
|
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
extract
|
|||
|
|
|
|||
|
|
|
|||
|
|
|
|||
|
|
#ifndef OLD_EXTRACT_STYLE
|
|||
|
|
|
|||
|
|
#include "scmosExt.tech.in"
|
|||
|
|
|
|||
|
|
#else
|
|||
|
|
/* In the following, MOSIS provides 9 extraction styles as follows:
|
|||
|
|
|
|||
|
|
SCNA20(ORB) - ORBIT 2.0 micron low-noise analog N-well CMOS/BJT
|
|||
|
|
process. *default*
|
|||
|
|
SCPE20(ORB) - ORBIT 2.0 micron P-well CMOS/Bulk process.
|
|||
|
|
SCNA16(AMI) - AMI 1.6 micron N-well CMOS/Junction-isolated BJT
|
|||
|
|
process.
|
|||
|
|
SCN12LC(HP) - HP CMOS34 1.2 micron N-well CMOS/Bulk process with
|
|||
|
|
linear capacitor option.
|
|||
|
|
SCNE12(ORB) - ORBIT 1.2 micron 2 poly N/P-well CMOS process.
|
|||
|
|
SCN10(MOT) - MOTOROLA 1.0 micron N-well/P-epi CMOS process.
|
|||
|
|
* Not Available at this moment *
|
|||
|
|
SCN08(HP) - HP CMOS26B 1.0 micron N-well CMOS/Bulk process.
|
|||
|
|
SCN08(IBM) - IBM 0.8 micron N-well CMOS/Bulk process.
|
|||
|
|
* Not Available at this moment *
|
|||
|
|
|
|||
|
|
Whenever it is available, measured data on MOSIS test structures
|
|||
|
|
is used. Data is obtained from a representitive run (usually the
|
|||
|
|
latest run at the time). If not available, typical (or nominal)
|
|||
|
|
data from vendor wafer specification is used if not specifically
|
|||
|
|
noted.
|
|||
|
|
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Have to redefine allMetal1 to make it pure metal line here... */
|
|||
|
|
|
|||
|
|
#undef allMetal1
|
|||
|
|
#define allMetal1 m1,m2c/m1
|
|||
|
|
|
|||
|
|
|
|||
|
|
#ifdef STANDARD
|
|||
|
|
style SCNA20(ORB)
|
|||
|
|
/* The following data is obtained from MOSIS run 'n34o' */
|
|||
|
|
/* Last modified by pi@isi.edu, 9/29/93 */
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 100
|
|||
|
|
step 100
|
|||
|
|
/* No parallel wire coupling capacitances */
|
|||
|
|
sidehalo 0
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 27260
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 59550
|
|||
|
|
resist allPoly 23430
|
|||
|
|
resist allPoly2 19690
|
|||
|
|
resist em,emc/a 27260
|
|||
|
|
resist pbase,pbc/a 2000000
|
|||
|
|
resist metal1,m2c/metal1 52
|
|||
|
|
resist metal2,pad 26
|
|||
|
|
resist nwell 2505830
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohms per square) */
|
|||
|
|
contact pc/a 4 11000
|
|||
|
|
contact ec/a,capc/a 4 9000
|
|||
|
|
contact ndc/a,nsc/a 4 18710
|
|||
|
|
contact pdc/a,psc/a 4 100560
|
|||
|
|
|
|||
|
|
/* Area parasitic capacitance to substrate (in attofarads per
|
|||
|
|
lambda square)
|
|||
|
|
[ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ]
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly, remove the
|
|||
|
|
following comment. */
|
|||
|
|
areacap poly,pc/a 39
|
|||
|
|
areacap metal1,pad,m2c/metal1 24
|
|||
|
|
areacap metal2 19
|
|||
|
|
/*
|
|||
|
|
areacap ndiff,ndc/a 220
|
|||
|
|
areacap pdiff,pdc/a 270
|
|||
|
|
*/
|
|||
|
|
areacap cc/a,cap 39
|
|||
|
|
areacap poly2,ec/a 50
|
|||
|
|
|
|||
|
|
/* Inter-layer capacitance */
|
|||
|
|
overlap metal1 pdiff,ndiff,psd,nsd 47
|
|||
|
|
overlap metal2 pdiff,ndiff,psd,nsd 22 metal1
|
|||
|
|
overlap metal1 poly 30
|
|||
|
|
overlap metal2 poly 19 metal1
|
|||
|
|
overlap metal2 metal1 45
|
|||
|
|
overlap metal1 poly2 40
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitances (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ] */
|
|||
|
|
/*
|
|||
|
|
perimc ndiff,ndc/a space,pwell 559
|
|||
|
|
perimc pdiff,pdc/a space,nwell 402
|
|||
|
|
*/
|
|||
|
|
perimc poly,pc/a space,pwell,nwell 80
|
|||
|
|
|
|||
|
|
/* Active devices: N-Well process */
|
|||
|
|
fet pfet pdiff,pdc,pffet 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc,nffet 2 nfet GND! pwell 0 0
|
|||
|
|
fet epfet pdiff,pdc,pffet 2 epfet Vdd! 0 0
|
|||
|
|
fet enfet ndiff,ndc,nffet 2 enfet GND! 0 0
|
|||
|
|
|
|||
|
|
/* Kludge for MOS capacitance extraction, where source and drain
|
|||
|
|
are connected together */
|
|||
|
|
fet pfet pdiff,pdc,pffet 1 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc,nffet 1 nfet GND! pwell 0 0
|
|||
|
|
|
|||
|
|
/* Electrode capacitance extraction */
|
|||
|
|
device capacitor None cap,capc/a poly,pc 120 735
|
|||
|
|
|
|||
|
|
/* DRAM capacitance extraction */
|
|||
|
|
device capacitor None wcap ndiff,ndc 300 0
|
|||
|
|
|
|||
|
|
/* bipolar NPN extraction */
|
|||
|
|
device bjt npn emit,emc/a pbase,pbc/a nwell
|
|||
|
|
|
|||
|
|
style SCPE20(ORB)
|
|||
|
|
|
|||
|
|
/* The following data is obtained from MOSIS run 'n35s', 6/93 */
|
|||
|
|
/* Last modified by pi@isi.edu, 9/29/93 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 100
|
|||
|
|
step 100
|
|||
|
|
/* No parallel wire coupling capacitances */
|
|||
|
|
sidehalo 0
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 26670
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 72860
|
|||
|
|
resist allPoly 23860
|
|||
|
|
resist allPoly2 18540
|
|||
|
|
resist metal1,m2c/metal1 49
|
|||
|
|
resist metal2,pad 26
|
|||
|
|
resist pwell 2128280
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohm per contact) */
|
|||
|
|
contact pc/a 4 12800
|
|||
|
|
contact ec/a,capc/a 4 8420
|
|||
|
|
contact ndc/a,nsc/a 4 36660
|
|||
|
|
contact pdc/a,psc/a 4 56300
|
|||
|
|
contact m2c/m1 5 30
|
|||
|
|
|
|||
|
|
/* Area parasitic capacitance to substrate (in attofarads per
|
|||
|
|
lambda square)
|
|||
|
|
[ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ]
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly, remove the
|
|||
|
|
following comment. */
|
|||
|
|
areacap poly,pc/a 57
|
|||
|
|
areacap allMetal1,DiffMetal,HVDiffMetal 41
|
|||
|
|
areacap PolyMetal,BiMetal,CCDMetal 41
|
|||
|
|
areacap allMetal2 21
|
|||
|
|
/*
|
|||
|
|
areacap ndiff,ndc/a 398
|
|||
|
|
areacap pdiff,pdc/a 230
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Inter-layer capacitance */
|
|||
|
|
overlap metal1 pdiff,ndiff,psd,nsd 36
|
|||
|
|
overlap metal2 pdiff,ndiff,psd,nsd 16 metal1
|
|||
|
|
overlap metal1 poly 33
|
|||
|
|
overlap metal2 poly 15 metal1
|
|||
|
|
overlap metal2 metal1 29
|
|||
|
|
overlap metal1 poly2,cap 33
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitances (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ] */
|
|||
|
|
/*
|
|||
|
|
perimc ndiff,ndc/a space,pwell 423
|
|||
|
|
perimc pdiff,pdc/a space,nwell 85
|
|||
|
|
*/
|
|||
|
|
perimc poly,pc/a space,pwell,nwell 168
|
|||
|
|
|
|||
|
|
/* Active devices: P-Well process */
|
|||
|
|
fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc 2 nfet GND! pwell 0 0
|
|||
|
|
|
|||
|
|
|
|||
|
|
style SCNA16(AMI)
|
|||
|
|
|
|||
|
|
/* The following data is obtained from MOSIS run 'n34l', 6/93 */
|
|||
|
|
/* Last modified by pi@isi.edu, 9/29/93 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 80
|
|||
|
|
step 100
|
|||
|
|
/* No parallel wire coupling capacitances */
|
|||
|
|
sidehalo 0
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 51680
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 74800
|
|||
|
|
resist allPoly 34780
|
|||
|
|
resist allPoly2 22400
|
|||
|
|
resist allMetal1 48
|
|||
|
|
resist allMetal2 28
|
|||
|
|
resist nwell 1446400
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohm per contact) */
|
|||
|
|
contact pc 4 61560
|
|||
|
|
contact ec 4 12010
|
|||
|
|
contact ndc,nsc 4 45780
|
|||
|
|
contact pdc,psc 4 32310
|
|||
|
|
contact m2c 5 37570
|
|||
|
|
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.8 micron ---> multiplication factor 0.64 ]
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly, remove the
|
|||
|
|
following comment. */
|
|||
|
|
/* areacap nfet 709 */
|
|||
|
|
/* areacap pfet 669 */
|
|||
|
|
areacap poly,pc/a 22
|
|||
|
|
areacap allMetal1,DiffMetal,HVDiffMetal 15
|
|||
|
|
areacap PolyMetal,BiMetal,CCDMetal 15
|
|||
|
|
areacap allMetal2 10
|
|||
|
|
|
|||
|
|
/* Inter-layer capacitance */
|
|||
|
|
overlap allMetal1 ndiff,nsd 27
|
|||
|
|
overlap allMetal1 pdiff,psd 27
|
|||
|
|
overlap allMetal2 pdiff,psd 12 metal1
|
|||
|
|
overlap allMetal1 allPoly 25
|
|||
|
|
overlap allMetal1 allP2 25
|
|||
|
|
overlap allMetal2 allPoly 11 metal1
|
|||
|
|
overlap metal2 metal1 23
|
|||
|
|
/* Junction capacitance */
|
|||
|
|
/*
|
|||
|
|
overlap ndiff,ndc/a space,pwell 172
|
|||
|
|
overlap pdiff,pdc/a space,nwell 200
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitances (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.8 micron ---> multiplication factor 0.8 ] */
|
|||
|
|
/*
|
|||
|
|
perimc ndiff,ndc/a space,allWell 6
|
|||
|
|
perimc pdiff,pdc/a space,allWell 68
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Active devices: N-Well process, */
|
|||
|
|
fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc 2 nfet GND! pwell 0 0
|
|||
|
|
|
|||
|
|
|
|||
|
|
style SCNE12(ORB)
|
|||
|
|
|
|||
|
|
/* The following data is obtained from MOSIS run 'n37d', 7/93 */
|
|||
|
|
/* Last modified by pi@isi.edu, 9/29/93 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 60
|
|||
|
|
step 100
|
|||
|
|
/* No parallel wire coupling capacitances */
|
|||
|
|
sidehalo 0
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistances (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 43180
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 79770
|
|||
|
|
resist allPoly 22160
|
|||
|
|
resist allPoly2 21140
|
|||
|
|
resist allMetal1 51
|
|||
|
|
resist allMetal2 26
|
|||
|
|
resist nwell 1195000
|
|||
|
|
|
|||
|
|
/* Contact resistances (in milliohm per contact) */
|
|||
|
|
contact pc 4 13230
|
|||
|
|
contact ec 4 13510
|
|||
|
|
contact ndc,nsc 4 56490
|
|||
|
|
contact pdc,psc 4 181400
|
|||
|
|
contact m2c 5 43330
|
|||
|
|
|
|||
|
|
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.6 micron ---> multiplication factor 0.36 ]
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly, remove the
|
|||
|
|
following comment. */
|
|||
|
|
/* areacap nfet 454 */
|
|||
|
|
/* areacap pfet 368 */
|
|||
|
|
areacap poly,pc/a 29
|
|||
|
|
areacap allMetal1,DiffMetal,HVDiffMetal 16
|
|||
|
|
areacap PolyMetal,BiMetal,CCDMetal 16
|
|||
|
|
areacap allMetal2 10
|
|||
|
|
|
|||
|
|
overlap allMetal1 ndiff,ndc/a 22
|
|||
|
|
overlap allMetal1 allPoly 19
|
|||
|
|
overlap allMetal1 allP2 21
|
|||
|
|
overlap allMetal2 ndiff,ndc/a 8
|
|||
|
|
overlap allMetal2 allPoly 7
|
|||
|
|
overlap metal2 metal1 12
|
|||
|
|
/* Junction capacitance */
|
|||
|
|
overlap ndiff,ndc/a space,pwell 185
|
|||
|
|
overlap pdiff,pdc/a space,nwell 148
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitances (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.6 micron ---> multiplication factor 0.6 ] */
|
|||
|
|
perimc allMetal1 space,allWell 41
|
|||
|
|
perimc allMetal2 space,allWell 42
|
|||
|
|
/* Junction capacitances */
|
|||
|
|
/*
|
|||
|
|
perimc ndiff,ndc/a space,pwell 236
|
|||
|
|
perimc pdiff,pdc/a space,nwell 147
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* No measurements for this run, but leave here for future...
|
|||
|
|
sideoverlap allMetal1 space,allWell PNplus 60
|
|||
|
|
sideoverlap allMetal2 space,allWell allPoly 60
|
|||
|
|
sideoverlap allMetal2 space,allWell PNplus 57
|
|||
|
|
sideoverlap allMetal2 space,allWell allPoly 57
|
|||
|
|
sideoverlap allMetal2 space,allWell allMetal1 64
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Nwell process, so PMOS has "nwell" defined for analog
|
|||
|
|
designs... */
|
|||
|
|
fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc 2 nfet GND! pwell 0 0
|
|||
|
|
|
|||
|
|
|
|||
|
|
#endif /* STANDARD */
|
|||
|
|
|
|||
|
|
#ifdef TIGHTMETAL
|
|||
|
|
style SCN12LC(HP)
|
|||
|
|
|
|||
|
|
/* The following data is obtained from MOSIS run 'n36y', 7/93 */
|
|||
|
|
/* Last modified by pi@isi.edu, 9/29/93 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 60
|
|||
|
|
step 100
|
|||
|
|
/* No parallel wire coupling capacitances */
|
|||
|
|
sidehalo 0
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nnd,ndc/a,nsc/a 74630
|
|||
|
|
resist pdiff,ppd,pdc/a,psc/a 109590
|
|||
|
|
resist poly,pc/a,pfet,nfet 26620
|
|||
|
|
resist allMetal1 60
|
|||
|
|
resist allMetal2 39
|
|||
|
|
resist nwell 1500000
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohm per contact) */
|
|||
|
|
contact ndc 4 77000
|
|||
|
|
contact pdc 4 44260
|
|||
|
|
contact pc 4 16210
|
|||
|
|
contact m2c 5 86560
|
|||
|
|
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.6 micron ---> multiplication factor 0.36 ]
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly, remove the
|
|||
|
|
following comment. */
|
|||
|
|
/* areacap nfet 556 */
|
|||
|
|
/* areacap pfet 489 */
|
|||
|
|
areacap poly,pc/a 22
|
|||
|
|
areacap allMetal1,DiffMetal,HVDiffMetal 14
|
|||
|
|
areacap PolyMetal,BiMetal,CCDMetal 14
|
|||
|
|
areacap allMetal2 9
|
|||
|
|
|
|||
|
|
/* Inter-layer capacitance */
|
|||
|
|
overlap allMetal1 allPoly 24
|
|||
|
|
overlap allMetal2 allPoly 7 metal1
|
|||
|
|
overlap metal2 metal1 14
|
|||
|
|
/* Junction capacitance */
|
|||
|
|
/*
|
|||
|
|
overlap ndiff,ndc/a space,pwell 106
|
|||
|
|
overlap pdiff,pdc/a space,nwell 183
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitances (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.6 micron ---> multiplication factor 0.6 ] */
|
|||
|
|
/* perimc nfet ndiff 90 */
|
|||
|
|
/* perimc pfet pdiff 817 */
|
|||
|
|
/* Junction capacitances */
|
|||
|
|
/*
|
|||
|
|
perimc ndiff,ndc/a space,allWell 102
|
|||
|
|
perimc pdiff,pdc/a space,allWell 2
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* Active devices: Nwell process, so PMOS has "nwell" defined
|
|||
|
|
for analog designs... */
|
|||
|
|
fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc 2 nfet GND! pwell 0 0
|
|||
|
|
/* Kludge for DRAM capacitance extraction */
|
|||
|
|
fet wcap ndiff,ndc 1 wcap GND! 300 0
|
|||
|
|
|
|||
|
|
/* These stuff are experimental.....
|
|||
|
|
fake npn:
|
|||
|
|
fet emit,emc/a pbase 1 d1np XSLLU! nwell 0 0
|
|||
|
|
fet fpb nwell 1 d2pn YSLLU! col,clc 0 0
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
/* saturation :: R = V (5V) / Idss
|
|||
|
|
fetresist nfet saturation 12000
|
|||
|
|
fetresist pfet saturation 28000
|
|||
|
|
fetresist enfet saturation 12000
|
|||
|
|
fetresist epfet saturation 28000
|
|||
|
|
|
|||
|
|
I am not sure how to do this yet, so I give the same value as
|
|||
|
|
saturation!
|
|||
|
|
|
|||
|
|
fetresist nfet linear 12000
|
|||
|
|
fetresist pfet linear 28000
|
|||
|
|
fetresist enfet linear 12000
|
|||
|
|
fetresist epfet linear 28000
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
|
|||
|
|
style SCN08(HP)
|
|||
|
|
|
|||
|
|
/* The following data is obtained from MOSIS run 'n33h', 7/93 */
|
|||
|
|
/* Last modified by pi@isi.edu, 9/29/93 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 50
|
|||
|
|
step 100
|
|||
|
|
/* Parallel wire coupling capacitance enabled */
|
|||
|
|
sidehalo 8
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 2280
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 1990
|
|||
|
|
resist poly 3480
|
|||
|
|
resist allMetal1 67
|
|||
|
|
resist allMetal2 65
|
|||
|
|
resist allMetal3 29
|
|||
|
|
resist nwell 1265560
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohm per contact) */
|
|||
|
|
contact pc 4 1680
|
|||
|
|
contact ndc,pdc,nsc,psc 4 1100
|
|||
|
|
contact m2c 5 305
|
|||
|
|
contact m3c 5 259
|
|||
|
|
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.5 micron ---> multiplication factor 0.25 ]
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly, remove the
|
|||
|
|
following comment. */
|
|||
|
|
/* areacap nfet 457 */
|
|||
|
|
/* areacap pfet 403 */
|
|||
|
|
areacap poly,pc/a 16
|
|||
|
|
areacap allMetal1,DiffMetal,HVDiffMetal 9
|
|||
|
|
areacap PolyMetal,BiMetal,CCDMetal 9
|
|||
|
|
areacap allMetal2 5
|
|||
|
|
areacap allMetal3 4
|
|||
|
|
|
|||
|
|
/* Inter-layer capacitance */
|
|||
|
|
overlap allMetal1 PNplus 13
|
|||
|
|
overlap allMetal1 allPoly 13
|
|||
|
|
overlap allMetal2 PNplus 4
|
|||
|
|
overlap allMetal2 allPoly 4
|
|||
|
|
overlap allMetal2 allMetal1 6
|
|||
|
|
overlap allMetal3 PNplus 2
|
|||
|
|
overlap allMetal3 allPoly 2
|
|||
|
|
overlap allMetal3 allMetal1 3
|
|||
|
|
overlap allMetal3 allMetal2 7
|
|||
|
|
/* Junction capacitance */
|
|||
|
|
overlap ndiff,ndc/a space,pwell 27
|
|||
|
|
overlap pdiff,pdc/a space,nwell 148
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitance (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.5 micron ---> multiplication factor 0.5 ] */
|
|||
|
|
perimc allMetal1 space,allWell 43
|
|||
|
|
perimc allMetal2 space,allWell 36
|
|||
|
|
perimc allMetal3 space,allWell 36
|
|||
|
|
|
|||
|
|
sideoverlap allMetal1 space,allWell allPoly 14
|
|||
|
|
sideoverlap allMetal2 space,allWell allPoly 5
|
|||
|
|
/* no such data for m2-to-m1, use data from specification file */
|
|||
|
|
sideoverlap allMetal2 space,allWell allMetal1 13
|
|||
|
|
sideoverlap allMetal3 space,allWell allPoly 1
|
|||
|
|
sideoverlap allMetal3 space,allWell allMetal1 4
|
|||
|
|
sideoverlap allMetal3 space,allWell allMetal2 13
|
|||
|
|
|
|||
|
|
/* Active devices: N-well process */
|
|||
|
|
fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc 2 nfet GND! pwell 0 0
|
|||
|
|
|
|||
|
|
#endif /* TIGHTMETAL */
|
|||
|
|
|
|||
|
|
#ifdef IBMTECH
|
|||
|
|
style SCN08(IBM)
|
|||
|
|
|
|||
|
|
/* The following data is obtained from MOSIS run 'n42s', 1/94 */
|
|||
|
|
/* Last modified by pi@isi.edu, 6/27/94 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 40
|
|||
|
|
step 100
|
|||
|
|
/* Parallel wire coupling capacitance disabled */
|
|||
|
|
sidehalo 0
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 3300
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 3180
|
|||
|
|
resist poly 3630
|
|||
|
|
resist allMetal1 43
|
|||
|
|
resist allMetal2 36
|
|||
|
|
resist allMetal3 36
|
|||
|
|
/* not monitored on PCM, use specification value */
|
|||
|
|
resist nwell 520000
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohm per contact) */
|
|||
|
|
contact ndc,nsc 4 2530
|
|||
|
|
contact pc 4 7510
|
|||
|
|
contact pdc,psc 4 2160
|
|||
|
|
contact m2c 5 330
|
|||
|
|
contact m3c 5 292
|
|||
|
|
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.4 micron ---> multiplication factor 0.16 ] */
|
|||
|
|
#endif /* IBMTECH */
|
|||
|
|
|
|||
|
|
#ifdef SUBMICRON
|
|||
|
|
style SCN08(HP26G)
|
|||
|
|
|
|||
|
|
/* The following data is obtained from MOSIS run 'n48r', 10/94 */
|
|||
|
|
/* Last modified by pi@isi.edu, 11/02/94 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 40
|
|||
|
|
step 100
|
|||
|
|
/* Parallel wire coupling capacitance enabled */
|
|||
|
|
sidehalo 8
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 2375
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 2000
|
|||
|
|
resist allPoly 2350
|
|||
|
|
resist allMetal1 70
|
|||
|
|
resist allMetal2 67
|
|||
|
|
resist allMetal3 30
|
|||
|
|
resist nwell 1265000
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohm per contact) */
|
|||
|
|
contact pc 4 1250
|
|||
|
|
contact ndc,nsc 4 1300
|
|||
|
|
contact pdc,psc 4 1125
|
|||
|
|
contact m2c 5 430
|
|||
|
|
contact m3c 5 300
|
|||
|
|
|
|||
|
|
/* The following are 10 types of capacitance extracted:
|
|||
|
|
1. poly to substrate.
|
|||
|
|
2. metal1 to substrate.
|
|||
|
|
3. metal1 to poly.
|
|||
|
|
4. metal2 to substrate.
|
|||
|
|
5. metal2 to poly.
|
|||
|
|
6. metal2 to metal1.
|
|||
|
|
7. metal3 to substrate.
|
|||
|
|
8. metal3 to poly.
|
|||
|
|
9. metal3 to metal1.
|
|||
|
|
10. metal3 to metal2.
|
|||
|
|
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly,
|
|||
|
|
remove the following comment. */
|
|||
|
|
/* areacap nfet 334 */
|
|||
|
|
/* areacap pfet 315 */
|
|||
|
|
|
|||
|
|
/* Type 1,2,4,7 (to substrate) */
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.4 micron ---> multiplication factor 0.16 ] */
|
|||
|
|
areacap poly,pc/a 13
|
|||
|
|
areacap allMetal1,DiffMetal,HVDiffMetal 6
|
|||
|
|
areacap PolyMetal,BiMetal,CCDMetal 6
|
|||
|
|
areacap allMetal2 3
|
|||
|
|
areacap allMetal3 2
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitance (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.4 micron ---> multiplication factor 0.4 ] */
|
|||
|
|
perimc poly,pc/a ~(poly,pc/a) 19
|
|||
|
|
perimc allMetal1 ~(allMetal1) 20
|
|||
|
|
perimc allMetal2 ~(allMetal2) 16
|
|||
|
|
perimc allMetal3 ~(allMetal3) 14
|
|||
|
|
|
|||
|
|
/* Inter-layer capacitance, type 3,5,6,8,9,10 */
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.4 micron ---> multiplication factor 0.16 ] */
|
|||
|
|
overlap allMetal1 allPoly 9
|
|||
|
|
overlap allMetal2 allPoly 3
|
|||
|
|
overlap allMetal2 allMetal1 5
|
|||
|
|
overlap allMetal3 allPoly 2
|
|||
|
|
overlap allMetal3 allMetal1 3
|
|||
|
|
overlap allMetal3 allMetal2 5
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitance (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.4 micron ---> multiplication factor 0.4 ] */
|
|||
|
|
sideoverlap allMetal1 space,allWell allPoly 23
|
|||
|
|
sideoverlap allMetal2 space,allWell allPoly 17
|
|||
|
|
sideoverlap allMetal2 space,allWell allMetal1 19
|
|||
|
|
sideoverlap allMetal3 space,allWell allPoly 15
|
|||
|
|
sideoverlap allMetal3 space,allWell allMetal1 17
|
|||
|
|
sideoverlap allMetal3 space,allWell allMetal2 21
|
|||
|
|
|
|||
|
|
/* Cross-couple capacitance */
|
|||
|
|
/* Perimeter parasitic capacitance (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.4 micron ---> multiplication factor 0.4 ] */
|
|||
|
|
sidewall allP ~(allP) ~(allP) allP 11
|
|||
|
|
sidewall allMetal1 ~(allMetal1) ~(allMetal1) allMetal1 24
|
|||
|
|
sidewall allMetal2 ~(allMetal2) ~(allMetal2) allMetal2 27
|
|||
|
|
sidewall allMetal3 ~(allMetal3) ~(allMetal3) allMetal3 39
|
|||
|
|
|
|||
|
|
/* Active devices: N-well process */
|
|||
|
|
fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc 2 nfet GND! pwell 0 0
|
|||
|
|
|
|||
|
|
|
|||
|
|
style SCN06(HP14B)
|
|||
|
|
|
|||
|
|
/* Not yet.... */
|
|||
|
|
/* Last modified by pi@isi.edu, 03/10/95 */
|
|||
|
|
|
|||
|
|
cscale 1
|
|||
|
|
lambda 30
|
|||
|
|
step 100
|
|||
|
|
/* Parallel wire coupling capacitance enabled */
|
|||
|
|
sidehalo 8
|
|||
|
|
|
|||
|
|
/* Define plane order first */
|
|||
|
|
#ifdef V5
|
|||
|
|
planeorder well 0
|
|||
|
|
planeorder implant 1
|
|||
|
|
planeorder active 2
|
|||
|
|
planeorder metal1 3
|
|||
|
|
planeorder metal2 4
|
|||
|
|
planeorder metal3 5
|
|||
|
|
planeorder oxide 6
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
/* Sheet resistance (in milliohms per square) */
|
|||
|
|
resist ndiff,nsd,ndc/a,nsc/a 2375
|
|||
|
|
resist pdiff,psd,pdc/a,psc/a 2000
|
|||
|
|
resist allPoly 2350
|
|||
|
|
resist allMetal1 70
|
|||
|
|
resist allMetal2 67
|
|||
|
|
resist allMetal3 30
|
|||
|
|
resist nwell 1265000
|
|||
|
|
|
|||
|
|
/* Contact resistance (in milliohm per contact) */
|
|||
|
|
contact pc 4 1250
|
|||
|
|
contact ndc,nsc 4 1300
|
|||
|
|
contact pdc,psc 4 1125
|
|||
|
|
contact m2c 5 430
|
|||
|
|
contact m3c 5 300
|
|||
|
|
|
|||
|
|
/* The following are 10 types of capacitance extracted:
|
|||
|
|
1. poly to substrate.
|
|||
|
|
2. metal1 to substrate.
|
|||
|
|
3. metal1 to poly.
|
|||
|
|
4. metal2 to substrate.
|
|||
|
|
5. metal2 to poly.
|
|||
|
|
6. metal2 to metal1.
|
|||
|
|
7. metal3 to substrate.
|
|||
|
|
8. metal3 to poly.
|
|||
|
|
9. metal3 to metal1.
|
|||
|
|
10. metal3 to metal2.
|
|||
|
|
|
|||
|
|
NOTE: Since most of the simulation tools have already
|
|||
|
|
included the gate-oxide capacitance, it is NOT
|
|||
|
|
extracted here. If you need it explictly,
|
|||
|
|
remove the following comment. */
|
|||
|
|
/* areacap nfet 334 */
|
|||
|
|
/* areacap pfet 315 */
|
|||
|
|
|
|||
|
|
/* Type 1,2,4,7 (to substrate) */
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.3 micron ---> multiplication factor 0.09 ] */
|
|||
|
|
areacap poly,pc/a 7
|
|||
|
|
areacap allMetal1,DiffMetal,HVDiffMetal 3
|
|||
|
|
areacap PolyMetal,BiMetal,CCDMetal 3
|
|||
|
|
areacap allMetal2 1
|
|||
|
|
areacap allMetal3 1
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitance (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.3 micron ---> multiplication factor 0.3 ] */
|
|||
|
|
perimc poly,pc/a ~(poly,pc/a) 14
|
|||
|
|
perimc allMetal1 ~(allMetal1) 15
|
|||
|
|
perimc allMetal2 ~(allMetal2) 12
|
|||
|
|
perimc allMetal3 ~(allMetal3) 10
|
|||
|
|
|
|||
|
|
/* Inter-layer capacitance, type 3,5,6,8,9,10 */
|
|||
|
|
/* Area parasitic capacitances (in attofarads per lambda square)
|
|||
|
|
[ 1 lambda = 0.3 micron ---> multiplication factor 0.09 ] */
|
|||
|
|
overlap allMetal1 allPoly 5
|
|||
|
|
overlap allMetal2 allPoly 2
|
|||
|
|
overlap allMetal2 allMetal1 3
|
|||
|
|
overlap allMetal3 allPoly 1
|
|||
|
|
overlap allMetal3 allMetal1 1
|
|||
|
|
overlap allMetal3 allMetal2 3
|
|||
|
|
|
|||
|
|
/* Perimeter parasitic capacitance (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.3 micron ---> multiplication factor 0.3 ] */
|
|||
|
|
sideoverlap allMetal1 space,allWell allPoly 17
|
|||
|
|
sideoverlap allMetal2 space,allWell allPoly 14
|
|||
|
|
sideoverlap allMetal2 space,allWell allMetal1 15
|
|||
|
|
sideoverlap allMetal3 space,allWell allPoly 11
|
|||
|
|
sideoverlap allMetal3 space,allWell allMetal1 13
|
|||
|
|
sideoverlap allMetal3 space,allWell allMetal2 16
|
|||
|
|
|
|||
|
|
/* Cross-couple capacitance */
|
|||
|
|
/* Perimeter parasitic capacitance (in attofarads per lambda)
|
|||
|
|
[ 1 lambda = 0.3 micron ---> multiplication factor 0.3 ] */
|
|||
|
|
sidewall allP ~(allP) ~(allP) allP 9
|
|||
|
|
sidewall allMetal1 ~(allMetal1) ~(allMetal1) allMetal1 19
|
|||
|
|
sidewall allMetal2 ~(allMetal2) ~(allMetal2) allMetal2 21
|
|||
|
|
sidewall allMetal3 ~(allMetal3) ~(allMetal3) allMetal3 31
|
|||
|
|
|
|||
|
|
/* Active devices: N-well process */
|
|||
|
|
fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0
|
|||
|
|
fet nfet ndiff,ndc 2 nfet GND! pwell 0 0
|
|||
|
|
|
|||
|
|
#endif /* SUBMICRON */
|
|||
|
|
|
|||
|
|
#endif /* OLD_EXTRACT_STYLE */
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
|
|||
|
|
wiring
|
|||
|
|
contact pdcontact 4 pdiff 0 metal1 0
|
|||
|
|
contact ndcontact 4 ndiff 0 metal1 0
|
|||
|
|
contact pcontact 4 poly 0 metal1 0
|
|||
|
|
contact ec 6 poly2 0 metal1 0
|
|||
|
|
contact m2contact 4 metal1 0 metal2 0
|
|||
|
|
contact m3contact 5 metal2 0 metal3 0
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
router
|
|||
|
|
layer1 metal1 3 allMetal1 3
|
|||
|
|
layer2 metal2 3 allMetal2 4 allPoly,allDiff 1
|
|||
|
|
contacts m2contact 4
|
|||
|
|
gridspacing 8
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
plowing
|
|||
|
|
fixed allFet,glass,pad
|
|||
|
|
covered allFet
|
|||
|
|
drag allFet
|
|||
|
|
end
|
|||
|
|
|
|||
|
|
plot
|
|||
|
|
/* based on Jeffrey C. Gealow's (jgealow@mtl.mit.edu) contribution */
|
|||
|
|
style colorversatec
|
|||
|
|
|
|||
|
|
ndiff,ndc yellow \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA
|
|||
|
|
|
|||
|
|
ndiff,ndc cyan \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555
|
|||
|
|
|
|||
|
|
|
|||
|
|
nsd,nsc,col,clc yellow \
|
|||
|
|
1515 2A2A 5151 A2A2 \
|
|||
|
|
1515 2A2A 5151 A2A2 \
|
|||
|
|
1515 2A2A 5151 A2A2 \
|
|||
|
|
1515 2A2A 5151 A2A2
|
|||
|
|
|
|||
|
|
nsd,nsc,col,clc cyan \
|
|||
|
|
0000 1515 0000 5151 \
|
|||
|
|
0000 1515 0000 5151 \
|
|||
|
|
0000 1515 0000 5151 \
|
|||
|
|
0000 1515 0000 5151
|
|||
|
|
|
|||
|
|
|
|||
|
|
pdiff,pdc yellow \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA
|
|||
|
|
|
|||
|
|
pdiff,pdc cyan \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555
|
|||
|
|
|
|||
|
|
pdiff,pdc magenta \
|
|||
|
|
AAAA 0000 AAAA 0000 \
|
|||
|
|
AAAA 0000 AAAA 0000 \
|
|||
|
|
AAAA 0000 AAAA 0000 \
|
|||
|
|
AAAA 0000 AAAA 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
psd,psc yellow \
|
|||
|
|
1515 2A2A 5151 A2A2 \
|
|||
|
|
1515 2A2A 5151 A2A2 \
|
|||
|
|
1515 2A2A 5151 A2A2 \
|
|||
|
|
1515 2A2A 5151 A2A2
|
|||
|
|
|
|||
|
|
psd,psc cyan \
|
|||
|
|
0000 1515 0000 5151 \
|
|||
|
|
0000 1515 0000 5151 \
|
|||
|
|
0000 1515 0000 5151 \
|
|||
|
|
0000 1515 0000 5151
|
|||
|
|
|
|||
|
|
psd,psc magenta \
|
|||
|
|
2A2A 0000 A2A2 0000 \
|
|||
|
|
2A2A 0000 A2A2 0000 \
|
|||
|
|
2A2A 0000 A2A2 0000 \
|
|||
|
|
2A2A 0000 A2A2 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
poly,pc/a magenta \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA
|
|||
|
|
|
|||
|
|
|
|||
|
|
poly2,ec/a yellow \
|
|||
|
|
FFFF FFFF FFFF FFFF \
|
|||
|
|
FFFF FFFF FFFF FFFF \
|
|||
|
|
FFFF FFFF FFFF FFFF \
|
|||
|
|
FFFF FFFF FFFF FFFF
|
|||
|
|
|
|||
|
|
|
|||
|
|
nfet yellow \
|
|||
|
|
0505 8282 1414 0A0A \
|
|||
|
|
5050 2828 4141 A0A0 \
|
|||
|
|
0505 8282 1414 0A0A \
|
|||
|
|
5050 2828 4141 A0A0
|
|||
|
|
|
|||
|
|
nfet cyan \
|
|||
|
|
0000 0505 0000 1414 \
|
|||
|
|
0000 5050 0000 4141 \
|
|||
|
|
0000 0505 0000 1414 \
|
|||
|
|
0000 5050 0000 4141
|
|||
|
|
|
|||
|
|
nfet magenta \
|
|||
|
|
5050 2828 4141 A0A0 \
|
|||
|
|
0505 8282 1414 0A0A \
|
|||
|
|
5050 2828 4141 A0A0 \
|
|||
|
|
0505 8282 1414 0A0A
|
|||
|
|
|
|||
|
|
|
|||
|
|
enfet yellow \
|
|||
|
|
BABA 7575 EAEA D5D5 \
|
|||
|
|
ABAB 5757 AEAE 5D5D \
|
|||
|
|
BABA 7575 EAEA D5D5 \
|
|||
|
|
ABAB 5757 AEAE 5D5D
|
|||
|
|
|
|||
|
|
enfet cyan \
|
|||
|
|
4141 0A0A 0505 2828 \
|
|||
|
|
1414 A0A0 5050 8282 \
|
|||
|
|
4141 0A0A 0505 2828 \
|
|||
|
|
1414 A0A0 5050 8282
|
|||
|
|
|
|||
|
|
|
|||
|
|
nffet yellow \
|
|||
|
|
8E8E 0707 8B8B D5D5 \
|
|||
|
|
E8E8 7070 B8B8 5D5D \
|
|||
|
|
8E8E 0707 8B8B D5D5 \
|
|||
|
|
E8E8 7070 B8B8 5D5D
|
|||
|
|
|
|||
|
|
nffet cyan \
|
|||
|
|
0101 0808 1414 2828 \
|
|||
|
|
1010 8080 4141 8282 \
|
|||
|
|
0101 0808 1414 2828 \
|
|||
|
|
1010 8080 4141 8282
|
|||
|
|
|
|||
|
|
nffet magenta \
|
|||
|
|
5050 A0A0 4040 0202 \
|
|||
|
|
0505 0A0A 0404 2020 \
|
|||
|
|
5050 A0A0 4040 0202 \
|
|||
|
|
0505 0A0A 0404 2020
|
|||
|
|
|
|||
|
|
|
|||
|
|
pfet yellow \
|
|||
|
|
6363 A0A0 5050 2828 \
|
|||
|
|
3636 0A0A 0505 8282 \
|
|||
|
|
6363 A0A0 5050 2828 \
|
|||
|
|
3636 0A0A 0505 8282
|
|||
|
|
|
|||
|
|
pfet cyan \
|
|||
|
|
0000 5151 0000 5454 \
|
|||
|
|
0000 1515 0000 1515 \
|
|||
|
|
0000 5151 0000 5454 \
|
|||
|
|
0000 1515 0000 1515
|
|||
|
|
|
|||
|
|
pfet magenta \
|
|||
|
|
9494 0A0A 2525 8282 \
|
|||
|
|
4949 A0A0 5252 2828 \
|
|||
|
|
9494 0A0A 2525 8282 \
|
|||
|
|
4949 A0A0 5252 2828
|
|||
|
|
|
|||
|
|
|
|||
|
|
epfet yellow \
|
|||
|
|
BCBC 4F4F 2F2F D3D3 \
|
|||
|
|
CBCB F4F4 F2F2 3D3D \
|
|||
|
|
BCBC 4F4F 2F2F D3D3 \
|
|||
|
|
CBCB F4F4 F2F2 3D3D
|
|||
|
|
|
|||
|
|
epfet cyan \
|
|||
|
|
0000 A0A0 0000 2828 \
|
|||
|
|
0000 0A0A 0000 8282 \
|
|||
|
|
0000 A0A0 0000 2828 \
|
|||
|
|
0000 0A0A 0000 8282
|
|||
|
|
|
|||
|
|
epfet magenta \
|
|||
|
|
4141 0000 5050 0000 \
|
|||
|
|
1414 0000 0505 0000 \
|
|||
|
|
4141 0000 5050 0000 \
|
|||
|
|
1414 0000 0505 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
pffet yellow \
|
|||
|
|
7B7B F0F0 F0F0 E9E9 \
|
|||
|
|
B7B7 0F0F 0F0F 9E9E \
|
|||
|
|
7B7B F0F0 F0F0 E9E9 \
|
|||
|
|
B7B7 0F0F 0F0F 9E9E
|
|||
|
|
|
|||
|
|
pffet cyan \
|
|||
|
|
0000 0101 0000 1414 \
|
|||
|
|
0000 1010 0000 4141 \
|
|||
|
|
0000 0101 0000 1414 \
|
|||
|
|
0000 1010 0000 4141
|
|||
|
|
|
|||
|
|
pffet magenta \
|
|||
|
|
8484 0A0A 2525 8282 \
|
|||
|
|
4848 A0A0 5252 2828 \
|
|||
|
|
8484 0A0A 2525 8282 \
|
|||
|
|
4848 A0A0 5252 2828
|
|||
|
|
|
|||
|
|
|
|||
|
|
cap,cc/a yellow \
|
|||
|
|
3E3E 7777 E3E3 C1C1 \
|
|||
|
|
E3E3 7777 3E3E 1C1C \
|
|||
|
|
3E3E 7777 E3E3 C1C1 \
|
|||
|
|
E3E3 7777 3E3E 1C1C
|
|||
|
|
|
|||
|
|
cap,cc/a magenta \
|
|||
|
|
4141 8888 1414 2A2A \
|
|||
|
|
1414 8888 4141 A2A2 \
|
|||
|
|
4141 8888 1414 2A2A \
|
|||
|
|
1414 8888 4141 A2A2
|
|||
|
|
|
|||
|
|
|
|||
|
|
allMetal1 cyan \
|
|||
|
|
AAAA 0000 AAAA 0000 \
|
|||
|
|
AAAA 0000 AAAA 0000 \
|
|||
|
|
AAAA 0000 AAAA 0000 \
|
|||
|
|
AAAA 0000 AAAA 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
allMetal2 cyan \
|
|||
|
|
0000 1111 0000 4444 \
|
|||
|
|
0000 1111 0000 4444 \
|
|||
|
|
0000 1111 0000 4444 \
|
|||
|
|
0000 1111 0000 4444
|
|||
|
|
|
|||
|
|
allMetal2 magenta \
|
|||
|
|
0000 4444 0000 1111 \
|
|||
|
|
0000 4444 0000 1111 \
|
|||
|
|
0000 4444 0000 1111 \
|
|||
|
|
0000 4444 0000 1111
|
|||
|
|
|
|||
|
|
|
|||
|
|
m2c/m1 black \
|
|||
|
|
0000 6666 6666 0000 \
|
|||
|
|
0000 9999 9999 0000 \
|
|||
|
|
0000 6666 6666 0000 \
|
|||
|
|
0000 9999 9999 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
pad,glass black \
|
|||
|
|
0300 0700 0E00 1C00 \
|
|||
|
|
3800 7000 E000 C000 \
|
|||
|
|
00C0 00E0 0070 0038 \
|
|||
|
|
001C 000E 0007 0003
|
|||
|
|
|
|||
|
|
|
|||
|
|
nwell yellow \
|
|||
|
|
0800 1000 2000 4000 \
|
|||
|
|
8000 0001 0002 0004 \
|
|||
|
|
0008 0010 0020 0040 \
|
|||
|
|
0080 0010 0200 0400
|
|||
|
|
|
|||
|
|
nwell cyan \
|
|||
|
|
1000 2000 4000 8000 \
|
|||
|
|
0001 0002 0004 0008 \
|
|||
|
|
0010 0020 0040 0080 \
|
|||
|
|
0100 0200 0400 0800
|
|||
|
|
|
|||
|
|
|
|||
|
|
pwell yellow \
|
|||
|
|
1000 0400 0400 0100 \
|
|||
|
|
0100 0040 0040 0010 \
|
|||
|
|
0010 0004 0004 0001 \
|
|||
|
|
0001 4000 4000 1000
|
|||
|
|
|
|||
|
|
pwell cyan \
|
|||
|
|
0000 0800 0000 0200 \
|
|||
|
|
0000 0080 0000 0020 \
|
|||
|
|
0000 0008 0000 0002 \
|
|||
|
|
0000 8000 0000 2000
|
|||
|
|
|
|||
|
|
pwell magenta \
|
|||
|
|
0800 0000 0200 0000 \
|
|||
|
|
0080 0000 0020 0000 \
|
|||
|
|
0008 0000 0002 0000 \
|
|||
|
|
8000 0000 2000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
bd yellow \
|
|||
|
|
4444 8888 4444 8888 \
|
|||
|
|
4444 8888 4444 8888 \
|
|||
|
|
4444 8888 4444 8888 \
|
|||
|
|
4444 8888 4444 8888
|
|||
|
|
|
|||
|
|
bd cyan \
|
|||
|
|
0000 4444 0000 4444 \
|
|||
|
|
0000 4444 0000 4444 \
|
|||
|
|
0000 4444 0000 4444 \
|
|||
|
|
0000 4444 0000 4444
|
|||
|
|
|
|||
|
|
bd magenta \
|
|||
|
|
8888 0000 8888 0000 \
|
|||
|
|
8888 0000 8888 0000 \
|
|||
|
|
8888 0000 8888 0000 \
|
|||
|
|
8888 0000 8888 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
nbd,nbdc yellow \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA \
|
|||
|
|
5555 AAAA 5555 AAAA
|
|||
|
|
|
|||
|
|
nbd,nbdc cyan \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555 \
|
|||
|
|
0000 5555 0000 5555
|
|||
|
|
|
|||
|
|
nbd,nbdc magenta \
|
|||
|
|
8888 0000 8888 0000 \
|
|||
|
|
8888 0000 8888 0000 \
|
|||
|
|
8888 0000 8888 0000 \
|
|||
|
|
8888 0000 8888 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
em,emc yellow \
|
|||
|
|
4444 8888 4444 8888 \
|
|||
|
|
4444 8888 4444 8888 \
|
|||
|
|
4444 8888 4444 8888 \
|
|||
|
|
4444 8888 4444 8888
|
|||
|
|
|
|||
|
|
em,emc cyan \
|
|||
|
|
0000 4444 0000 4444 \
|
|||
|
|
0000 4444 0000 4444 \
|
|||
|
|
0000 4444 0000 4444 \
|
|||
|
|
0000 4444 0000 4444
|
|||
|
|
|
|||
|
|
|
|||
|
|
pbase,pbc yellow \
|
|||
|
|
5555 AAAA 0000 0000 \
|
|||
|
|
5555 AAAA 0000 0000 \
|
|||
|
|
5555 AAAA 0000 0000 \
|
|||
|
|
5555 AAAA 0000 0000
|
|||
|
|
|
|||
|
|
pbase,pbc cyan \
|
|||
|
|
0000 5555 0000 0000 \
|
|||
|
|
0000 5555 0000 0000 \
|
|||
|
|
0000 5555 0000 0000 \
|
|||
|
|
0000 5555 0000 0000
|
|||
|
|
|
|||
|
|
pbase,pbc magenta \
|
|||
|
|
AAAA 0000 0000 0000 \
|
|||
|
|
AAAA 0000 0000 0000 \
|
|||
|
|
AAAA 0000 0000 0000 \
|
|||
|
|
AAAA 0000 0000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
allMetal3 black \
|
|||
|
|
0100 0000 0000 0000 \
|
|||
|
|
1010 0000 0000 0000 \
|
|||
|
|
0001 0000 0000 0000 \
|
|||
|
|
1010 0000 0000 0000
|
|||
|
|
|
|||
|
|
allMetal3 cyan \
|
|||
|
|
0280 0000 0820 0000 \
|
|||
|
|
2008 0000 8002 0000 \
|
|||
|
|
8002 0000 2008 0000 \
|
|||
|
|
0820 0000 0280 0000
|
|||
|
|
|
|||
|
|
allMetal3 magenta \
|
|||
|
|
0100 06C0 0440 1830 \
|
|||
|
|
1010 600C 4004 8003 \
|
|||
|
|
0001 C006 4004 3018 \
|
|||
|
|
1010 0C60 0440 0380
|
|||
|
|
|
|||
|
|
|
|||
|
|
m3c/m2 black \
|
|||
|
|
0820 0820 0820 0FE0 \
|
|||
|
|
E00F 2008 2008 2008 \
|
|||
|
|
2008 2008 2008 E00F \
|
|||
|
|
0000 0FE0 0820 0820
|
|||
|
|
|
|||
|
|
|
|||
|
|
error_p,error_s,error_ps black \
|
|||
|
|
0000 3C3C 4646 4A4A \
|
|||
|
|
5252 6262 3C3C 0000 \
|
|||
|
|
0000 3C3C 4646 4A4A \
|
|||
|
|
5252 6262 3C3C 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
magnet yellow \
|
|||
|
|
AAAA 0000 5555 0000 \
|
|||
|
|
AAAA 0000 5555 0000 \
|
|||
|
|
AAAA 0000 5555 0000 \
|
|||
|
|
AAAA 0000 5555 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
fence magenta \
|
|||
|
|
FFFF 0000 0000 0000 \
|
|||
|
|
0000 0000 0000 0000 \
|
|||
|
|
FFFF 0000 0000 0000 \
|
|||
|
|
0000 0000 0000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
rotate cyan \
|
|||
|
|
0000 E0E0 E0E0 E0E0 \
|
|||
|
|
0000 0000 0000 0000 \
|
|||
|
|
0000 E0E0 E0E0 E0E0 \
|
|||
|
|
0000 0000 0000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
allCut,BiCut X
|
|||
|
|
|
|||
|
|
|
|||
|
|
style versatec
|
|||
|
|
|
|||
|
|
pfet \
|
|||
|
|
07c0 0f80 1f00 3e00 \
|
|||
|
|
7c00 f800 f001 e003 \
|
|||
|
|
c007 800f 001f 003e \
|
|||
|
|
00c7 00f8 01f0 03e0
|
|||
|
|
|
|||
|
|
|
|||
|
|
nfet \
|
|||
|
|
1f00 0f80 07c0 03e0 \
|
|||
|
|
01f0 00f8 007c 003e \
|
|||
|
|
001f 800f c007 e003 \
|
|||
|
|
f001 f800 7c00 3e00
|
|||
|
|
|
|||
|
|
|
|||
|
|
m2c \
|
|||
|
|
c3c3 c3c3 0000 0000 \
|
|||
|
|
0000 0000 c3c3 c3c3 \
|
|||
|
|
c3c3 c3c3 0000 0000 \
|
|||
|
|
0000 0000 c3c3 c3c3
|
|||
|
|
|
|||
|
|
|
|||
|
|
pwell \
|
|||
|
|
2020 2020 2020 2020 \
|
|||
|
|
2020 2020 2020 2020 \
|
|||
|
|
0000 0000 0000 0000 \
|
|||
|
|
0000 0000 0000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
nwell \
|
|||
|
|
0808 0404 0202 0101 \
|
|||
|
|
0000 0000 0000 0000 \
|
|||
|
|
0808 0404 0202 0101 \
|
|||
|
|
0000 0000 0000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
allPoly \
|
|||
|
|
0808 0400 0202 0101 \
|
|||
|
|
8080 4000 2020 1010 \
|
|||
|
|
0808 0004 0202 0101 \
|
|||
|
|
8080 0040 2020 1010
|
|||
|
|
|
|||
|
|
|
|||
|
|
allMetal1 \
|
|||
|
|
8080 0000 0000 0000 \
|
|||
|
|
0808 0000 0000 0000 \
|
|||
|
|
8080 0000 0000 0000 \
|
|||
|
|
0808 0000 0000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
pad,glass \
|
|||
|
|
0000 0000 1c1c 3e3e \
|
|||
|
|
3636 3e3e 1c1c 0000 \
|
|||
|
|
0000 0000 1c1c 3e3e \
|
|||
|
|
3636 3e3e 1c1c 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
nsd,nsc,col,clc \
|
|||
|
|
0808 1414 2222 4141 \
|
|||
|
|
8080 4040 2020 1010 \
|
|||
|
|
0808 1414 2222 4141 \
|
|||
|
|
8080 4040 2020 1010
|
|||
|
|
|
|||
|
|
|
|||
|
|
allMetal2 \
|
|||
|
|
0000 1111 0000 0000 \
|
|||
|
|
0000 1111 0000 0000 \
|
|||
|
|
0000 1111 0000 0000 \
|
|||
|
|
0000 1111 0000 0000
|
|||
|
|
|
|||
|
|
|
|||
|
|
pdiff,pdc,pfet \
|
|||
|
|
0000 0808 5555 8080 \
|
|||
|
|
0000 8080 5555 0808 \
|
|||
|
|
0000 0808 5555 8080 \
|
|||
|
|
0000 8080 5555 0808
|
|||
|
|
|
|||
|
|
|
|||
|
|
psd,psc \
|
|||
|
|
1414 2222 0000 2222 \
|
|||
|
|
4141 2222 0000 2222 \
|
|||
|
|
1414 2222 0000 2222 \
|
|||
|
|
4141 2222 0000 2222
|
|||
|
|
|
|||
|
|
|
|||
|
|
ndiff,nfet,ndc \
|
|||
|
|
0808 1010 2020 4040 \
|
|||
|
|
8080 4141 2222 1414 \
|
|||
|
|
0808 1010 2020 4040 \
|
|||
|
|
8080 4141 2222 1414
|
|||
|
|
|
|||
|
|
|
|||
|
|
allPoly2 \
|
|||
|
|
0000 2020 5050 2020 \
|
|||
|
|
0000 0202 0505 0202 \
|
|||
|
|
0000 2020 5050 2020 \
|
|||
|
|
0000 0202 0505 0202
|
|||
|
|
|
|||
|
|
|
|||
|
|
allCut,BiCut X
|
|||
|
|
|
|||
|
|
/* -------------------------------------------------------------- */
|
|||
|
|
style gremlin
|
|||
|
|
pfet 9
|
|||
|
|
nfet 10
|
|||
|
|
m2c 11
|
|||
|
|
pwell 15
|
|||
|
|
nwell 16
|
|||
|
|
allPoly 19
|
|||
|
|
allMetal1 22
|
|||
|
|
pad,glass 23
|
|||
|
|
nsd,nsc 24
|
|||
|
|
allMetal2 28
|
|||
|
|
pdiff,pdc,pfet 29
|
|||
|
|
psd,psc 30
|
|||
|
|
ndiff,nfet,ndc 31
|
|||
|
|
m2c/m1,pc/m1,ndc/m1,pdc/m1,psc/m1,nsc/m1,pad/m1 X
|
|||
|
|
/* -------------------------------------------------------------- */
|
|||
|
|
style postscript
|
|||
|
|
/*
|
|||
|
|
* stipple definitions for 32x8 bitmaps
|
|||
|
|
* # row1 row2 row3 row4 row5 row6 row7 row8
|
|||
|
|
*/
|
|||
|
|
1 C0C0C0C0 C0C0C0C0 00000000 00000000 0C0C0C0C 0C0C0C0C 00000000 00000000
|
|||
|
|
2 A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A
|
|||
|
|
3 00030003 000C000C 00300030 00C000C0 03000300 0C000C00 30003000 C000C000
|
|||
|
|
4 00000000 00000000 C0C0C0C0 00000000 00000000 00000000 0C0C0C0C 00000000
|
|||
|
|
5 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
|
|||
|
|
6 07070707 0E0E0E0E 1C1C1C1C 38383838 70707070 E0E0E0E0 C1C1C1C1 83838383
|
|||
|
|
7 18181818 30303030 60606060 C0C0C0C0 81818181 03030303 06060606 0C0C0C0C
|
|||
|
|
8 18181818 0C0C0C0C 06060606 03030303 81818181 C0C0C0C0 60606060 30303030
|
|||
|
|
9 18181818 3C3C3C3C 3C3C3C3C 18181818 81818181 C3C3C3C3 C3C3C3C3 81818181
|
|||
|
|
10 F0F0F0F0 60606060 06060606 0F0F0F0F 0F0F0F0F 06060606 60606060 F0F0F0F0
|
|||
|
|
11 01000080 02000040 0C000030 F000000F 000FF000 00300C00 00400200 00800100
|
|||
|
|
12 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
|
|||
|
|
13 00000000 00000000 33333333 33333333 00000000 00000000 CCCCCCCC CCCCCCCC
|
|||
|
|
/*
|
|||
|
|
* color definitions in CMYK format
|
|||
|
|
* # C M Y K closest named color in RGB space
|
|||
|
|
*/
|
|||
|
|
1 47 95 111 0 /* RosyBrown3 */
|
|||
|
|
2 223 31 223 0 /* limegreen */
|
|||
|
|
3 0 0 0 192 /* gray25 */
|
|||
|
|
4 31 111 31 0 /* plum */
|
|||
|
|
5 31 111 255 0 /* orange2 */
|
|||
|
|
6 63 95 191 0 /* goldenrod3 */
|
|||
|
|
7 255 63 255 0 /* green3 */
|
|||
|
|
8 0 0 0 127 /* gray50 */
|
|||
|
|
9 223 47 223 0 /* limegreen */
|
|||
|
|
10 0 255 255 0 /* red */
|
|||
|
|
11 0 0 255 0 /* yellow */
|
|||
|
|
12 191 127 0 0 /* RoyalBlue1 */
|
|||
|
|
13 95 223 63 0 /* DarkOrchid3 */
|
|||
|
|
14 0 0 0 255 /* black */
|
|||
|
|
15 191 127 63 0 /* steelblue */
|
|||
|
|
16 111 151 244 0 /* goldenrod4 */
|
|||
|
|
17 23 175 183 0 /* tomato2 */
|
|||
|
|
/*
|
|||
|
|
* magic layer definitions (plotted top to bottom)
|
|||
|
|
* layer(s) color# stipple# (plus B=box, X=cross & box)
|
|||
|
|
*/
|
|||
|
|
cc,pc,ndc,pdc,psc,nsc 14 X
|
|||
|
|
m2c,pad,glass 14 B
|
|||
|
|
pad,glass 14 11
|
|||
|
|
m2c 14 13
|
|||
|
|
m2,m2c,pad 13 10
|
|||
|
|
pdc,ndc,psc,nsc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,clc,emc,pbc,nbdc,m1,m2c,gc 12 9
|
|||
|
|
cap,cc,poly2 11 7
|
|||
|
|
nsd,nsc 7 1
|
|||
|
|
psd,psc 6 1
|
|||
|
|
nfet,nffet 9 8
|
|||
|
|
pfet,wcap,pffet 1 7
|
|||
|
|
poly,pc,cap,cc 10 5
|
|||
|
|
nfet 16 5
|
|||
|
|
pfet,wcap 17 5
|
|||
|
|
pdiff,pdc,pffet 1 5
|
|||
|
|
ndiff,ndc,nffet 9 5
|
|||
|
|
pwell 1 4
|
|||
|
|
nwell 2 4
|
|||
|
|
|
|||
|
|
/* ------------------------------------------------------------------------ */
|
|||
|
|
style pnm
|
|||
|
|
draw metal1
|
|||
|
|
draw metal2
|
|||
|
|
draw polysilicon
|
|||
|
|
draw ndiffusion
|
|||
|
|
draw pdiffusion
|
|||
|
|
draw ntransistor
|
|||
|
|
draw ptransistor
|
|||
|
|
map psubstratepdiff pdiffusion
|
|||
|
|
map nsubstratendiff ndiffusion
|
|||
|
|
map polycontact polysilicon metal1
|
|||
|
|
map m2contact metal1 metal2
|
|||
|
|
map m3contact metal2 metal3
|
|||
|
|
map ndcontact ndiffusion metal1
|
|||
|
|
map pdcontact pdiffusion metal1
|
|||
|
|
map nsubstratencontact ndiffusion metal1
|
|||
|
|
map psubstratepcontact pdiffusion metal1
|
|||
|
|
|
|||
|
|
end
|