Created Enhanced Verification Base (markdown)

Enhanced-Verification-Base.md

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+# The problem
+
+Verification is a fundamental task in the chip design process. KLayout basically offers a good basis for verification as it already includes a capable layout database, a lot of algorithms for layout extraction and verification and an integrated error review environment. 
+
+Two important verification methods are addressed here:
+
+ * Design rule check (DRC)
+ * Schematic extraction plus schematic compare. Both steps form layout vs. schematic verification (LVS)
+
+KLayout supports DRC verification to some extent:
+
+ * The most important methods are provided (boolean operations, sizing, measurement, edge operations)
+ * The functionality provided seems to be sufficient in general, but has some weaknesses - e.g. in the area of width/space dependent rules. Rules involving connectivity are not available.
+ * The engine is flat meaning it does not take advantage of the hierarchical structure of a layout. All operations will be performed in the top-level cell. To mitigate memory consumption and performance issues, the area can be split into parts which are computed individually (tiling)
+
+LVS is not available. The only functionality related to connectivity extraction is the net tracer. This tool allows deriving all shapes connected to a see shape. This is a very basic form of netlist extraction. As the net tracer can be scripted it is basically possible to perform connectivity extraction net by net and finally forming a netlist. However, this approach is clumsy and not readily available. In addition, the incremental netlist extraction algorithm suffers from performance issues on very large nets (i.e. power nets).
+
+The enhanced verification base project is supposed to deal with these shortcomings. 
+
+# Basic plan
+
+The basic plan is this:
+
+ * Enhance the layout engine to support hierarchical operations. This should improve performance and allows generating device recognition shapes down in the hierarchy. This should basically enable hierarchical device extraction.
+ * Provide a "all in once" connectivity extraction tool. This tool can be based on the hierarchical algorithms prepared in the first step. A representation for the hierarchical netlist is required.
+ * Provide readers and writers for the netlist to and from external file formats (initially SPICE)
+ * Provide netlist vs. netlist compare rendering an LVS
+
+# Detailed plan for the hierarchical enhancements of the layout engine
+
+The 
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+