mirror of
https://github.com/KLayout/klayout.git
synced 2026-08-29 17:30:09 +02:00
Matthias Koefferlein
ca747771ac
same_nets, equivalent_pins, same_circuits and same_device_classes can now be given at the beginning of the LVS script. This will simplify building universal scripts with the run specific part at the beginning (one "load" section). The price are somewhat less specific error messages when something fails in these methods.
102 lines
2.8 KiB
Plaintext
102 lines
2.8 KiB
Plaintext
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source($lvs_test_source, "RINGO")
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report_lvs($lvs_test_target_lvsdb, true)
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writer = write_spice(true, false)
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target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
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schematic("ringo.cir")
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# preempt configuration
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same_device_classes("PM", "PMOS")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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thickox = input(12, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pactive_hv = pactive & thickox
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pgate_hv = pactive_hv & poly
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psd_hv = pactive_hv - pgate_hv
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pactive_lv = pactive - thickox
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pgate_lv = pactive_lv & poly
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psd_lv = pactive_lv - pgate_lv
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psd = pactive - poly
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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nactive_hv = nactive & thickox
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ngate_hv = nactive_hv & poly
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nsd_hv = nactive_hv - ngate_hv
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nactive_lv = nactive - thickox
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ngate_lv = nactive_lv & poly
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nsd_lv = nactive_lv - ngate_lv
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nsd = nactive - poly
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PM"), { "SD" => psd_lv, "G" => pgate_lv, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NM"), { "SD" => nsd_lv, "G" => ngate_lv, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# PMOS transistor device extraction (HV)
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extract_devices(mos4("PMHV"), { "SD" => psd_hv, "G" => pgate_hv, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction (HV)
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extract_devices(mos4("NMHV"), { "SD" => nsd_hv, "G" => ngate_hv, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.simplify
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same_device_classes("NM", "NMOS")
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same_device_classes("PMHV", "PMOSHV")
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same_device_classes("NMHV", "NMOSHV")
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compare
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