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https://github.com/KLayout/klayout.git
synced 2026-09-07 03:21:34 +02:00
Matthias Köfferlein
b413cb9d74
* WIP: some refactoring * WIP: some refactoring * Netlist compare: introducing ambiguity resolution by net names By default now net names are used for resolving ambiguities. If net names match, they will be used to associate nets if the choice is ambiguous. This is usually much faster and more reliable than trying to resolve ambiguities through topology analysis. This feature can be disabled using "consider_net_names(false)" in the LVS script. * Some refactoring, Jenkinsfile modified for better test coverage
133 lines
3.0 KiB
Plaintext
133 lines
3.0 KiB
Plaintext
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source($lvs_test_source)
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report_lvs($lvs_test_target_lvsdb)
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writer = write_spice(true, false)
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target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
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# needs this delegate because we use MOS3 which is not available in Spice
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class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
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# says we want to catch these subcircuits as devices
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def wants_subcircuit(name)
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name == "HVNMOS" || name == "HVPMOS"
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end
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# translate the element
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def element(circuit, el, name, model, value, nets, params)
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if el != "M"
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# all other elements are left to the standard implementation
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return super
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end
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if nets.size != 4
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error("Device #{model} needs four nodes")
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end
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# provide a device class
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cls = circuit.netlist.device_class_by_name(model)
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if ! cls
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cls = RBA::DeviceClassMOS3Transistor::new
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cls.name = model
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circuit.netlist.add(cls)
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end
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# create a device
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device = circuit.create_device(cls, name)
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# and configure the device
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[ "S", "G", "D" ].each_with_index do |t,index|
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device.connect_terminal(t, nets[index])
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end
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device.set_parameter("W", params["W"] * 1e6)
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device.set_parameter("L", params["L"] * 1e6)
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device
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end
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end
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reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
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schematic("invchain_for_cheat.cir", reader)
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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poly = input(3, 0)
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poly_lbl = input(3, 1)
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diff_cont = input(4, 0)
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poly_cont = input(5, 0)
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metal1 = input(6, 0)
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metal1_lbl = input(6, 1)
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via1 = input(7, 0)
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metal2 = input(8, 0)
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metal2_lbl = input(8, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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psd = nil
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nsd = nil
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cheat("INV") do
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate,
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"tS" => psd, "tD" => psd, "tG" => poly })
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# NMOS transistor device extraction
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extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate,
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"tS" => nsd, "tD" => nsd, "tG" => poly })
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end
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, diff_cont)
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connect(nsd, diff_cont)
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connect(poly, poly_cont)
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connect(diff_cont, metal1)
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connect(poly_cont, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# attach labels
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connect(poly, poly_lbl)
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connect(metal1, metal1_lbl)
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connect(metal2, metal2_lbl)
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# Global
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connect_global(bulk, "SUBSTRATE")
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# Compare section
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netlist.simplify
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align
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consider_net_names(false)
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compare
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