mirror of https://github.com/KLayout/klayout.git
966 lines
18 KiB
Groff
966 lines
18 KiB
Groff
#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12 '10/0')
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layer(l13 '11/0')
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layer(l7)
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l7 l7)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l2 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (450 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(l2 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$2 PMOS
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terminal(S
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rect(l2 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l6 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$1 NMOS
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terminal(S
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rect(l6 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (450 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$2 NMOS
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terminal(S
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rect(l6 (-575 -475) (450 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Circuit boundary
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rect((-100 400) (2600 7600))
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# Nets with their geometries
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net(1 name(VDD)
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rect(l8 (1110 5160) (180 180))
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rect(l8 (-180 920) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l11 (-240 -790) (300 1700))
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rect(l11 (-1350 0) (2400 800))
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rect(l11 (-1150 -400) (0 0))
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rect(l2 (-275 -2150) (425 1500))
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rect(l2 (-400 -1500) (425 1500))
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)
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net(2 name(OUT)
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rect(l8 (1810 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-1580 3760) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (1220 920) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
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rect(l11 (-110 1390) (300 1400))
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polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
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rect(l11 (-140 -500) (0 0))
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rect(l11 (-1750 1100) (300 1400))
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rect(l11 (1100 -1700) (300 300))
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rect(l11 (-300 0) (300 1400))
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rect(l2 (-1750 -1450) (425 1500))
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rect(l2 (950 -1500) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(3 name(VSS)
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rect(l8 (410 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -1300) (300 1360))
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rect(l11 (-650 -2160) (2400 800))
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rect(l11 (-1150 -400) (0 0))
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rect(l6 (-950 860) (425 950))
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)
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net(4
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rect(l3 (-100 4500) (2600 3500))
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)
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net(5 name(B)
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rect(l4 (1425 2860) (250 1940))
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rect(l4 (-345 -950) (300 300))
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rect(l4 (-205 650) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-285 1050) (180 180))
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rect(l11 (-70 -90) (0 0))
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rect(l11 (-170 -150) (300 300))
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)
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net(6 name(A)
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rect(l4 (725 2860) (250 1940))
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rect(l4 (-325 -1850) (300 300))
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rect(l4 (-225 1550) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-265 150) (180 180))
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rect(l11 (-90 -90) (0 0))
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rect(l11 (-150 -150) (300 300))
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)
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net(7 name(SUBSTRATE))
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net(8 name($I3)
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rect(l6 (975 1660) (425 950))
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rect(l6 (-400 -950) (425 950))
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)
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# Outgoing pins and their connections to nets
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pin(1 name(VDD))
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pin(2 name(OUT))
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pin(3 name(VSS))
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pin(4)
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pin(5 name(B))
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pin(6 name(A))
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pin(7 name(SUBSTRATE))
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# Devices and their connections
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device(1 D$PMOS
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location(850 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.6375)
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param(AD 0.3375)
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param(PS 3.85)
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param(PD 1.95)
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terminal(S 2)
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terminal(G 6)
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terminal(D 1)
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terminal(B 4)
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)
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device(2 D$PMOS$1
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location(1550 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.3375)
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param(AD 0.6375)
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param(PS 1.95)
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param(PD 3.85)
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terminal(S 1)
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terminal(G 5)
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terminal(D 2)
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terminal(B 4)
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)
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device(3 D$NMOS$1
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location(850 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.40375)
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param(AD 0.21375)
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param(PS 2.75)
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param(PD 1.4)
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terminal(S 3)
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terminal(G 6)
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terminal(D 8)
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terminal(B 7)
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)
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device(4 D$NMOS$2
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location(1550 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.21375)
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param(AD 0.40375)
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param(PS 1.4)
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param(PD 2.75)
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terminal(S 8)
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terminal(G 5)
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terminal(D 2)
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terminal(B 7)
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)
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)
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circuit(INVX1
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# Circuit boundary
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rect((-100 400) (2000 7600))
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# Nets with their geometries
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net(1 name(VDD)
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rect(l8 (410 6260) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l11 (-240 -240) (300 1400))
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rect(l11 (-650 300) (1800 800))
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rect(l11 (-1450 -1100) (300 300))
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rect(l11 (300 400) (0 0))
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rect(l2 (-650 -2150) (425 1500))
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)
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net(2 name(OUT)
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rect(l8 (1110 5160) (180 180))
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rect(l8 (-180 920) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -4120) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -790) (300 4790))
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rect(l11 (-150 -2500) (0 0))
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rect(l2 (-225 1050) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(3 name(VSS)
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rect(l8 (410 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -1300) (300 1360))
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rect(l11 (-650 -2160) (1800 800))
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rect(l11 (-850 -400) (0 0))
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rect(l6 (-650 860) (425 950))
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)
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net(4
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rect(l3 (-100 4500) (2000 3500))
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)
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net(5 name(IN)
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rect(l4 (725 2860) (250 1940))
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rect(l4 (-525 -1850) (300 300))
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rect(l4 (-25 1550) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-465 150) (180 180))
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rect(l11 (-90 -90) (0 0))
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rect(l11 (-150 -150) (300 300))
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)
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net(6 name(SUBSTRATE))
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# Outgoing pins and their connections to nets
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pin(1 name(VDD))
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pin(2 name(OUT))
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pin(3 name(VSS))
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pin(4)
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pin(5 name(IN))
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pin(6 name(SUBSTRATE))
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# Devices and their connections
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device(1 D$PMOS$2
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location(850 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.6375)
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param(AD 0.6375)
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param(PS 3.85)
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param(PD 3.85)
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terminal(S 1)
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terminal(G 5)
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terminal(D 2)
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terminal(B 4)
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)
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device(2 D$NMOS
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location(850 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.40375)
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param(AD 0.40375)
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param(PS 2.75)
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param(PD 2.75)
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terminal(S 3)
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terminal(G 5)
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terminal(D 2)
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terminal(B 6)
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)
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)
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circuit(RINGO
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# Circuit boundary
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rect((0 350) (27600 7650))
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# Nets with their geometries
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net(1 name($3)
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rect(l4 (26050 2800) (525 550))
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rect(l4 (-525 -300) (300 300))
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rect(l4 (-25 -2000) (250 1450))
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rect(l8 (-465 310) (180 180))
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rect(l11 (-240 -240) (300 300))
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)
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net(2 name($4)
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rect(l11 (4040 2950) (610 300))
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)
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net(3 name($5)
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rect(l11 (5550 2950) (900 300))
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)
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net(4 name($6)
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rect(l11 (7350 2950) (900 300))
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)
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net(5 name($7)
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rect(l11 (9150 2950) (900 300))
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)
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net(6 name($8)
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rect(l11 (10950 2950) (900 300))
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)
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net(7 name($9)
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rect(l11 (12750 2950) (900 300))
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)
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net(8 name($10)
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rect(l11 (14550 2950) (900 300))
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)
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net(9 name($11)
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rect(l11 (16350 2950) (900 300))
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)
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net(10 name($12)
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rect(l11 (18150 2950) (900 300))
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)
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net(11 name($13)
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rect(l11 (19950 2950) (900 300))
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)
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net(12 name(FB)
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rect(l11 (21750 2950) (900 300))
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rect(l11 (-19530 590) (320 320))
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rect(l11 (17820 -320) (320 320))
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rect(l12 (-18400 -260) (200 200))
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rect(l12 (17940 -200) (200 200))
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rect(l13 (-18040 -300) (17740 400))
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rect(l13 (-17920 -200) (0 0))
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rect(l13 (-220 -200) (400 400))
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rect(l13 (17740 -400) (400 400))
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)
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net(13 name(VDD)
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rect(l3 (500 4500) (1400 3500))
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rect(l3 (-1900 -3500) (600 3500))
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rect(l3 (23300 -3500) (1400 3500))
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rect(l3 (-100 -3500) (600 3500))
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rect(l3 (0 -3500) (600 3500))
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rect(l3 (0 -3500) (600 3500))
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rect(l3 (0 -3500) (600 3500))
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rect(l8 (-26490 -1240) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (23220 370) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l11 (-21740 860) (0 0))
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rect(l11 (-2350 -450) (1200 800))
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rect(l11 (-750 -1450) (300 1400))
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rect(l11 (-100 -350) (0 0))
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rect(l11 (-1250 -400) (600 800))
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rect(l11 (23400 -800) (1200 800))
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rect(l11 (-750 -1450) (300 1400))
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rect(l11 (-100 -350) (0 0))
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rect(l11 (550 -400) (600 800))
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rect(l11 (0 -800) (600 800))
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rect(l11 (0 -800) (600 800))
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rect(l11 (0 -800) (600 800))
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rect(l9 (-26650 -1500) (500 1500))
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rect(l9 (22900 -1500) (500 1500))
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)
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net(14 name(OUT)
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rect(l11 (23440 3840) (320 320))
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rect(l12 (-260 -260) (200 200))
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rect(l13 (-100 -100) (0 0))
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rect(l13 (-200 -200) (400 400))
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)
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net(15 name(ENABLE)
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rect(l11 (2440 2940) (320 320))
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rect(l12 (-260 -260) (200 200))
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rect(l13 (-100 -100) (0 0))
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rect(l13 (-200 -200) (400 400))
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)
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net(16 name(VSS)
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rect(l8 (26010 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (520 -730) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-25780 -890) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (23220 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (1260 -40) (300 1360))
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rect(l11 (400 -1360) (300 1360))
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rect(l11 (-24000 -1710) (0 0))
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rect(l11 (-1900 -400) (300 1400))
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rect(l11 (-750 -1450) (1200 800))
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rect(l11 (-550 -400) (0 0))
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rect(l11 (-1250 -400) (600 800))
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rect(l11 (23850 -750) (300 1400))
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rect(l11 (-750 -1450) (1200 800))
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rect(l11 (-550 -400) (0 0))
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rect(l11 (550 -400) (600 800))
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rect(l11 (0 -800) (600 800))
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rect(l11 (0 -800) (600 800))
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rect(l11 (0 -800) (600 800))
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rect(l6 (-1700 400) (425 950))
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rect(l6 (250 -950) (425 950))
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rect(l10 (-26050 -2150) (500 1500))
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rect(l10 (22900 -1500) (500 1500))
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)
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# Outgoing pins and their connections to nets
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pin(12 name(FB))
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pin(13 name(VDD))
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pin(14 name(OUT))
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pin(15 name(ENABLE))
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pin(16 name(VSS))
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# Devices and their connections
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device(1 D$NMOS
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location(26450 2075)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.40375)
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param(AD 0.40375)
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param(PS 2.75)
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param(PD 2.75)
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terminal(S 16)
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terminal(G 1)
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terminal(D 16)
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|
terminal(B 16)
|
|
)
|
|
|
|
# Subcircuits and their connections
|
|
circuit(3 ND2X1 location(1800 0)
|
|
pin(0 13)
|
|
pin(1 2)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 12)
|
|
pin(5 15)
|
|
pin(6 16)
|
|
)
|
|
circuit(4 INVX1 location(4200 0)
|
|
pin(0 13)
|
|
pin(1 3)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 2)
|
|
pin(5 16)
|
|
)
|
|
circuit(5 INVX1 location(6000 0)
|
|
pin(0 13)
|
|
pin(1 4)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 3)
|
|
pin(5 16)
|
|
)
|
|
circuit(6 INVX1 location(7800 0)
|
|
pin(0 13)
|
|
pin(1 5)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 4)
|
|
pin(5 16)
|
|
)
|
|
circuit(7 INVX1 location(9600 0)
|
|
pin(0 13)
|
|
pin(1 6)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 5)
|
|
pin(5 16)
|
|
)
|
|
circuit(8 INVX1 location(11400 0)
|
|
pin(0 13)
|
|
pin(1 7)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 6)
|
|
pin(5 16)
|
|
)
|
|
circuit(9 INVX1 location(13200 0)
|
|
pin(0 13)
|
|
pin(1 8)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 7)
|
|
pin(5 16)
|
|
)
|
|
circuit(10 INVX1 location(15000 0)
|
|
pin(0 13)
|
|
pin(1 9)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 8)
|
|
pin(5 16)
|
|
)
|
|
circuit(11 INVX1 location(16800 0)
|
|
pin(0 13)
|
|
pin(1 10)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 9)
|
|
pin(5 16)
|
|
)
|
|
circuit(12 INVX1 location(18600 0)
|
|
pin(0 13)
|
|
pin(1 11)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 10)
|
|
pin(5 16)
|
|
)
|
|
circuit(13 INVX1 location(20400 0)
|
|
pin(0 13)
|
|
pin(1 12)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 11)
|
|
pin(5 16)
|
|
)
|
|
circuit(14 INVX1 location(22200 0)
|
|
pin(0 13)
|
|
pin(1 14)
|
|
pin(2 16)
|
|
pin(3 13)
|
|
pin(4 12)
|
|
pin(5 16)
|
|
)
|
|
|
|
)
|
|
)
|
|
|
|
# Reference netlist
|
|
reference(
|
|
|
|
# Device class section
|
|
class(PMOS MOS4)
|
|
class(NMOS MOS4)
|
|
|
|
# Circuit section
|
|
# Circuits are the hierarchical building blocks of the netlist.
|
|
circuit(ND2X1
|
|
|
|
# Nets
|
|
net(1 name(VDD))
|
|
net(2 name(OUT))
|
|
net(3 name(VSS))
|
|
net(4 name(NWELL))
|
|
net(5 name(B))
|
|
net(6 name(A))
|
|
net(7 name(BULK))
|
|
net(8 name('1'))
|
|
|
|
# Outgoing pins and their connections to nets
|
|
pin(1 name(VDD))
|
|
pin(2 name(OUT))
|
|
pin(3 name(VSS))
|
|
pin(4 name(NWELL))
|
|
pin(5 name(B))
|
|
pin(6 name(A))
|
|
pin(7 name(BULK))
|
|
|
|
# Devices and their connections
|
|
device(1 PMOS
|
|
name($1)
|
|
param(L 0.25)
|
|
param(W 1.5)
|
|
param(AS 0)
|
|
param(AD 0)
|
|
param(PS 0)
|
|
param(PD 0)
|
|
terminal(S 1)
|
|
terminal(G 6)
|
|
terminal(D 2)
|
|
terminal(B 4)
|
|
)
|
|
device(2 PMOS
|
|
name($2)
|
|
param(L 0.25)
|
|
param(W 1.5)
|
|
param(AS 0)
|
|
param(AD 0)
|
|
param(PS 0)
|
|
param(PD 0)
|
|
terminal(S 2)
|
|
terminal(G 5)
|
|
terminal(D 1)
|
|
terminal(B 4)
|
|
)
|
|
device(3 NMOS
|
|
name($3)
|
|
param(L 0.25)
|
|
param(W 0.95)
|
|
param(AS 0)
|
|
param(AD 0)
|
|
param(PS 0)
|
|
param(PD 0)
|
|
terminal(S 8)
|
|
terminal(G 6)
|
|
terminal(D 3)
|
|
terminal(B 7)
|
|
)
|
|
device(4 NMOS
|
|
name($4)
|
|
param(L 0.25)
|
|
param(W 0.95)
|
|
param(AS 0)
|
|
param(AD 0)
|
|
param(PS 0)
|
|
param(PD 0)
|
|
terminal(S 2)
|
|
terminal(G 5)
|
|
terminal(D 8)
|
|
terminal(B 7)
|
|
)
|
|
|
|
)
|
|
circuit(INVX1
|
|
|
|
# Nets
|
|
net(1 name(VDD))
|
|
net(2 name(OUT))
|
|
net(3 name(VSS))
|
|
net(4 name(NWELL))
|
|
net(5 name(IN))
|
|
net(6 name(BULK))
|
|
|
|
# Outgoing pins and their connections to nets
|
|
pin(1 name(VDD))
|
|
pin(2 name(OUT))
|
|
pin(3 name(VSS))
|
|
pin(4 name(NWELL))
|
|
pin(5 name(IN))
|
|
pin(6 name(BULK))
|
|
|
|
# Devices and their connections
|
|
device(1 PMOS
|
|
name($1)
|
|
param(L 0.25)
|
|
param(W 1.5)
|
|
param(AS 0)
|
|
param(AD 0)
|
|
param(PS 0)
|
|
param(PD 0)
|
|
terminal(S 2)
|
|
terminal(G 5)
|
|
terminal(D 1)
|
|
terminal(B 4)
|
|
)
|
|
device(2 NMOS
|
|
name($2)
|
|
param(L 0.25)
|
|
param(W 0.95)
|
|
param(AS 0)
|
|
param(AD 0)
|
|
param(PS 0)
|
|
param(PD 0)
|
|
terminal(S 2)
|
|
terminal(G 5)
|
|
terminal(D 3)
|
|
terminal(B 6)
|
|
)
|
|
|
|
)
|
|
circuit(RINGO
|
|
|
|
# Nets
|
|
net(1 name(VSS))
|
|
net(2 name(VDD))
|
|
net(3 name(FB))
|
|
net(4 name(ENABLE))
|
|
net(5 name(OUT))
|
|
net(6 name('1'))
|
|
net(7 name('2'))
|
|
net(8 name('3'))
|
|
net(9 name('4'))
|
|
net(10 name('5'))
|
|
net(11 name('6'))
|
|
net(12 name('7'))
|
|
net(13 name('8'))
|
|
net(14 name('9'))
|
|
net(15 name('10'))
|
|
net(16 name(DUMMY))
|
|
|
|
# Outgoing pins and their connections to nets
|
|
pin(1 name(VSS))
|
|
pin(2 name(VDD))
|
|
pin(3 name(FB))
|
|
pin(4 name(ENABLE))
|
|
pin(5 name(OUT))
|
|
|
|
# Devices and their connections
|
|
device(1 NMOS
|
|
name($1)
|
|
param(L 0.25)
|
|
param(W 0.95)
|
|
param(AS 0)
|
|
param(AD 0)
|
|
param(PS 0)
|
|
param(PD 0)
|
|
terminal(S 1)
|
|
terminal(G 16)
|
|
terminal(D 1)
|
|
terminal(B 1)
|
|
)
|
|
|
|
# Subcircuits and their connections
|
|
circuit(1 ND2X1 name($1)
|
|
pin(0 2)
|
|
pin(1 6)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 3)
|
|
pin(5 4)
|
|
pin(6 1)
|
|
)
|
|
circuit(2 INVX1 name($2)
|
|
pin(0 2)
|
|
pin(1 7)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 6)
|
|
pin(5 1)
|
|
)
|
|
circuit(3 INVX1 name($3)
|
|
pin(0 2)
|
|
pin(1 8)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 7)
|
|
pin(5 1)
|
|
)
|
|
circuit(4 INVX1 name($4)
|
|
pin(0 2)
|
|
pin(1 9)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 8)
|
|
pin(5 1)
|
|
)
|
|
circuit(5 INVX1 name($5)
|
|
pin(0 2)
|
|
pin(1 10)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 9)
|
|
pin(5 1)
|
|
)
|
|
circuit(6 INVX1 name($6)
|
|
pin(0 2)
|
|
pin(1 11)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 10)
|
|
pin(5 1)
|
|
)
|
|
circuit(7 INVX1 name($7)
|
|
pin(0 2)
|
|
pin(1 12)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 11)
|
|
pin(5 1)
|
|
)
|
|
circuit(8 INVX1 name($8)
|
|
pin(0 2)
|
|
pin(1 13)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 12)
|
|
pin(5 1)
|
|
)
|
|
circuit(9 INVX1 name($9)
|
|
pin(0 2)
|
|
pin(1 14)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 13)
|
|
pin(5 1)
|
|
)
|
|
circuit(10 INVX1 name($10)
|
|
pin(0 2)
|
|
pin(1 15)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 14)
|
|
pin(5 1)
|
|
)
|
|
circuit(11 INVX1 name($11)
|
|
pin(0 2)
|
|
pin(1 3)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 15)
|
|
pin(5 1)
|
|
)
|
|
circuit(12 INVX1 name($12)
|
|
pin(0 2)
|
|
pin(1 5)
|
|
pin(2 1)
|
|
pin(3 2)
|
|
pin(4 3)
|
|
pin(5 1)
|
|
)
|
|
|
|
)
|
|
)
|
|
|
|
# Cross reference
|
|
xref(
|
|
circuit(INVX1 INVX1 match
|
|
xref(
|
|
net(4 4 match)
|
|
net(5 5 match)
|
|
net(2 2 match)
|
|
net(6 6 match)
|
|
net(1 1 match)
|
|
net(3 3 match)
|
|
pin(3 3 match)
|
|
pin(4 4 match)
|
|
pin(1 1 match)
|
|
pin(5 5 match)
|
|
pin(0 0 match)
|
|
pin(2 2 match)
|
|
device(2 2 match)
|
|
device(1 1 match)
|
|
)
|
|
)
|
|
circuit(ND2X1 ND2X1 match
|
|
xref(
|
|
net(8 8 match)
|
|
net(4 4 match)
|
|
net(6 6 match)
|
|
net(5 5 match)
|
|
net(2 2 match)
|
|
net(7 7 match)
|
|
net(1 1 match)
|
|
net(3 3 match)
|
|
pin(3 3 match)
|
|
pin(5 5 match)
|
|
pin(4 4 match)
|
|
pin(1 1 match)
|
|
pin(6 6 match)
|
|
pin(0 0 match)
|
|
pin(2 2 match)
|
|
device(3 3 match)
|
|
device(4 4 match)
|
|
device(1 1 match)
|
|
device(2 2 match)
|
|
)
|
|
)
|
|
circuit(RINGO RINGO match
|
|
xref(
|
|
net(2 6 match)
|
|
net(11 15 match)
|
|
net(3 7 match)
|
|
net(4 8 match)
|
|
net(5 9 match)
|
|
net(6 10 match)
|
|
net(7 11 match)
|
|
net(8 12 match)
|
|
net(9 13 match)
|
|
net(10 14 match)
|
|
net(1 16 match)
|
|
net(15 4 match)
|
|
net(12 3 match)
|
|
net(14 5 match)
|
|
net(13 2 match)
|
|
net(16 1 match)
|
|
pin(3 3 match)
|
|
pin(0 2 match)
|
|
pin(2 4 match)
|
|
pin(1 1 match)
|
|
pin(4 0 match)
|
|
device(1 1 match)
|
|
circuit(4 2 match)
|
|
circuit(5 3 match)
|
|
circuit(6 4 match)
|
|
circuit(7 5 match)
|
|
circuit(8 6 match)
|
|
circuit(9 7 match)
|
|
circuit(10 8 match)
|
|
circuit(11 9 match)
|
|
circuit(12 10 match)
|
|
circuit(13 11 match)
|
|
circuit(14 12 match)
|
|
circuit(3 1 match)
|
|
)
|
|
)
|
|
)
|