mirror of
https://github.com/KLayout/klayout.git
synced 2026-09-01 10:27:53 +02:00
Matthias Koefferlein
9630bff240
With this patch, empty layers can be used to place device terminals on and these shapes are visible on those layers. This allows splitting the terminal shapes and used those shapes to connect down to different substrates. The patch turns EmptyLayer into a DeepLayer when used as terminal layer for device extraction.
108 lines
2.6 KiB
Plaintext
108 lines
2.6 KiB
Plaintext
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$lvs_test_source && source($lvs_test_source)
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if $lvs_test_target_l2n
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report_netlist($lvs_test_target_l2n)
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else
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report_netlist
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end
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writer = write_spice(true, false)
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$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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nplus = input(2, 1)
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pplus = input(2, 2)
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poly = input(3, 0)
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poly_lbl = input(3, 1)
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diff_cont = input(4, 0)
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poly_cont = input(5, 0)
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metal1 = input(6, 0)
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metal1_lbl = input(6, 1)
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via1 = input(7, 0)
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metal2 = input(8, 0)
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metal2_lbl = input(8, 1)
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iosub = input(10, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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psd = nil
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nsd = nil
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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ntie = active_in_nwell & nplus
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ptie = active_outside_nwell & pplus
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly })
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# Define connectivity for netlist extraction
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# Inter-layer
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soft_connect(diff_cont, psd)
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soft_connect(diff_cont, nsd)
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soft_connect(diff_cont, ptie)
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soft_connect(diff_cont, ntie)
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soft_connect(ntie, nwell)
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soft_connect(poly_cont, poly)
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connect(diff_cont, metal1)
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connect(poly_cont, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# attach labels
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connect(poly, poly_lbl)
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connect(metal1, metal1_lbl)
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connect(metal2, metal2_lbl)
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# Split bulk and ptie into inside and outside iosub
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(bulk_io, bulk_reg) = bulk.andnot(iosub)
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(ptie_io, ptie_reg) = ptie.andnot(iosub)
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# connect outside to "SUBSTRATE" globally
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connect(bulk, bulk_reg)
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connect(ptie, ptie_reg)
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connect_global(bulk_reg, "SUBSTRATE")
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soft_connect_global(ptie_reg, "SUBSTRATE")
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# connect inside to "IOSUB" via polygons
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connect(bulk, bulk_io)
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connect(ptie, ptie_io)
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connect(bulk_io, iosub)
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soft_connect(ptie_io, iosub)
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connect_global(iosub, "IOSUB")
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# Netlist section (NOTE: we only check log here)
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# for debugging: _make_soft_connection_diodes(true)
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netlist
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netlist.simplify
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