mirror of https://github.com/KLayout/klayout.git
555 lines
9.6 KiB
Plaintext
555 lines
9.6 KiB
Plaintext
#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12 '10/0')
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layer(l13 '11/0')
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layer(l7 '13/0')
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l7 l7)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Circuit boundary
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rect((-100 249) (2600 7751))
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# Outgoing pins and their connections to nets
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin()
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pin(name(B))
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pin(name(A))
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pin(name(BULK))
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)
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circuit(INVX1
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# Circuit boundary
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rect((-100 249) (2000 7751))
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# Outgoing pins and their connections to nets
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin()
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pin(name(IN))
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pin(name(BULK))
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)
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circuit(INVX2
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# Circuit boundary
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rect((-100 249) (2600 7751))
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# Outgoing pins and their connections to nets
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pin(name(IN))
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin()
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pin(name(BULK))
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)
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circuit(RINGO
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# Circuit boundary
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rect((600 249) (25800 7751))
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# Nets with their geometries
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net(1
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rect(l8 (4710 3010) (180 180))
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rect(l11 (-850 -240) (610 300))
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)
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net(2
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rect(l8 (6510 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(3
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rect(l8 (19110 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(4
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rect(l8 (20910 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(5 name(FB)
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rect(l8 (22710 3010) (180 180))
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rect(l8 (-19700 720) (180 180))
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rect(l11 (18380 -1140) (900 300))
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rect(l11 (-19530 590) (320 320))
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rect(l11 (17820 -320) (320 320))
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rect(l12 (-18400 -260) (200 200))
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rect(l12 (17940 -200) (200 200))
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rect(l13 (-18040 -300) (17740 400))
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rect(l13 (-17921 -201) (2 2))
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rect(l13 (-221 -201) (400 400))
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rect(l13 (17740 -400) (400 400))
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)
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net(6 name(VDD)
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rect(l3 (1100 4500) (1400 3500))
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rect(l3 (-1900 -3500) (600 3500))
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rect(l3 (23300 -3500) (1400 3500))
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rect(l3 (-100 -3500) (600 3500))
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rect(l8 (-24690 -1240) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (23220 370) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l11 (-22341 859) (2 2))
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rect(l11 (-1751 -451) (1200 800))
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rect(l11 (-750 -1450) (300 1400))
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rect(l11 (-101 -351) (2 2))
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rect(l11 (-1251 -401) (600 800))
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rect(l11 (23400 -800) (1200 800))
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rect(l11 (-750 -1450) (300 1400))
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rect(l11 (-101 -351) (2 2))
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rect(l11 (549 -401) (600 800))
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rect(l9 (-24850 -1500) (500 1500))
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rect(l9 (22900 -1500) (500 1500))
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)
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net(7 name(OUT)
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rect(l11 (23440 3840) (320 320))
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rect(l12 (-260 -260) (200 200))
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rect(l13 (-101 -101) (2 2))
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rect(l13 (-201 -201) (400 400))
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)
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net(8 name(ENABLE)
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rect(l8 (2510 3010) (180 180))
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rect(l11 (-250 -250) (320 320))
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rect(l12 (-260 -260) (200 200))
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rect(l13 (-101 -101) (2 2))
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rect(l13 (-201 -201) (400 400))
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)
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net(9 name(VSS)
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rect(l8 (1710 1610) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (23220 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-22341 -391) (2 2))
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rect(l11 (-1301 -401) (300 1400))
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rect(l11 (-750 -1450) (1200 800))
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rect(l11 (-551 -401) (2 2))
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rect(l11 (-1251 -401) (600 800))
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rect(l11 (23850 -750) (300 1400))
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rect(l11 (-750 -1450) (1200 800))
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rect(l11 (-551 -401) (2 2))
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rect(l11 (549 -401) (600 800))
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rect(l10 (-24850 -800) (500 1500))
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rect(l10 (22900 -1500) (500 1500))
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)
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net(10
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rect(l8 (8310 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(11
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rect(l8 (17310 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(12
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rect(l8 (10110 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(13
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rect(l8 (11910 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(14
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rect(l8 (13710 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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net(15
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rect(l8 (15510 3010) (180 180))
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rect(l11 (-1140 -240) (900 300))
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)
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# Outgoing pins and their connections to nets
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pin(5 name(FB))
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pin(6 name(VDD))
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pin(7 name(OUT))
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pin(8 name(ENABLE))
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pin(9 name(VSS))
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# Subcircuits and their connections
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circuit(1 ND2X1 location(1800 0)
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pin(0 6)
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pin(1 1)
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pin(2 9)
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pin(3 6)
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pin(4 5)
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pin(5 8)
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pin(6 9)
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)
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circuit(2 INVX1 location(4200 0)
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pin(0 6)
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pin(1 2)
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pin(2 9)
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pin(3 6)
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pin(4 1)
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pin(5 9)
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)
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circuit(3 INVX1 location(6000 0)
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pin(0 6)
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pin(1 10)
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pin(2 9)
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pin(3 6)
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pin(4 2)
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pin(5 9)
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)
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circuit(4 INVX1 location(16800 0)
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pin(0 6)
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pin(1 3)
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pin(2 9)
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pin(3 6)
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pin(4 11)
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pin(5 9)
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)
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circuit(5 INVX1 location(18600 0)
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pin(0 6)
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pin(1 4)
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pin(2 9)
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pin(3 6)
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pin(4 3)
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pin(5 9)
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)
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circuit(6 INVX1 location(20400 0)
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pin(0 6)
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pin(1 5)
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pin(2 9)
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pin(3 6)
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pin(4 4)
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pin(5 9)
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)
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circuit(7 INVX2 location(22200 0)
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pin(0 5)
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pin(1 6)
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pin(2 7)
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pin(3 9)
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pin(4 6)
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pin(5 9)
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)
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circuit(17 INVX1 location(7800 0)
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pin(0 6)
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pin(1 12)
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pin(2 9)
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pin(3 6)
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pin(4 10)
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pin(5 9)
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)
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circuit(18 INVX1 location(9600 0)
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pin(0 6)
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pin(1 13)
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pin(2 9)
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pin(3 6)
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pin(4 12)
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pin(5 9)
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)
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circuit(19 INVX1 location(11400 0)
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pin(0 6)
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pin(1 14)
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pin(2 9)
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pin(3 6)
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pin(4 13)
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pin(5 9)
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)
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circuit(20 INVX1 location(13200 0)
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pin(0 6)
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pin(1 15)
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pin(2 9)
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pin(3 6)
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pin(4 14)
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pin(5 9)
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)
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circuit(21 INVX1 location(15000 0)
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pin(0 6)
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pin(1 11)
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pin(2 9)
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pin(3 6)
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pin(4 15)
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pin(5 9)
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)
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)
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)
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# Reference netlist
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reference(
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Outgoing pins and their connections to nets
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin(name(NWELL))
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pin(name(B))
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pin(name(A))
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pin(name(BULK))
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)
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circuit(INVX1
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# Outgoing pins and their connections to nets
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin(name(NWELL))
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pin(name(IN))
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pin(name(BULK))
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)
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circuit(INVX2
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# Outgoing pins and their connections to nets
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin(name(NWELL))
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pin(name(IN))
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pin(name(BULK))
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)
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circuit(RINGO
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# Nets
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net(1 name(VSS))
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net(2 name(VDD))
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net(3 name(FB))
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net(4 name(ENABLE))
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net(5 name(OUT))
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net(6 name('1'))
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net(7 name('2'))
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net(8 name('3'))
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net(9 name('4'))
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net(10 name('5'))
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net(11 name('6'))
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net(12 name('7'))
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net(13 name('8'))
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net(14 name('9'))
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net(15 name('10'))
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# Outgoing pins and their connections to nets
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pin(1 name(VSS))
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pin(2 name(VDD))
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pin(3 name(FB))
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pin(4 name(ENABLE))
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pin(5 name(OUT))
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# Subcircuits and their connections
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circuit(1 ND2X1 name($1)
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pin(0 2)
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pin(1 6)
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pin(2 1)
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pin(3 2)
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pin(4 3)
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pin(5 4)
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pin(6 1)
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)
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circuit(2 INVX1 name($2)
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pin(0 2)
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pin(1 7)
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pin(2 1)
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pin(3 2)
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pin(4 6)
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pin(5 1)
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)
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circuit(3 INVX1 name($3)
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pin(0 2)
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pin(1 8)
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pin(2 1)
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pin(3 2)
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pin(4 7)
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pin(5 1)
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)
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circuit(4 INVX1 name($4)
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pin(0 2)
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pin(1 9)
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pin(2 1)
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pin(3 2)
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pin(4 8)
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pin(5 1)
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)
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circuit(5 INVX1 name($5)
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pin(0 2)
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pin(1 10)
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pin(2 1)
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pin(3 2)
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pin(4 9)
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pin(5 1)
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)
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circuit(6 INVX1 name($6)
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pin(0 2)
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pin(1 11)
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pin(2 1)
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pin(3 2)
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pin(4 10)
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pin(5 1)
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)
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circuit(7 INVX1 name($7)
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pin(0 2)
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pin(1 12)
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pin(2 1)
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pin(3 2)
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pin(4 11)
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pin(5 1)
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)
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circuit(8 INVX1 name($8)
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pin(0 2)
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pin(1 13)
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pin(2 1)
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pin(3 2)
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pin(4 12)
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pin(5 1)
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)
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circuit(9 INVX1 name($9)
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pin(0 2)
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pin(1 14)
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pin(2 1)
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pin(3 2)
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pin(4 13)
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pin(5 1)
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)
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circuit(10 INVX1 name($10)
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pin(0 2)
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pin(1 15)
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pin(2 1)
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pin(3 2)
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pin(4 14)
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pin(5 1)
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)
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circuit(11 INVX1 name($11)
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pin(0 2)
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pin(1 3)
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pin(2 1)
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pin(3 2)
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pin(4 15)
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pin(5 1)
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)
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circuit(12 INVX2 name($12)
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pin(0 2)
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pin(1 5)
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pin(2 1)
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pin(3 2)
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pin(4 3)
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pin(5 1)
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)
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)
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)
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# Cross reference
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xref(
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circuit(INVX1 INVX1 match
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xref(
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pin(3 3 match)
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pin(5 5 match)
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pin(4 4 match)
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pin(1 1 match)
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pin(0 0 match)
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pin(2 2 match)
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)
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)
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circuit(INVX2 INVX2 match
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xref(
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pin(4 3 match)
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pin(5 5 match)
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pin(0 4 match)
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pin(2 1 match)
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pin(1 0 match)
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pin(3 2 match)
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)
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)
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circuit(ND2X1 ND2X1 match
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xref(
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pin(3 3 match)
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pin(5 5 match)
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pin(4 4 match)
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pin(6 6 match)
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pin(1 1 match)
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pin(0 0 match)
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pin(2 2 match)
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)
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)
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circuit(RINGO RINGO match
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xref(
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net(1 6 match)
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net(4 15 match)
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net(2 7 match)
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net(10 8 match)
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net(12 9 match)
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net(13 10 match)
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net(14 11 match)
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net(15 12 match)
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net(11 13 match)
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net(3 14 match)
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net(8 4 match)
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net(5 3 match)
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net(7 5 match)
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net(6 1 warning)
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net(9 2 warning)
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pin(3 3 match)
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pin(0 2 match)
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pin(2 4 match)
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pin(1 0 match)
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pin(4 1 match)
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circuit(2 2 match)
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circuit(3 3 match)
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circuit(17 4 match)
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circuit(18 5 match)
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circuit(19 6 match)
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circuit(20 7 match)
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circuit(21 8 match)
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circuit(4 9 match)
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circuit(5 10 match)
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circuit(6 11 match)
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circuit(7 12 match)
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circuit(1 1 match)
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)
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)
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)
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