mirror of
https://github.com/KLayout/klayout.git
synced 2026-08-31 10:06:28 +02:00
Matthias Koefferlein
2b447854f9
Previously: matching of blackbox pins was enforced by using pin names for passive nets in the compare. Problem: no match was achieved when pins are not named or not named consistently. In this case, it's desirable to treat them as ambiguous. The new solution is to let the ambiguity resolver handle that using an extended definition of the net names: it will take the pin name into account if an unnamed net is attached to a pin. In addition, net ambiguities are projected to pin equivalence now. This also will propagate symmetry through nested blocks (dbNetlistCompareTests:20_BusLikeConnections).
131 lines
2.8 KiB
Plaintext
131 lines
2.8 KiB
Plaintext
* RINGO netlist before simplification
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* cell RINGO
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.SUBCKT RINGO
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* net 11 FB
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* net 12 VDD
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* net 15 OUT
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* net 16 ENABLE
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* net 19 BULK,VSS
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* cell instance $1 r0 *1 1.8,0
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X$1 12 1 19 12 11 16 19 ND2X1
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* cell instance $2 r0 *1 4.2,0
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X$2 12 2 19 12 1 19 INVX1
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* cell instance $3 r0 *1 6,0
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X$3 12 3 19 12 2 19 INVX1
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* cell instance $4 r0 *1 7.8,0
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X$4 12 4 19 12 3 19 INVX1
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* cell instance $5 r0 *1 9.6,0
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X$5 12 5 19 12 4 19 INVX1
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* cell instance $6 r0 *1 11.4,0
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X$6 12 6 19 12 5 19 INVX1
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* cell instance $7 r0 *1 13.2,0
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X$7 12 7 19 12 6 19 INVX1
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* cell instance $8 r0 *1 15,0
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X$8 12 8 19 12 7 19 INVX1
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* cell instance $9 r0 *1 16.8,0
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X$9 12 9 19 12 8 19 INVX1
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* cell instance $10 r0 *1 18.6,0
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X$10 12 10 19 12 9 19 INVX1
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* cell instance $11 r0 *1 20.4,0
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X$11 12 11 19 12 10 19 INVX1
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* cell instance $12 r0 *1 22.2,0
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X$12 12 15 19 12 11 19 INVX1
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* cell instance $13 r0 *1 3.28,4
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X$13 11 M1M2
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* cell instance $14 r0 *1 21.42,4
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X$14 11 M1M2
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* cell instance $15 r0 *1 0.6,0
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X$15 12 19 TIE
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* cell instance $16 r0 *1 0,0
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X$16 12 19 12 EMPTY
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* cell instance $17 r0 *1 24,0
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X$17 12 19 TIE
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* cell instance $18 r0 *1 25.2,0
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X$18 12 19 12 EMPTY
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* cell instance $19 r0 *1 23.6,4
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X$19 15 M1M2
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* cell instance $20 r0 *1 2.6,3.1
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X$20 16 M1M2
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.ENDS RINGO
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* cell ND2X1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin B
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* pin A
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* pin BULK
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.SUBCKT ND2X1 1 2 3 4 5 6 9
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* net 1 VDD
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* net 2 OUT
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* net 3 VSS
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* net 5 B
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* net 6 A
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* net 9 BULK
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* cell instance $1 r0 *1 0.3,5.05
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X$1 6 1 2 PMOS3
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* cell instance $2 r0 *1 1,5.05
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X$2 5 2 1 PMOS3
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* cell instance $3 r0 *1 1,1.66
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X$3 5 2 10 NMOS2
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* cell instance $4 r0 *1 0.3,1.66
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X$4 6 10 3 NMOS2
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* cell instance $5 r0 *1 1.48,4
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X$5 5 POLYM1
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* cell instance $6 r0 *1 0.8,3.1
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X$6 6 POLYM1
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* device instance $1 0.85,5.8 LVPMOS
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M$1 2 6 1 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
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* device instance $2 1.55,5.8 LVPMOS
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M$2 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
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* device instance $3 0.85,2.135 LVNMOS
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M$3 3 6 10 9 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
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* device instance $4 1.55,2.135 LVNMOS
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M$4 10 5 2 9 LVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
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.ENDS ND2X1
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* cell INVX1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin IN
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* pin BULK
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.SUBCKT INVX1 1 2 3 4 5 7
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* net 1 VDD
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* net 2 OUT
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* net 3 VSS
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* net 5 IN
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* net 7 BULK
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* cell instance $1 r0 *1 0.3,5.05
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X$1 5 1 2 PMOS3
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* cell instance $2 r0 *1 0.3,1.66
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X$2 5 2 3 NMOS2
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* cell instance $3 r0 *1 0.6,3.1
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X$3 5 POLYM1
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* device instance $1 0.85,5.8 LVPMOS
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M$1 1 5 2 4 LVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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* device instance $2 0.85,2.135 LVNMOS
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M$2 3 5 2 7 LVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
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.ENDS INVX1
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.SUBCKT M1M2 $1
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.ENDS M1M2
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.SUBCKT TIE $1 $2
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.ENDS TIE
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.SUBCKT EMPTY $1 $2 $3
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.ENDS EMPTY
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.SUBCKT POLYM1 $1
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.ENDS POLYM1
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.SUBCKT NMOS2 $1 $2 $3
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.ENDS NMOS2
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.SUBCKT PMOS3 $1 $2 $3
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.ENDS PMOS3
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