mirror of https://github.com/KLayout/klayout.git
37 lines
794 B
Plaintext
37 lines
794 B
Plaintext
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source($lvs_test_source)
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("resistor.cir")
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deep
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contact = input(15, 0)
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metal1 = input(16, 0)
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metal1_ver = input(16, 5)
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metal1_lbl = labels(16, 3)
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res = metal1 & metal1_ver
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metal1_not_res = metal1 - metal1_ver
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dc = extract_devices(resistor("RR1", 1), { "R" => res , "C" => metal1_not_res})
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dc.enable_parameter("W", true)
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dc.enable_parameter("L", true)
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sp = dc.spice_profile("")
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sp.outgoing_parameters = {
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"R" => "", # drop
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"W" => "W",
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"L" => "L",
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"$" => "R" # direct value
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}
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dc.set_spice_profile("", sp)
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connect(contact, metal1_not_res)
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connect(metal1_not_res, metal1_lbl)
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align
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netlist.make_top_level_pins(false)
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netlist.simplify
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compare
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