mirror of https://github.com/KLayout/klayout.git
112 lines
2.5 KiB
Plaintext
112 lines
2.5 KiB
Plaintext
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source($lvs_test_source)
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# will get pretty big:
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# report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice(true), "Extracted by KLayout")
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schematic("vexriscv_schematic.cir.gz")
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deep
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# Drawing layers
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nwell = input(1, 0)
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pactive = input(4, 0)
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nactive = input(3, 0)
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ntie = input(5, 0)
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ptie = input(6, 0)
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poly = input(7, 0)
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cont = input(10, 0)
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metal1 = input(11, 0)
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via1 = input(14, 0)
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metal2 = input(16, 0)
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via2 = input(18, 0)
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metal3 = input(19, 0)
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via3 = input(21, 0)
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metal4 = input(22, 0)
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via4 = input(25, 0)
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metal5 = input(26, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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poly_cont = cont & poly
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diff_cont = cont - poly
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pgate = pactive & poly
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psd = pactive - pgate
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, diff_cont)
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connect(nsd, diff_cont)
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connect(poly, poly_cont)
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connect(poly_cont, metal1)
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connect(diff_cont, metal1)
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connect(diff_cont, ntie)
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connect(diff_cont, ptie)
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connect(nwell, ntie)
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connect(metal1, via1)
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connect(via1, metal2)
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connect(metal2, via2)
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connect(via2, metal3)
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connect(metal3, via3)
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connect(via3, metal4)
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connect(metal4, via4)
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connect(via4, metal5)
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# Global
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connect_global(ptie, "BULK")
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connect_global(bulk, "BULK")
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# Implicit
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connect_implicit("VDD")
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connect_implicit("VSS")
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# Compare section
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same_device_classes("PMOS", "TP")
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same_device_classes("NMOS", "TN")
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# Ignore all caps from the schematic
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same_device_classes(nil, "CAP")
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# Increase the default complexity from 100 to 200
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# This is required because the clock tree is incorrect and exhibits manifold ambiguities
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# (the netlists are just samples, not necessarily functional).
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# The algorithm needs enough freedom to follow all these branches and different variants.
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max_branch_complexity(200)
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schematic.combine_devices
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netlist.combine_devices
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align
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if ! compare
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raise "Netlists don't match"
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else
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puts "Congratulations! Netlists match."
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end
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