mirror of https://github.com/KLayout/klayout.git
127 lines
3.1 KiB
Plaintext
127 lines
3.1 KiB
Plaintext
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source($lvs_test_source, "RINGO")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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# Provide a special reader
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class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate
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# says we want to catch these subcircuits as devices
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def wants_subcircuit(name)
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name == "NMOS" || name == "XPMOS"
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end
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# translate the element
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def element(circuit, el, name, model, value, nets, params)
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if el != "X"
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# all other elements are left to the standard implementation
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return super
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end
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if nets.size != 4
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error("Subcircuit #{model} needs four nodes")
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end
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# provide a device class
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cls = circuit.netlist.device_class_by_name(model)
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if ! cls
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cls = RBA::DeviceClassMOS4Transistor::new
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cls.name = model
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circuit.netlist.add(cls)
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end
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# create a device
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device = circuit.create_device(cls, name)
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# and configure the device
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[ "S", "G", "D", "B" ].each_with_index do |t,index|
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device.connect_terminal(t, nets[index])
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end
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# parameters in the model are given in micrometer units, so
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# we need to translate the parameter values from SI to um values:
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device.set_parameter("W", (params["W"] || 0.0) * 1e6)
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device.set_parameter("L", (params["L"] || 0.0) * 1e6)
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return true
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end
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end
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schematic("ringo_xdevice.cir", RBA::NetlistSpiceReader::new(SubcircuitModelsReader::new))
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Test same_device_classes
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same_device_classes("PMOS", $change_case ? "xpMos" : "XPMOS")
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# Compare section
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netlist.simplify
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compare
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