klayout/testdata/lvs/nand2_split_gate_early.cir.2

24 lines
647 B
Groff

* Extracted by KLayout
* cell NAND2_WITH_DIODES
* pin B
* pin A
* pin OUT
* pin VDD
* pin VSS
.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
* net 1 B
* net 2 A
* net 4 OUT
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,0.65 NMOS
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,0.65 NMOS
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES