mirror of https://github.com/KLayout/klayout.git
435 lines
8.0 KiB
Plaintext
435 lines
8.0 KiB
Plaintext
#%lvsdb-klayout
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# Layout
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layout(
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top(TOP)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(nwell '1/0')
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layer(poly '5/0')
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layer(contact '8/0')
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layer(metal1 '9/0')
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layer(via1)
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layer(metal2)
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layer(bulk)
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layer(psd)
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layer(ntie)
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layer(nsd)
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layer(l1)
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# Mask layer connectivity
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connect(nwell nwell ntie)
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connect(poly poly contact)
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connect(contact poly contact metal1 psd ntie nsd l1)
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connect(metal1 contact metal1 via1)
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connect(via1 metal1 via1 metal2)
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connect(metal2 via1 metal2)
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connect(bulk bulk)
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connect(psd contact psd)
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connect(ntie nwell contact ntie)
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connect(nsd contact nsd)
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connect(l1 contact l1)
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# Global nets and connectivity
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global(bulk SUBSTRATE)
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global(l1 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(psd (-550 -750) (425 1500))
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)
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terminal(G
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rect(poly (-125 -750) (250 1500))
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)
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terminal(D
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rect(psd (125 -750) (425 1500))
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)
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terminal(B
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rect(nwell (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(nsd (-550 -475) (425 950))
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)
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terminal(G
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rect(poly (-125 -475) (250 950))
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)
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terminal(D
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rect(nsd (125 -475) (425 950))
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)
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terminal(B
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rect(bulk (-125 -475) (250 950))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INVX1
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# Circuit boundary
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rect((-100 400) (2000 7600))
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# Nets with their geometries
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net(1 name(OUT)
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rect(contact (1110 5160) (180 180))
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rect(contact (-180 920) (180 180))
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rect(contact (-180 -730) (180 180))
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rect(contact (-180 -4120) (180 180))
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rect(contact (-180 370) (180 180))
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rect(metal1 (-240 -790) (300 4790))
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rect(metal1 (-150 -2500) (0 0))
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rect(psd (-225 1050) (425 1500))
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rect(nsd (-425 -4890) (425 950))
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)
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net(2 name(VDD)
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rect(nwell (-100 4500) (2000 3500))
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rect(contact (-1090 -890) (180 180))
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rect(contact (-580 -1030) (180 180))
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rect(contact (-180 -730) (180 180))
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rect(contact (-180 -730) (180 180))
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rect(metal1 (-590 1460) (1800 800))
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rect(metal1 (-1050 -550) (300 300))
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rect(metal1 (-700 -850) (300 300))
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rect(metal1 (300 500) (0 0))
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rect(metal1 (-600 -2200) (300 1400))
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rect(psd (-350 -1450) (425 1500))
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rect(ntie (-75 450) (500 500))
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)
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net(3 name(IN)
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rect(poly (725 2860) (250 1940))
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rect(poly (-525 -1850) (300 300))
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rect(poly (-25 -1840) (250 1450))
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rect(poly (-250 1940) (250 2000))
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rect(poly (-250 -2000) (250 2000))
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rect(contact (-465 -3790) (180 180))
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rect(metal1 (-90 -90) (0 0))
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rect(metal1 (-150 -150) (300 300))
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)
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net(4 name(VSS)
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rect(contact (810 710) (180 180))
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rect(contact (-580 880) (180 180))
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rect(contact (-180 370) (180 180))
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rect(metal1 (-590 -2100) (1800 800))
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rect(metal1 (-1050 -550) (300 300))
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rect(metal1 (-100 -150) (0 0))
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rect(metal1 (-600 400) (300 1360))
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rect(nsd (-350 -900) (425 950))
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rect(l1 (-75 -2010) (500 400))
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)
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# Outgoing pins and their connections to nets
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pin(1 name(OUT))
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pin(2 name(VDD))
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pin(3 name(IN))
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pin(4 name(VSS))
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# Devices and their connections
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device(1 D$PMOS
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location(850 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.6375)
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param(AD 0.6375)
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param(PS 3.85)
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param(PD 3.85)
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terminal(S 2)
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terminal(G 3)
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terminal(D 1)
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terminal(B 2)
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)
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device(2 D$NMOS
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location(850 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.40375)
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param(AD 0.40375)
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param(PS 2.75)
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param(PD 2.75)
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terminal(S 4)
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terminal(G 3)
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terminal(D 1)
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terminal(B 4)
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)
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)
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circuit(DINV
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# Circuit boundary
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rect((-100 400) (3800 7600))
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# Nets with their geometries
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net(1 name('A<1>')
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rect(metal1 (600 3100) (0 0))
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)
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net(2 name('A<2>')
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rect(metal1 (2400 3100) (0 0))
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)
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net(3 name('B<2>')
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rect(metal1 (3000 4000) (0 0))
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)
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net(4 name('B<1>')
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rect(metal1 (1200 4000) (0 0))
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)
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net(5 name(VDD)
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rect(metal1 (1800 7200) (0 0))
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)
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net(6 name(VSS)
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rect(metal1 (1800 800) (0 0))
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)
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# Outgoing pins and their connections to nets
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pin(1 name('A<1>'))
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pin(2 name('A<2>'))
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pin(3 name('B<2>'))
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pin(5 name(VDD))
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pin(6 name(VSS))
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# Subcircuits and their connections
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circuit(1 INVX1 location(0 0)
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pin(0 4)
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pin(1 5)
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pin(2 1)
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pin(3 6)
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)
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circuit(2 INVX1 location(1800 0)
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pin(0 3)
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pin(1 5)
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pin(2 2)
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pin(3 6)
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)
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)
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circuit(TOP
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# Circuit boundary
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rect((-100 400) (5600 7600))
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# Nets with their geometries
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net(1
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rect(metal1 (3100 2950) (950 300))
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)
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net(2 name(A)
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rect(metal1 (600 3100) (0 0))
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)
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net(3 name(C)
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rect(metal1 (2400 3100) (0 0))
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)
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net(4 name(SUBSTRATE))
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net(5)
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net(6)
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# Outgoing pins and their connections to nets
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pin(2 name(A))
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pin(3 name(C))
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pin(4 name(SUBSTRATE))
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# Subcircuits and their connections
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circuit(1 DINV location(0 0)
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pin(0 2)
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pin(1 3)
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pin(2 1)
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pin(3 6)
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pin(4 4)
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)
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circuit(2 INVX1 location(3600 0)
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pin(0 5)
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pin(1 6)
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pin(2 1)
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pin(3 4)
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)
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)
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)
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# Reference netlist
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reference(
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# Device class section
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class(NMOS MOS4)
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class(PMOS MOS4)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INVX1
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# Nets
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net(1 name(A))
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net(2 name(Z))
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net(3 name(VSS))
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net(4 name(VDD))
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# Outgoing pins and their connections to nets
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pin(1 name(A))
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pin(2 name(Z))
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pin(4 name(VDD))
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pin(3 name(VSS))
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# Devices and their connections
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device(1 NMOS
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name('0')
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param(L 0.25)
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param(W 0.95)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 3)
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terminal(G 1)
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terminal(D 2)
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terminal(B 3)
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)
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device(2 PMOS
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name('1')
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param(L 0.25)
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param(W 1.5)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 4)
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terminal(G 1)
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terminal(D 2)
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terminal(B 4)
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)
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)
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circuit(DINV
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# Nets
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net(1 name('A<1>'))
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net(2 name('A<2>'))
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net(3 name('B<1>'))
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net(4 name('B<2>'))
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net(5 name(VDD))
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net(6 name(VSS))
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# Outgoing pins and their connections to nets
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pin(1 name('A<1>'))
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pin(2 name('A<2>'))
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pin(3 name('B<1>'))
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pin(4 name('B<2>'))
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pin(5 name(VDD))
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pin(6 name(VSS))
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# Subcircuits and their connections
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circuit(1 INVX1 name(A)
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pin(0 1)
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pin(1 3)
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pin(2 5)
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pin(3 6)
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)
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circuit(2 INVX1 name(B)
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pin(0 2)
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pin(1 4)
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pin(2 5)
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pin(3 6)
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)
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)
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circuit(TOP
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# Nets
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net(1 name(A))
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net(2 name(C))
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net(3 name(D))
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net(4 name(B))
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net(5 name(E))
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net(6 name(VDD))
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net(7 name(VSS))
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# Outgoing pins and their connections to nets
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pin(1 name(A))
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pin(2 name(C))
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pin(3 name(D))
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pin(6 name(VDD))
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pin(7 name(VSS))
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# Subcircuits and their connections
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circuit(1 DINV name('0')
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pin(0 1)
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pin(1 2)
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pin(2 4)
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pin(3 5)
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pin(4 6)
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pin(5 7)
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)
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circuit(2 INVX1 name('1')
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pin(0 5)
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pin(1 3)
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pin(2 6)
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pin(3 7)
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)
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)
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)
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# Cross reference
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xref(
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circuit(DINV DINV match
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log(
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entry(warning description('Matching nets B<1> from an ambiguous group of nets'))
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entry(warning description('Matching nets B<2> from an ambiguous group of nets'))
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entry(info description('Matching nets A<1> following an ambiguous match'))
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entry(info description('Matching nets A<2> following an ambiguous match'))
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)
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xref(
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net(1 1 match)
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net(2 2 match)
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net(4 3 warning)
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net(3 4 warning)
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net(5 5 match)
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net(6 6 match)
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pin(() 2 match)
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pin(0 0 match)
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pin(1 1 match)
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pin(2 3 match)
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pin(3 4 match)
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pin(4 5 match)
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circuit(1 1 match)
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circuit(2 2 match)
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)
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)
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circuit(INVX1 INVX1 match
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xref(
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net(3 1 match)
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net(1 2 match)
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net(2 4 match)
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net(4 3 match)
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pin(2 0 match)
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pin(0 1 match)
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pin(1 2 match)
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pin(3 3 match)
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device(2 1 match)
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device(1 2 match)
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)
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)
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circuit(TOP TOP match
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xref(
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net(5 3 match)
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net(1 5 match)
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net(6 6 match)
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net(2 1 match)
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net(3 2 match)
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net(4 7 match)
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pin(() 2 match)
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pin(() 3 match)
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pin(0 0 match)
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pin(1 1 match)
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pin(2 4 match)
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circuit(1 1 match)
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circuit(2 2 match)
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)
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)
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)
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