mirror of https://github.com/KLayout/klayout.git
34 lines
697 B
Plaintext
34 lines
697 B
Plaintext
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source($lvs_test_source)
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("resistor.cir")
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deep
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contact = input(15, 0)
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metal1 = input(16, 0)
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metal1_ver = input(16, 5)
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metal1_lbl = labels(16, 3)
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res = metal1 & metal1_ver
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metal1_not_res = metal1 - metal1_ver
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class MyResistorClass < RBA::DeviceClassResistor
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def initialize
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super
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enable_parameter("W", true)
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enable_parameter("L", true)
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end
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end
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extract_devices(resistor("RR1", 1, MyResistorClass), { "R" => res , "C" => metal1_not_res})
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connect(contact, metal1_not_res)
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connect(metal1_not_res, metal1_lbl)
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align
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netlist.simplify
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compare
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