mirror of https://github.com/KLayout/klayout.git
341 lines
6.2 KiB
Plaintext
341 lines
6.2 KiB
Plaintext
#%lvsdb-klayout
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# Layout
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layout(
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top(testall)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l1 '73/0')
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layer(l3 '44/0')
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layer(l2 '37/0')
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layer(l4 '36/0')
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layer(l5 '35/0')
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layer(l6 '34/0')
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layer(l7 '33/0')
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layer(l8 '32/0')
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layer(l9 '31/0')
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layer(l10 '30/0')
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layer(l11 '75/0')
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layer(l12 '19/0')
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layer(l13 '50/0')
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layer(l14 '51/0')
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layer(l15 '64/0')
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layer(l16 '78/0')
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# Mask layer connectivity
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connect(l1 l1 l2)
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connect(l3 l3 l2)
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connect(l2 l1 l3 l2 l4)
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connect(l4 l2 l4 l5)
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connect(l5 l4 l5 l6)
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connect(l6 l5 l6 l7)
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connect(l7 l6 l7 l8)
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connect(l8 l7 l8 l9)
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connect(l9 l8 l9 l10)
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connect(l10 l9 l10 l11 l12)
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connect(l11 l10 l11)
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connect(l12 l10 l12 l13)
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connect(l13 l12 l13 l14)
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connect(l14 l13 l14 l15 l16)
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connect(l15 l14 l15)
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connect(l16 l14 l16)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(BWBTEST
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# Circuit boundary
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rect((554500 -276000) (403000 162000))
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# Outgoing pins and their connections to nets
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pin(name(A))
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)
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circuit(FWBTEST
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# Circuit boundary
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rect((536500 386500) (404000 179000))
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# Outgoing pins and their connections to nets
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pin(name(A))
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)
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circuit(FBGATEST
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# Circuit boundary
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rect((-449500 412500) (390500 198000))
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# Outgoing pins and their connections to nets
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pin(name(B))
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)
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circuit(BBGATEST
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# Circuit boundary
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rect((-468000 -313000) (442500 226000))
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# Outgoing pins and their connections to nets
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pin(name(A))
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)
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circuit(BDPTEST
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# Circuit boundary
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rect((71500 -290000) (371500 194000))
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(DPTEST
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# Circuit boundary
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rect((64500 86000) (371500 214500))
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# Outgoing pins and their connections to nets
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pin(name(B))
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pin(name(A))
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)
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circuit(FDPTEST
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# Circuit boundary
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rect((59500 359500) (375500 241000))
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# Outgoing pins and their connections to nets
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pin(name(B))
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pin(name(A))
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)
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circuit(testall
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# Circuit boundary
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rect((-577500 -1123000) (1868000 1796000))
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# Nets with their geometries
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net(1
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rect(l2 (345500 455000) (256500 25000))
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rect(l2 (-256500 -146000) (25000 146000))
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rect(l2 (-47000 -183500) (75000 75000))
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rect(l4 (-50000 -50000) (25000 25000))
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rect(l5 (-134000 -25000) (134000 25000))
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rect(l5 (-50000 -50000) (75000 75000))
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rect(l5 (-184000 -78500) (75000 75000))
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rect(l6 (-50000 -50000) (25000 25000))
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rect(l7 (-133500 -21500) (134500 25000))
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rect(l7 (-51000 -53500) (75000 75000))
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rect(l7 (-183500 -73000) (75000 75000))
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rect(l8 (-50000 -50000) (25000 25000))
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rect(l9 (-25000 -152000) (25000 152000))
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rect(l9 (-50000 -50000) (75000 75000))
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rect(l9 (-80500 -217500) (90000 90000))
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rect(l10 (-57500 -57500) (25000 25000))
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rect(l11 (-25000 -25000) (25000 25000))
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)
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net(2
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rect(l2 (-148000 463000) (300000 25000))
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)
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net(3 name($5)
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rect(l9 (348500 26500) (25000 179000))
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rect(l9 (-57500 -58000) (90000 90000))
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rect(l9 (-86000 -288500) (90000 90000))
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rect(l10 (-61500 141000) (25000 25000))
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rect(l10 (-21000 -223500) (25000 25000))
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rect(l11 (-29000 173500) (25000 25000))
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rect(l12 (-58500 -261000) (100000 100000))
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rect(l12 (-100000 -100000) (100000 100000))
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rect(l13 (-62500 -62500) (25000 25000))
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rect(l14 (-24000 -225500) (269500 25000))
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rect(l14 (-270500 7500) (25000 193000))
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rect(l14 (-87500 -87500) (150000 150000))
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)
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net(4 name($8)
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rect(l14 (-126000 -195000) (292000 25000))
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)
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# Subcircuits and their connections
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circuit(2 FDPTEST location(0 0)
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pin(0 1)
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pin(1 2)
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)
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circuit(3 FWBTEST location(0 0) pin(0 1))
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circuit(7 DPTEST location(0 0)
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pin(0 3)
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pin(1 1)
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)
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circuit(8 FBGATEST location(0 0) pin(0 2))
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circuit(9 BDPTEST location(0 0)
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pin(0 3)
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pin(1 4)
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)
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circuit(10 BWBTEST location(0 0) pin(0 3))
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circuit(14 BBGATEST location(0 0) pin(0 4))
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)
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)
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# Reference netlist
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reference(
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(FBGATEST
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(FWBTEST
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(FDPTEST
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(DPTEST
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(BDPTEST
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(BWBTEST
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(BBGATEST
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# Outgoing pins and their connections to nets
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pin(name(A))
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pin(name(B))
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)
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circuit(TESTALL
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# Nets
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net(1 name(A1))
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net(2 name(B1))
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net(3 name(C1))
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net(4 name(G1))
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net(5 name(D1))
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net(6 name(E1))
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net(7 name(H1))
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net(8 name(F1))
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# Subcircuits and their connections
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circuit(1 FBGATEST name(UFBGA)
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pin(0 1)
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pin(1 2)
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)
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circuit(2 FWBTEST name(UFWB)
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pin(0 3)
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pin(1 4)
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)
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circuit(3 FDPTEST name(UFDP)
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pin(0 2)
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pin(1 3)
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)
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circuit(4 DPTEST name(UDP)
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pin(0 3)
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pin(1 5)
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)
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circuit(5 BDPTEST name(UBDP)
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pin(0 5)
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pin(1 6)
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)
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circuit(6 BWBTEST name(UBWB)
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pin(0 5)
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pin(1 7)
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)
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circuit(7 BBGATEST name(UBBGA)
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pin(0 6)
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pin(1 8)
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)
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)
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)
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# Cross reference
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xref(
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circuit(BBGATEST BBGATEST match
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xref(
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pin(() 1 match)
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pin(0 0 match)
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)
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)
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circuit(BDPTEST BDPTEST match
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xref(
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pin(0 0 match)
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pin(1 1 match)
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)
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)
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circuit(BWBTEST BWBTEST match
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xref(
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pin(() 1 match)
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pin(0 0 match)
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)
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)
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circuit(DPTEST DPTEST match
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xref(
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pin(1 0 match)
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pin(0 1 match)
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)
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)
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circuit(FBGATEST FBGATEST match
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xref(
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pin(() 0 match)
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pin(0 1 match)
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)
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)
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circuit(FDPTEST FDPTEST match
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xref(
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pin(1 0 match)
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pin(0 1 match)
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)
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)
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circuit(FWBTEST FWBTEST match
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xref(
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pin(() 1 match)
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pin(0 0 match)
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)
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)
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circuit(testall TESTALL match
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xref(
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net(2 2 match)
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net(1 3 match)
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net(3 5 match)
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net(4 6 match)
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circuit(14 7 match)
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circuit(9 5 match)
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circuit(10 6 match)
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circuit(7 4 match)
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circuit(8 1 match)
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circuit(2 3 match)
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circuit(3 2 match)
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)
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)
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)
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