mirror of https://github.com/KLayout/klayout.git
67 lines
1.4 KiB
Plaintext
67 lines
1.4 KiB
Plaintext
# Flat extraction
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source($drc_test_source)
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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poly = input(3, 0)
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poly_lbl = input(3, 1)
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diff_cont = input(4, 0)
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poly_cont = input(5, 0)
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metal1 = input(6, 0)
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metal1_lbl = input(6, 1)
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via1 = input(7, 0)
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metal2 = input(8, 0)
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metal2_lbl = input(8, 1)
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# Computed layers
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pactive = active & nwell
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pgate = pactive & poly
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psd = pactive - pgate
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nactive = active - nwell
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ngate = nactive & poly
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nsd = nactive - ngate
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# PMOS transistor device extraction
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pmos_ex = RBA::DeviceExtractorMOS3Transistor::new("PMOS")
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extract_devices(pmos_ex, { "SD" => psd, "G" => pgate, "P" => poly })
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# NMOS transistor device extraction
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nmos_ex = RBA::DeviceExtractorMOS3Transistor::new("NMOS")
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extract_devices(nmos_ex, { "SD" => nsd, "G" => ngate, "P" => poly })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, diff_cont)
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connect(nsd, diff_cont)
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connect(poly, poly_cont)
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connect(poly_cont, metal1)
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connect(diff_cont, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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connect(poly, poly_lbl)
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connect(metal1, metal1_lbl)
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connect(metal2, metal2_lbl)
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# Actually performs the extraction
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connect_implicit("{VDDZ,VSSZ,NEXT,FB}")
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netlist = l2n_data.netlist
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# Writes the netlist
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writer = RBA::NetlistSpiceWriter::new
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netlist.write($drc_test_target, writer, "RINGO netlist")
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