Matthias Koefferlein
c682cc85d0
Generalized concept of region, texts etc. into 'shape collections'. Fixed LVS and DRC tests.
2020-05-21 23:59:30 +02:00
Matthias Koefferlein
d0fc1edf35
Further updates of test data.
2019-12-15 01:45:15 +01:00
Matthias Koefferlein
550e2622bf
Put more amphasis on net names to resolve ambiguities
...
The problem was that with the floating test case, the
ambiguity resolution sometimes assigned the wrong pins
and floating pins/connected pins were swapped.
One option is to make the ambiguity resolver consider
the pin connection state when tenatively evaluating
nodes.
Another option is to put more emphasis on net names
and use them for ambiguity resolution. This has helped
here.
2019-08-30 10:24:55 +02:00
Matthias Koefferlein
169cc5246d
WIP: updated golden data for new device sorting in cross reference.
2019-07-27 20:37:41 +02:00
Matthias Koefferlein
b4fa4b1bae
Flattening of layout with circuit flattening.
...
Technically, the layout isn't flattened, but connections are made
which allow regenerating the layout even after the circuit
has been flattened.
2019-07-27 00:37:22 +02:00
Matthias Koefferlein
64d32c1ae9
LVS tests are more stable because of sorting of terminal names before assigning them (no hash order)
2019-07-24 21:23:19 +02:00
Matthias Koefferlein
c7e883cdb2
SPICE reader now assigned net names as pin names.
2019-07-12 19:00:27 +02:00
Matthias Koefferlein
0d9273aaf6
WIP: new subcircuit match algorithm
2019-07-11 00:16:36 +02:00
Matthias Koefferlein
b48453633f
WIP: some fixes and small enhancements. New tests.
2019-07-08 00:09:10 +02:00