luke
/
klayout
mirror of https://github.com/KLayout/klayout.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Updated documentation

This commit is contained in:
Matthias Koefferlein 2019-12-17 20:29:37 +01:00
parent d0e6efa484
commit f174e5b83d
2 changed files with 53 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/lay/lay/doc/about/drc_ref_global.xml
View File

@ -234,6 +234,7 @@ See <a href="/about/drc_ref_netter.xml#connect_global">Netter#connect_global</a>
<a name="connect_implicit"/><p>Usage:</p> <a name="connect_implicit"/><p>Usage:</p>
<ul> <ul>
<li><tt>connect_implicit(label_pattern)</tt></li> <li><tt>connect_implicit(label_pattern)</tt></li>
<li><tt>connect_implicit(cell_pattern, label_pattern)</tt></li>
</ul> </ul>
<p> <p>
See <a href="/about/drc_ref_netter.xml#connect_implicit">Netter#connect_implicit</a> for a description of that function. See <a href="/about/drc_ref_netter.xml#connect_implicit">Netter#connect_implicit</a> for a description of that function.

52
src/lay/lay/doc/manual/lvs_connect.xml
View File

@ -131,4 +131,56 @@ connect(metal2, metal2_labels)</pre>
opens may pass unnoticed. opens may pass unnoticed.
</p> </p>
<p>
You can include labels of a certain class in a "connect_implicit" statement
using glob-style pattern:
</p>
<pre>connect_implicit("VDD*")</pre>
<p>
This will connect all nets labelled with "VDD1" for example or those labelled
with "VDD_5V". However, this statement will only connect "VDD1" with "VDD1",
<b>not</b> nets with different labels. I.e. it will not connect "VDD1" with "VDD2"
labels.
</p>
<p>
"connect_implicit" can be present multiple times. Each statement extends the
choice of labels which will be connected.
</p>
<p>
The standard method "connect_implicit" will only act on top-level cells.
However, sometimes the construction of certain library cells requires
connecting nets inside subcells. For example, memory cells are often made
in a way that their common rails are exposed on different sides but
not connected internally. Formally, those cells need to be described by
circuits with multiple pins in the schematic. As the cells are only used
in certain contexts where these rails are connected, it's sufficient to
specify a single pin and connect the rails inside the subcells if labelled
properly. The following statement will connect all nets labelled with "VDD"
from the "MEMCELL" subcell:
</p>
<pre>connect_implicit("MEMCELL", "VDD")</pre>
<p>
If MEMCELL is the top cell, the single-argument, unspecific "connect_implicit"
rule is applied, unless no such rule is given. In other words: the unspecific
rule has priority for the top cell.
</p>
<p>
The cell argument can be a glob-style pattern. In this case, the rule is
applied to all matching cells. Again, the "connect_implicit" rule may be
given multiple times. In this case, all matching occurances act together.
</p>
<p>
The "connect_implicit" statements must be given before the netlist is
extracted. Typically this happens before or shortly after "connect"
statements.
</p>
</doc> </doc>