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Adjusting testdata. Needed because we do not create all circuits as a side effect in device extraction

This commit is contained in:
Matthias Koefferlein 2024-07-14 23:19:13 +02:00
parent 3fbcfbfd5a
commit eacc19b18a
22 changed files with 283 additions and 1377 deletions
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2
src/lvs/unit_tests/lvsTests.cc
View File

@ -148,7 +148,7 @@ TEST(16_private)
TEST(17_private)
{
test_is_long_runner ();
run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_4.lvsdb");
run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_5.lvsdb");
}
TEST(18_private)

BIN
testdata/algo/l2n_writer_au_2.gds vendored
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Binary file not shown.

12
testdata/algo/l2n_writer_au_p.txt vendored
View File

@ -71,7 +71,13 @@ D(D$NMOS$1 NMOS
)
X(INV2
R((-1700 -800) (3100 4600))
F(#17 #42)
F('a_"non_quoted"_string' 's')
F('a_float' ##0.5)
N(1 I(IN)
F(#17 #142)
F('a_"non_quoted"_string' '1s')
F('a_float' ##10.5)
R(poly (-525 -250) (250 2500))
R(poly (-1425 -630) (1300 360))
R(poly (-125 -2780) (250 1600))
@ -191,13 +197,7 @@ X(INV2
)
X(RINGO
R((-1720 -800) (26880 4600))
F(#17 #42)
F('a_"non_quoted"_string' 's')
F('a_float' ##0.5)
N(1 I(FB)
F(#17 #142)
F('a_"non_quoted"_string' '1s')
F('a_float' ##10.5)
R(metal1 (-1700 1620) (360 360))
R(via1 (-305 -305) (250 250))
R(via1 (24230 -250) (250 250))

8
testdata/lvs/floating.cir vendored
View File

@ -43,8 +43,8 @@ X$2 3 5 2 6 INVX1
* net 2 VDD
* net 3 IN
* net 4 VSS
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* device instance $1 r0 *1 0.85,2.135 NMOS
M$1 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* device instance $2 r0 *1 0.85,5.8 PMOS
M$2 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
.ENDS INVX1

32
testdata/lvs/floating.lvsdb vendored
View File

@ -135,20 +135,7 @@ layout(
pin(4 name(VSS))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 2)
terminal(G 3)
terminal(D 1)
terminal(B 2)
)
device(2 D$NMOS
device(1 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
@ -161,6 +148,19 @@ layout(
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 2)
terminal(G 3)
terminal(D 1)
terminal(B 2)
)
)
circuit(DINV
@ -410,8 +410,8 @@ xref(
pin(0 1 match)
pin(1 2 match)
pin(3 3 match)
device(2 1 match)
device(1 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(TOP TOP match

10
testdata/lvs/invchain_cheat.cir.1 → testdata/lvs/invchain_cheat.cir vendored
View File

@ -6,17 +6,17 @@ X$2 \$5 \$6 \$4 \$5 VDD VSS INV2
X$3 VSS VDD \$6 OUT INV
.ENDS INVCHAIN
.SUBCKT INV2 \$I8 \$I7 \$I6 \$I5 \$I4 \$I2
X$1 \$I2 \$I4 \$I6 \$I8 INV
X$2 \$I2 \$I4 \$I5 \$I7 INV
.ENDS INV2
.SUBCKT INV3 3 5 7 4 6 8 \$I4 \$I2
X$1 \$I2 \$I4 3 4 INV
X$2 \$I2 \$I4 5 6 INV
X$3 \$I2 \$I4 7 8 INV
.ENDS INV3
.SUBCKT INV2 \$I8 \$I7 \$I6 \$I5 \$I4 \$I2
X$1 \$I2 \$I4 \$I6 \$I8 INV
X$2 \$I2 \$I4 \$I5 \$I7 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U

54
testdata/lvs/invchain_cheat.lvsdb vendored
View File

@ -116,33 +116,6 @@ J(
T(D 1)
)
)
X(INV2
R((0 0) (5500 4600))
N(1)
N(2)
N(3)
N(4)
N(5)
N(6)
P(1)
P(2)
P(3)
P(4)
P(5)
P(6)
X(1 INV M O(180) Y(1500 800)
P(0 6)
P(1 5)
P(2 3)
P(3 1)
)
X(2 INV Y(4000 800)
P(0 6)
P(1 5)
P(2 4)
P(3 2)
)
)
X(INV3
R((0 0) (6300 4600))
N(1 I('3')
@ -192,6 +165,33 @@ J(
P(3 6)
)
)
X(INV2
R((0 0) (5500 4600))
N(1)
N(2)
N(3)
N(4)
N(5)
N(6)
P(1)
P(2)
P(3)
P(4)
P(5)
P(6)
X(1 INV M O(180) Y(1500 800)
P(0 6)
P(1 5)
P(2 3)
P(3 1)
)
X(2 INV Y(4000 800)
P(0 6)
P(1 5)
P(2 4)
P(3 2)
)
)
X(INVCHAIN
R((-1500 -800) (10400 4600))
N(1 I(IN)

8
testdata/lvs/layer_names.cir vendored
View File

@ -43,8 +43,8 @@ X$2 3 5 2 6 INVX1
* net 2 VDD
* net 3 IN
* net 4 VSS
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* device instance $1 r0 *1 0.85,2.135 NMOS
M$1 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* device instance $2 r0 *1 0.85,5.8 PMOS
M$2 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
.ENDS INVX1

32
testdata/lvs/layer_names.lvsdb vendored
View File

@ -135,20 +135,7 @@ layout(
pin(4 name(VSS))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 2)
terminal(G 3)
terminal(D 1)
terminal(B 2)
)
device(2 D$NMOS
device(1 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
@ -161,6 +148,19 @@ layout(
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 2)
terminal(G 3)
terminal(D 1)
terminal(B 2)
)
)
circuit(DINV
@ -410,8 +410,8 @@ xref(
pin(0 1 match)
pin(1 2 match)
pin(3 3 match)
device(2 1 match)
device(1 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(TOP TOP match

8
testdata/lvs/ringo_mixed_hierarchy.cir vendored
View File

@ -57,8 +57,8 @@ M$4 4 1 15 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
* net 3 VSS
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* device instance $1 r0 *1 0.85,2.135 NMOS
M$1 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* device instance $2 r0 *1 0.85,5.8 PMOS
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
.ENDS INVX1

32
testdata/lvs/ringo_mixed_hierarchy.lvsdb vendored
View File

@ -190,20 +190,7 @@ layout(
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
device(1 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
@ -216,6 +203,19 @@ layout(
terminal(D 2)
terminal(B 6)
)
device(2 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
)
circuit(RINGO
@ -770,8 +770,8 @@ xref(
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
device(1 2 match)
device(2 1 match)
)
)
circuit(RINGO RINGO match

22
testdata/lvs/ringo_simple_blackboxing.cir vendored
View File

@ -38,6 +38,17 @@ X$20 6 15 9 6 14 9 INVX1
X$21 6 11 9 6 15 9 INVX1
.ENDS RINGO
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin BULK
.SUBCKT ND2X1 1 2 3 4 5 6 7
.ENDS ND2X1
* cell INVX2
* pin IN
* pin VDD
@ -57,14 +68,3 @@ X$21 6 11 9 6 15 9 INVX1
* pin BULK
.SUBCKT INVX1 1 2 3 4 5 6
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin BULK
.SUBCKT ND2X1 1 2 3 4 5 6 7
.ENDS ND2X1

30
testdata/lvs/ringo_simple_blackboxing.lvsdb vendored
View File

@ -43,21 +43,6 @@ layout(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 250) (2600 7750))
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin()
pin(name(B))
pin(name(A))
pin(name(BULK))
)
circuit(INVX1
# Circuit boundary
@ -85,6 +70,21 @@ layout(
pin()
pin(name(BULK))
)
circuit(ND2X1
# Circuit boundary
rect((-100 250) (2600 7750))
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin()
pin(name(B))
pin(name(A))
pin(name(BULK))
)
circuit(RINGO

22
testdata/lvs/ringo_simple_blackboxing_netter.cir vendored
View File

@ -38,6 +38,17 @@ X$20 6 15 9 6 14 9 INVX1
X$21 6 11 9 6 15 9 INVX1
.ENDS RINGO
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin BULK
.SUBCKT ND2X1 1 2 3 4 5 6 7
.ENDS ND2X1
* cell INVX2
* pin IN
* pin VDD
@ -57,14 +68,3 @@ X$21 6 11 9 6 15 9 INVX1
* pin BULK
.SUBCKT INVX1 1 2 3 4 5 6
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin BULK
.SUBCKT ND2X1 1 2 3 4 5 6 7
.ENDS ND2X1

30
testdata/lvs/ringo_simple_blackboxing_netter.lvsdb vendored
View File

@ -43,21 +43,6 @@ layout(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 250) (2600 7750))
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin()
pin(name(B))
pin(name(A))
pin(name(BULK))
)
circuit(INVX1
# Circuit boundary
@ -85,6 +70,21 @@ layout(
pin()
pin(name(BULK))
)
circuit(ND2X1
# Circuit boundary
rect((-100 250) (2600 7750))
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin()
pin(name(B))
pin(name(A))
pin(name(BULK))
)
circuit(RINGO

20
testdata/lvs/ringo_simple_simplification_with_align.cir vendored
View File

@ -26,16 +26,16 @@ X$5 6 4 9 6 3 9 INVX1
X$6 6 5 9 6 4 9 INVX1
* cell instance $7 r0 *1 22.2,0
X$7 5 6 7 9 6 9 INVX2
* cell instance $13 r0 *1 7.8,0
X$13 6 12 9 6 10 9 INVX1
* cell instance $14 r0 *1 9.6,0
X$14 6 13 9 6 12 9 INVX1
* cell instance $15 r0 *1 11.4,0
X$15 6 14 9 6 13 9 INVX1
* cell instance $16 r0 *1 13.2,0
X$16 6 15 9 6 14 9 INVX1
* cell instance $17 r0 *1 15,0
X$17 6 11 9 6 15 9 INVX1
* cell instance $17 r0 *1 7.8,0
X$17 6 12 9 6 10 9 INVX1
* cell instance $18 r0 *1 9.6,0
X$18 6 13 9 6 12 9 INVX1
* cell instance $19 r0 *1 11.4,0
X$19 6 14 9 6 13 9 INVX1
* cell instance $20 r0 *1 13.2,0
X$20 6 15 9 6 14 9 INVX1
* cell instance $21 r0 *1 15,0
X$21 6 11 9 6 15 9 INVX1
.ENDS RINGO
* cell INVX2

20
testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 vendored
View File

@ -644,7 +644,7 @@ layout(
pin(4 6)
pin(5 9)
)
circuit(13 INVX1 location(7800 0)
circuit(17 INVX1 location(7800 0)
pin(0 6)
pin(1 12)
pin(2 9)
@ -652,7 +652,7 @@ layout(
pin(4 10)
pin(5 9)
)
circuit(14 INVX1 location(9600 0)
circuit(18 INVX1 location(9600 0)
pin(0 6)
pin(1 13)
pin(2 9)
@ -660,7 +660,7 @@ layout(
pin(4 12)
pin(5 9)
)
circuit(15 INVX1 location(11400 0)
circuit(19 INVX1 location(11400 0)
pin(0 6)
pin(1 14)
pin(2 9)
@ -668,7 +668,7 @@ layout(
pin(4 13)
pin(5 9)
)
circuit(16 INVX1 location(13200 0)
circuit(20 INVX1 location(13200 0)
pin(0 6)
pin(1 15)
pin(2 9)
@ -676,7 +676,7 @@ layout(
pin(4 14)
pin(5 9)
)
circuit(17 INVX1 location(15000 0)
circuit(21 INVX1 location(15000 0)
pin(0 6)
pin(1 11)
pin(2 9)
@ -1080,11 +1080,11 @@ xref(
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(13 4 match)
circuit(14 5 match)
circuit(15 6 match)
circuit(16 7 match)
circuit(17 8 match)
circuit(17 4 match)
circuit(18 5 match)
circuit(19 6 match)
circuit(20 7 match)
circuit(21 8 match)
circuit(4 9 match)
circuit(5 10 match)
circuit(6 11 match)

1095
testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 vendored
View File

File diff suppressed because it is too large Load Diff

10
testdata/lvs/soft_connect3.cir vendored
View File

@ -10,12 +10,12 @@ X$1 \$5 \$1 \$4 SUBSTRATE NTRANS
X$2 \$5 \$2 \$4 \$3 PTRANS
.ENDS INV
.SUBCKT PTRANS \$1 \$3 \$5 \$I3
M$1 \$3 \$5 \$1 \$I3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS PTRANS
.SUBCKT NTRANS \$1 \$3 \$5 SUBSTRATE
M$1 \$3 \$5 \$1 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS NTRANS
.SUBCKT PTRANS \$1 \$3 \$5 \$I3
M$1 \$3 \$5 \$1 \$I3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS PTRANS

72
testdata/lvs/soft_connect3.l2n vendored
View File

@ -73,42 +73,6 @@ D(D$NMOS NMOS
R(l7 (-125 -475) (250 950))
)
)
X(NTRANS
R((-1000 -800) (2000 1600))
N(1
R(l8 (-510 -310) (220 220))
R(l8 (-220 180) (220 220))
R(l12 (-290 -690) (360 760))
R(l6 (-680 -855) (775 950))
)
N(2
R(l8 (290 -310) (220 220))
R(l8 (-220 180) (220 220))
R(l12 (-290 -690) (360 760))
R(l6 (-455 -855) (775 950))
)
N(3
R(l4 (-125 -800) (250 1600))
)
N(4 I(SUBSTRATE))
P(1)
P(2)
P(3)
P(4 I(SUBSTRATE))
D(1 D$NMOS
Y(0 0)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 1)
T(G 3)
T(D 2)
T(B 4)
)
)
X(PTRANS
R((-1000 -800) (2000 1600))
N(1
@ -145,6 +109,42 @@ X(PTRANS
T(B 4)
)
)
X(NTRANS
R((-1000 -800) (2000 1600))
N(1
R(l8 (-510 -310) (220 220))
R(l8 (-220 180) (220 220))
R(l12 (-290 -690) (360 760))
R(l6 (-680 -855) (775 950))
)
N(2
R(l8 (290 -310) (220 220))
R(l8 (-220 180) (220 220))
R(l12 (-290 -690) (360 760))
R(l6 (-455 -855) (775 950))
)
N(3
R(l4 (-125 -800) (250 1600))
)
N(4 I(SUBSTRATE))
P(1)
P(2)
P(3)
P(4 I(SUBSTRATE))
D(1 D$NMOS
Y(0 0)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 1)
T(G 3)
T(D 2)
T(B 4)
)
)
X(INV
R((-1500 -800) (3000 4600))
N(1

75
testdata/python/dbLayoutToNetlist.py vendored
View File

@ -286,19 +286,7 @@ end;
# Perform netlist extraction
l2n.extract_netlist()
self.assertEqual(str(l2n.netlist()), """circuit RINGO ();
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
end;
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
self.assertEqual(str(l2n.netlist()), """circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
@ -310,6 +298,18 @@ circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
end;
circuit TRANS ($1=$1,$2=$2,$3=$3);
end;
circuit RINGO ();
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
end;
""")
# cleanup now
@ -401,18 +401,7 @@ end;
# Perform netlist extraction
l2n.extract_netlist()
self.assertEqual(str(l2n.netlist()), """circuit RINGO ();
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
self.assertEqual(str(l2n.netlist()), """circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
@ -424,29 +413,41 @@ circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
end;
circuit TRANS ($1=$1,$2=$2,$3=$3);
end;
""")
l2n.netlist().combine_devices()
l2n.netlist().make_top_level_pins()
l2n.netlist().purge()
self.assertEqual(str(l2n.netlist()), """circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit RINGO ();
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
""")
l2n.netlist().combine_devices()
l2n.netlist().make_top_level_pins()
l2n.netlist().purge()
print('"""' + str(l2n.netlist()) + '"""')
self.assertEqual(str(l2n.netlist()), """circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
""")
# cleanup now

66
testdata/ruby/dbLayoutToNetlist.rb vendored
View File

@ -368,18 +368,6 @@ END
l2n.extract_netlist
assert_equal(l2n.netlist.to_s, <<END)
circuit RINGO ();
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
end;
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
@ -392,6 +380,18 @@ circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
end;
circuit TRANS ($1=$1,$2=$2,$3=$3);
end;
circuit RINGO ();
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
end;
END
# cleanup now
@ -484,17 +484,6 @@ END
l2n.extract_netlist
assert_equal(l2n.netlist.to_s, <<END)
circuit RINGO ();
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
@ -507,6 +496,17 @@ circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
end;
circuit TRANS ($1=$1,$2=$2,$3=$3);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit RINGO ();
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
END
l2n.netlist.combine_devices
@ -514,6 +514,16 @@ END
l2n.netlist.purge
assert_equal(l2n.netlist.to_s, <<END)
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
@ -521,16 +531,6 @@ circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
end;
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
end;
circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
end;
END
# cleanup now