mirror of https://github.com/KLayout/klayout.git
Simplified test code
This commit is contained in:
Matthias Koefferlein
parent
5b9087c864
commit
e71a4dfb92
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@ -3131,234 +3131,6 @@ TEST(12_FlattenCircuitDoesFlattenLayout)
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db::compare_layouts (_this, ly, au);
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}
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TEST(13_JoinNetNames)
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{
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db::Layout ly;
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db::LayerMap lmap;
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unsigned int nwell = define_layer (ly, lmap, 1);
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unsigned int active = define_layer (ly, lmap, 2);
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unsigned int pplus = define_layer (ly, lmap, 10);
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unsigned int nplus = define_layer (ly, lmap, 11);
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unsigned int poly = define_layer (ly, lmap, 3);
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unsigned int poly_lbl = define_layer (ly, lmap, 3, 1);
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unsigned int diff_cont = define_layer (ly, lmap, 4);
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unsigned int poly_cont = define_layer (ly, lmap, 5);
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unsigned int metal1 = define_layer (ly, lmap, 6);
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unsigned int metal1_lbl = define_layer (ly, lmap, 6, 1);
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unsigned int via1 = define_layer (ly, lmap, 7);
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unsigned int metal2 = define_layer (ly, lmap, 8);
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unsigned int metal2_lbl = define_layer (ly, lmap, 8, 1);
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{
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db::LoadLayoutOptions options;
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options.get_options<db::CommonReaderOptions> ().layer_map = lmap;
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options.get_options<db::CommonReaderOptions> ().create_other_layers = false;
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std::string fn (tl::testdata ());
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fn = tl::combine_path (fn, "algo");
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fn = tl::combine_path (fn, "device_extract_l13.gds");
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tl::InputStream stream (fn);
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db::Reader reader (stream);
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reader.read (ly, options);
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}
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db::Cell &tc = ly.cell (*ly.begin_top_down ());
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db::LayoutToNetlist l2n (db::RecursiveShapeIterator (ly, tc, std::set<unsigned int> ()));
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std::unique_ptr<db::Region> rbulk (l2n.make_layer ("bulk"));
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std::unique_ptr<db::Region> rnwell (l2n.make_layer (nwell, "nwell"));
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std::unique_ptr<db::Region> ractive (l2n.make_layer (active, "active"));
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std::unique_ptr<db::Region> rpplus (l2n.make_layer (pplus, "pplus"));
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std::unique_ptr<db::Region> rnplus (l2n.make_layer (nplus, "nplus"));
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std::unique_ptr<db::Region> rpoly (l2n.make_polygon_layer (poly, "poly"));
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std::unique_ptr<db::Texts> rpoly_lbl (l2n.make_text_layer (poly_lbl, "poly_lbl"));
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std::unique_ptr<db::Region> rdiff_cont (l2n.make_polygon_layer (diff_cont, "diff_cont"));
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std::unique_ptr<db::Region> rpoly_cont (l2n.make_polygon_layer (poly_cont, "poly_cont"));
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std::unique_ptr<db::Region> rmetal1 (l2n.make_polygon_layer (metal1, "metal1"));
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std::unique_ptr<db::Texts> rmetal1_lbl (l2n.make_text_layer (metal1_lbl, "metal1_lbl"));
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std::unique_ptr<db::Region> rvia1 (l2n.make_polygon_layer (via1, "via1"));
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std::unique_ptr<db::Region> rmetal2 (l2n.make_polygon_layer (metal2, "metal2"));
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std::unique_ptr<db::Texts> rmetal2_lbl (l2n.make_text_layer (metal2_lbl, "metal2_lbl"));
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// derived regions
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db::Region ractive_in_nwell = *ractive & *rnwell;
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db::Region rpactive = ractive_in_nwell & *rpplus;
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db::Region rntie = ractive_in_nwell & *rnplus;
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db::Region rpgate = rpactive & *rpoly;
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db::Region rpsd = rpactive - rpgate;
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db::Region ractive_outside_nwell = *ractive - *rnwell;
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db::Region rnactive = ractive_outside_nwell & *rnplus;
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db::Region rptie = ractive_outside_nwell & *rpplus;
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db::Region rngate = rnactive & *rpoly;
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db::Region rnsd = rnactive - rngate;
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// return the computed layers into the original layout and write it for debugging purposes
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unsigned int lgate = ly.insert_layer (db::LayerProperties (20, 0)); // 20/0 -> Gate
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unsigned int lsd = ly.insert_layer (db::LayerProperties (21, 0)); // 21/0 -> Source/Drain
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unsigned int lpdiff = ly.insert_layer (db::LayerProperties (22, 0)); // 22/0 -> P Diffusion
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unsigned int lndiff = ly.insert_layer (db::LayerProperties (23, 0)); // 23/0 -> N Diffusion
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unsigned int lptie = ly.insert_layer (db::LayerProperties (24, 0)); // 24/0 -> P Tie
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unsigned int lntie = ly.insert_layer (db::LayerProperties (25, 0)); // 25/0 -> N Tie
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rpgate.insert_into (&ly, tc.cell_index (), lgate);
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rngate.insert_into (&ly, tc.cell_index (), lgate);
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rpsd.insert_into (&ly, tc.cell_index (), lsd);
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rnsd.insert_into (&ly, tc.cell_index (), lsd);
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rpsd.insert_into (&ly, tc.cell_index (), lpdiff);
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rnsd.insert_into (&ly, tc.cell_index (), lndiff);
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rpsd.insert_into (&ly, tc.cell_index (), lptie);
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rnsd.insert_into (&ly, tc.cell_index (), lntie);
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db::NetlistDeviceExtractorMOS4Transistor pmos_ex ("PMOS");
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db::NetlistDeviceExtractorMOS4Transistor nmos_ex ("NMOS");
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// device extraction
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db::NetlistDeviceExtractor::input_layers dl;
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dl["SD"] = &rpsd;
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dl["G"] = &rpgate;
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dl["P"] = rpoly.get (); // not needed for extraction but to return terminal shapes
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dl["W"] = rnwell.get ();
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l2n.extract_devices (pmos_ex, dl);
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dl["SD"] = &rnsd;
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dl["G"] = &rngate;
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dl["P"] = rpoly.get (); // not needed for extraction but to return terminal shapes
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dl["W"] = rbulk.get ();
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l2n.extract_devices (nmos_ex, dl);
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// net extraction
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l2n.register_layer (rpsd, "psd");
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l2n.register_layer (rnsd, "nsd");
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l2n.register_layer (rptie, "ptie");
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l2n.register_layer (rntie, "ntie");
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// Intra-layer
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l2n.connect (rpsd);
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l2n.connect (rnsd);
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l2n.connect (*rnwell);
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l2n.connect (*rpoly);
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l2n.connect (*rdiff_cont);
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l2n.connect (*rpoly_cont);
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l2n.connect (*rmetal1);
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l2n.connect (*rvia1);
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l2n.connect (*rmetal2);
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l2n.connect (rptie);
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l2n.connect (rntie);
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// Inter-layer
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l2n.connect (rpsd, *rdiff_cont);
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l2n.connect (rnsd, *rdiff_cont);
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l2n.connect (*rpoly, *rpoly_cont);
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l2n.connect (*rpoly_cont, *rmetal1);
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l2n.connect (*rdiff_cont, *rmetal1);
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l2n.connect (*rdiff_cont, rptie);
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l2n.connect (*rdiff_cont, rntie);
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l2n.connect (*rnwell, rntie);
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l2n.connect (*rmetal1, *rvia1);
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l2n.connect (*rvia1, *rmetal2);
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l2n.connect (*rpoly, *rpoly_lbl); // attaches labels
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l2n.connect (*rmetal1, *rmetal1_lbl); // attaches labels
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l2n.connect (*rmetal2, *rmetal2_lbl); // attaches labels
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// Global
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l2n.connect_global (rntie, "VDD");
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l2n.connect_global (*rnwell, "VDD");
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l2n.connect_global (rptie, "VSS");
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l2n.connect_global (*rbulk, "VSS");
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// Extract with joining VSS and VDD
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l2n.join_net_names (tl::GlobPattern ("{VSS,VDD}"));
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l2n.extract_netlist ();
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// debug layers produced for nets
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// 201/0 -> Well
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// 203/0 -> Poly
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// 204/0 -> Diffusion contacts
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// 205/0 -> Poly contacts
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// 206/0 -> Metal1
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// 207/0 -> Via1
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// 208/0 -> Metal2
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// 210/0 -> N source/drain
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// 211/0 -> P source/drain
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// 212/0 -> N tie
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// 213/0 -> P tie
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std::map<const db::Region *, unsigned int> dump_map;
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dump_map [&rpsd ] = ly.insert_layer (db::LayerProperties (210, 0));
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dump_map [&rnsd ] = ly.insert_layer (db::LayerProperties (211, 0));
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dump_map [&rptie ] = ly.insert_layer (db::LayerProperties (212, 0));
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dump_map [&rntie ] = ly.insert_layer (db::LayerProperties (213, 0));
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dump_map [rbulk.get () ] = ly.insert_layer (db::LayerProperties (214, 0));
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dump_map [rnwell.get () ] = ly.insert_layer (db::LayerProperties (201, 0));
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dump_map [rpoly.get () ] = ly.insert_layer (db::LayerProperties (203, 0));
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dump_map [rdiff_cont.get ()] = ly.insert_layer (db::LayerProperties (204, 0));
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dump_map [rpoly_cont.get ()] = ly.insert_layer (db::LayerProperties (205, 0));
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dump_map [rmetal1.get () ] = ly.insert_layer (db::LayerProperties (206, 0));
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dump_map [rvia1.get () ] = ly.insert_layer (db::LayerProperties (207, 0));
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dump_map [rmetal2.get () ] = ly.insert_layer (db::LayerProperties (208, 0));
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// write nets to layout
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db::CellMapping cm = l2n.cell_mapping_into (ly, tc);
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dump_nets_to_layout (l2n, ly, dump_map, cm);
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dump_map.clear ();
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dump_map [&rpsd ] = ly.insert_layer (db::LayerProperties (310, 0));
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dump_map [&rnsd ] = ly.insert_layer (db::LayerProperties (311, 0));
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dump_map [&rptie ] = ly.insert_layer (db::LayerProperties (312, 0));
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dump_map [&rntie ] = ly.insert_layer (db::LayerProperties (313, 0));
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dump_map [rbulk.get () ] = ly.insert_layer (db::LayerProperties (314, 0));
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dump_map [rnwell.get () ] = ly.insert_layer (db::LayerProperties (301, 0));
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dump_map [rpoly.get () ] = ly.insert_layer (db::LayerProperties (303, 0));
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dump_map [rdiff_cont.get ()] = ly.insert_layer (db::LayerProperties (304, 0));
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dump_map [rpoly_cont.get ()] = ly.insert_layer (db::LayerProperties (305, 0));
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dump_map [rmetal1.get () ] = ly.insert_layer (db::LayerProperties (306, 0));
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dump_map [rvia1.get () ] = ly.insert_layer (db::LayerProperties (307, 0));
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dump_map [rmetal2.get () ] = ly.insert_layer (db::LayerProperties (308, 0));
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dump_recursive_nets_to_layout (l2n, ly, dump_map, cm);
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// compare netlist as string
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CHECKPOINT ();
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db::compare_netlist (_this, *l2n.netlist (),
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"circuit RINGO ();\n"
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" subcircuit INV2 $1 (IN=$I7,$2=FB,OUT=OSC,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $2 (IN=FB,$2=$I34,OUT=$I17,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $3 (IN=$3,$2=$I38,OUT=$I4,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $4 (IN=$I2,$2=$I37,OUT=$3,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $5 (IN=$I4,$2=$I39,OUT=$I5,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $6 (IN=$I5,$2=$I40,OUT=$I6,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $7 (IN=$I6,$2=$I41,OUT=$I7,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $8 (IN=$I17,$2=$I35,OUT=$I1,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $9 (IN=$I1,$2=$I36,OUT=$I2,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5,VDD=VDD,VSS=VSS);\n"
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" device PMOS $1 (S=$2,G=IN,D=$5,B=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device PMOS $2 (S=$5,G=$2,D=OUT,B=VDD) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
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" device NMOS $3 (S=$2,G=IN,D=$4,B=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device NMOS $4 (S=$4,G=$2,D=OUT,B=VSS) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
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" subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);\n"
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" subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);\n"
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" subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);\n"
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" subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);\n"
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"end;\n"
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"circuit TRANS ($1=$1,$2=$2,$3=$3);\n"
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"end;\n"
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);
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// compare the collected test data
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std::string au = tl::testdata ();
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au = tl::combine_path (au, "algo");
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au = tl::combine_path (au, "device_extract_au13_circuits.gds");
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db::compare_layouts (_this, ly, au);
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}
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namespace
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{
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@ -3494,9 +3266,6 @@ public:
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l2n.connect (*rpoly, *rpoly_lbl); // attaches labels
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l2n.connect (*rmetal1, *rmetal1_lbl); // attaches labels
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l2n.connect (*rmetal2, *rmetal2_lbl); // attaches labels
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// Global
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l2n.connect_global (*rbulk, "BULK");
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l2n.connect_global (rptie, "BULK");
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return l2n_p.release ();
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}
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@ -3574,6 +3343,8 @@ public:
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private:
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db::Layout &m_ly;
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db::LayerMap m_lmap;
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public:
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unsigned int nwell;
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unsigned int nwell_lbl;
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unsigned int active;
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@ -3617,6 +3388,78 @@ private:
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}
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TEST(13_JoinNetNames)
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{
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db::Layout ly;
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TestRig test_rig (ly);
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{
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db::LoadLayoutOptions options;
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options.get_options<db::CommonReaderOptions> ().layer_map = test_rig.lmap ();
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options.get_options<db::CommonReaderOptions> ().create_other_layers = false;
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std::string fn (tl::testdata ());
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fn = tl::combine_path (fn, "algo");
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fn = tl::combine_path (fn, "device_extract_l13.gds");
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tl::InputStream stream (fn);
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db::Reader reader (stream);
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reader.read (ly, options);
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}
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std::unique_ptr<db::LayoutToNetlist> l2n (test_rig.make_l2n ());
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// Global
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l2n->connect_global (test_rig.rntie, "VDD");
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l2n->connect_global (*test_rig.rnwell, "VDD");
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l2n->connect_global (test_rig.rptie, "VSS");
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l2n->connect_global (*test_rig.rbulk, "VSS");
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// Extract with joining VSS and VDD
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l2n->join_net_names (tl::GlobPattern ("{VSS,VDD}"));
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l2n->extract_netlist ();
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test_rig.dump_nets (*l2n);
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test_rig.dump_nets_recursive (*l2n);
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// compare netlist as string
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CHECKPOINT ();
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db::compare_netlist (_this, *l2n->netlist (),
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"circuit RINGO ();\n"
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" subcircuit INV2 $1 (IN=$I7,$2=FB,OUT=OSC,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $2 (IN=FB,$2=$I34,OUT=$I17,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $3 (IN=$3,$2=$I38,OUT=$I4,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $4 (IN=$I2,$2=$I37,OUT=$3,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $5 (IN=$I4,$2=$I39,OUT=$I5,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $6 (IN=$I5,$2=$I40,OUT=$I6,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $7 (IN=$I6,$2=$I41,OUT=$I7,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $8 (IN=$I17,$2=$I35,OUT=$I1,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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" subcircuit INV2 $9 (IN=$I1,$2=$I36,OUT=$I2,$4=VSS,$5=VDD,VDD=VDD,VSS=VSS);\n"
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"end;\n"
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"circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5,VDD=VDD,VSS=VSS);\n"
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" device PMOS $1 (S=$2,G=IN,D=$5,B=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device PMOS $2 (S=$5,G=$2,D=OUT,B=VDD) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
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" device NMOS $3 (S=$2,G=IN,D=$4,B=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
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" device NMOS $4 (S=$4,G=$2,D=OUT,B=VSS) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
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" subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);\n"
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" subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);\n"
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" subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);\n"
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" subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);\n"
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"end;\n"
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"circuit TRANS ($1=$1,$2=$2,$3=$3);\n"
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"end;\n"
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);
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|
||||
// compare the collected test data
|
||||
|
||||
std::string au = tl::testdata ();
|
||||
au = tl::combine_path (au, "algo");
|
||||
au = tl::combine_path (au, "device_extract_au13_circuits.gds");
|
||||
|
||||
db::compare_layouts (_this, ly, au);
|
||||
}
|
||||
|
||||
TEST(14_JoinNets)
|
||||
{
|
||||
db::Layout ly;
|
||||
|
|
@ -3638,6 +3481,10 @@ TEST(14_JoinNets)
|
|||
|
||||
std::unique_ptr<db::LayoutToNetlist> l2n (test_rig.make_l2n ());
|
||||
|
||||
// Global
|
||||
l2n->connect_global (*test_rig.rbulk, "BULK");
|
||||
l2n->connect_global (test_rig.rptie, "BULK");
|
||||
|
||||
// Extract while joining VSS with BULK and VDD with NWELL
|
||||
std::set<std::string> jn;
|
||||
jn.insert ("VDD");
|
||||
|
|
|
|||
Loading…
Reference in New Issue