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MERGE: added Spice reader testcase for resistors with model names.

This commit is contained in:
Matthias Koefferlein 2020-04-01 23:19:13 +02:00
parent f5bb371961
commit e56aac2859
2 changed files with 37 additions and 0 deletions
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20
src/db/unit_tests/dbNetlistReaderTests.cc
View File

@ -48,6 +48,26 @@ TEST(1_BasicReader)
);
}
TEST(1b_BasicReader_ResistorModels)
{
db::Netlist nl;
std::string path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nreader1b.cir");
db::NetlistSpiceReader reader;
tl::InputStream is (path);
reader.read (is, nl);
EXPECT_EQ (nl.to_string (),
"circuit TOP ('1'='1','2'='2','4'='4','7'='7');\n"
" device M1 $1 (A='6',B='1') (R=7650,L=0,W=0,A=0,P=0);\n"
" device M2 $2 (A='3',B='1') (R=7650,L=0,W=0,A=0,P=0);\n"
" device M3 $3 (A='3',B='2') (R=2670,L=0,W=0,A=0,P=0);\n"
" device MHVPMOS $4 (S='6',G='4',D='7',B='7') (L=0.25,W=1.5,AS=0.63,AD=0.63,PS=3.84,PD=3.84);\n"
"end;\n"
);
}
TEST(2_ReaderWithSubcircuits)
{
db::Netlist nl;

17
testdata/algo/nreader1b.cir vendored Normal file
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@ -0,0 +1,17 @@
* VDIV netlist before simplification
* cell TOP
.SUBCKT TOP 1 2 4 7
* net 1 OUT
* net 2 GND
* net 4 IN
* net 7 VDD
* device instance $1 1.025,0.335 RES, model M1
R$1 6 1 7650 M1
* device instance $2 2.85,0.335 RES, model M2
R$2 3 1 7650 M2
* device instance $3 4.665,0.335 RES, model M3
R$3 3 2 2670 M3
* device instance $4 1.765,7.485 HVPMOS
M$4 6 4 7 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
.ENDS TOP