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Enhanced documentation for blank_circuit, consilidated 'blank_circuit' method provided which can be used anywhere

This commit is contained in:
Matthias Koefferlein 2021-06-28 19:51:57 +02:00
parent e0ccb4f980
commit dae5d3227a
10 changed files with 821 additions and 16 deletions
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10
src/lay/lay/doc/about/drc_ref_layer.xml
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@ -3334,7 +3334,7 @@ The tile size must be specified with the "tile_size" option:
</p><p>
<pre>
# reports areas where layer 1/0 density is below 10% on 20x20 um tiles
low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um))
low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um))
</pre>
</p><p>
Anisotropic tiles can be specified by giving two values, like "tile_size(10.um, 20.um)".
@ -3348,7 +3348,7 @@ in increments of the tile step:
<pre>
# reports areas where layer 1/0 density is below 10% on 30x30 um tiles
# with a tile step of 20x20 um:
low_density = input(1, 0).density(0.0 .. 0.1, tile_size(30.um), tile_step(20.um))
low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(30.um), tile_step(20.um))
</pre>
</p><p>
For "tile_step", anisotropic values can be given as well by using two values: the first for the
@ -3366,7 +3366,7 @@ drawn boundary layer. To specify a separate, additional layer included in the bo
# reports density of layer 1/0 below 10% on 20x20 um tiles. The layout's boundary is taken from
# layer 0/0:
cell_frame = input(0, 0)
low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um), tile_boundary(cell_frame))
low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um), tile_boundary(cell_frame))
</pre>
</p><p>
Note that the layer given in "tile_boundary" adds to the input layer for computing the bounding box.
@ -3378,7 +3378,7 @@ direction. With the "tile_origin" option this allows full control over the area
<pre>
# reports density of layer 1/0 below 10% on 20x20 um tiles in the region 0,0 .. 2000,3000
# (100 and 150 tiles of 20 um each are used in horizontal and vertical direction):
low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um), tile_origin(0.0, 0.0), tile_count(100, 150))
low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um), tile_origin(0.0, 0.0), tile_count(100, 150))
</pre>
</p><p>
The "padding mode" indicates how the area outside the layout's bounding box is considered.
@ -3392,7 +3392,7 @@ There are two modes:
Example:
</p><p>
<pre>
low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um), padding_ignore)
low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um), padding_ignore)
</pre>
</p><p>
The complementary version of "with_density" is <a href="#without_density">without_density</a>.

9
src/lay/lay/doc/about/lvs_ref_global.xml
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@ -28,6 +28,15 @@ For more details about the DRC functions see <a href="/about/drc_ref_global.xml"
<p>
See <a href="/about/lvs_ref_netter.xml#align">Netter#align</a> for a description of that function.
</p>
<a name="blank_circuit"/><h2>"blank_circuit" - Removes the content from the given circuits (blackboxing)</h2>
<keyword name="blank_circuit"/>
<p>Usage:</p>
<ul>
<li><tt>blank_circuit(circuit_filter)</tt></li>
</ul>
<p>
See <a href="/about/lvs_ref_netter.xml#blank_circuit">Netter#blank_circuit</a> for a description of that function.
</p>
<a name="compare"/><h2>"compare" - Compares the extracted netlist vs. the schematic</h2>
<keyword name="compare"/>
<p>Usage:</p>

28
src/lay/lay/doc/about/lvs_ref_netter.xml
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@ -68,6 +68,34 @@ are other (explicit) ways to flatten circuits.
Please note that flattening circuits has some side effects such
as loss of details in the cross reference and net layout.
</p>
<a name="blank_circuit"/><h2>"blank_circuit" - Removes the content from the given circuits (blackboxing)</h2>
<keyword name="blank_circuit"/>
<p>Usage:</p>
<ul>
<li><tt>blank_circuit(circuit_filter)</tt></li>
</ul>
<p>
This method will erase all content from the circuits matching the filter.
The filter is a glob expression.
</p><p>
This has the following effects:
</p><p>
<ul>
<li>The circuits are no longer compared against each other </li>
<li>Named pins are required to match (use labels on the nets to name pins in the layout) </li>
<li>Unnamed pins are treated as equivalent and can be swapped </li>
<li>The selected circuits will not be purged on netlist simplification </li>
</ul>
</p><p>
Using this method can be useful to reduce the verification overhead for
blocks which are already verifified by other ways or for which no schematic
is available - e.g. hard macros.
</p><p>
<pre>
# skips all MEMORY* circuits from compare
blank_circuit("MEMORY*")
</pre>
</p>
<a name="compare"/><h2>"compare" - Compares the extracted netlist vs. the schematic</h2>
<keyword name="compare"/>
<p>Usage:</p>

31
src/lay/lay/doc/manual/lvs_tweaks.xml
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@ -153,10 +153,11 @@
<p>
A useful method in this context is the "blank_circuit" method. It clears
a circuit's innards and leaves only the pins. You can use this method to
ensure abstracts in both the layout netlist and the schematic. After this,
a circuit's innards from a netlist. After this,
the compare algorithm will identify both circuits as identical, provided
they feature the same number of pins.
they feature the same number of pins. Named pins are required to match exactly
unless declared equivalent. Unnamed pins are treated as equivalent. To name
pins use labels on the pin's nets inside the circuit's layout.
</p>
<p>
@ -166,14 +167,20 @@
<pre>netlist.blank_circuit("CIRCUIT_NAME")
schematic.blank_circuit("CIRCUIT_NAME")</pre>
<p><b>NOTE:</b> In this version, use "blank_circuit" before "purge" or "simplify" (see below). "blank_circuit"
sets a flag (<class_doc href="Circuit#dont_purge"/>) which prevents purging of abstract circuits.</p>
<p>
The argument to "blank_circuit" is a glob pattern (shell-like).
For example, "MEMORY*" will blank out all circuits starting with "MEMORY".
There is a short form for this too (<a href="/about/lvs_ref_netter.xml#blank_circuit">blank_circuit</a>).
In contrast to netlist-based "blank_circuit", this method can be used anywhere in the LVS script:
</p>
<p><b>NOTE:</b> Use "blank_circuit" before "purge" or "simplify" (see below). This method
sets a flag (<class_doc href="Circuit#dont_purge"/>) which prevents purging of abstract
circuits.</p>
<pre>blank_circuit("CIRCUIT_NAME")</pre>
<p>
The argument to "blank_circuit" in both cases is a glob pattern (shell-like).
For example, "MEMORY*" will blank out all circuits starting with the word "MEMORY".
</p>
<h2>Joining of symmetric nodes</h2>
@ -201,8 +208,8 @@ schematic.blank_circuit("CIRCUIT_NAME")</pre>
</p>
<p>
KLayout provides a feature which will add such connections after extraction
of the netlist:
KLayout provides a feature (<a href="/about/lvs_ref_netter.xml#join_symmetric_nets">join_symmetric_nets</a>)
which will add such connections after extraction of the netlist:
</p>
<pre>join_symmetric_nets("NAND2")</pre>
@ -221,6 +228,10 @@ schematic.blank_circuit("CIRCUIT_NAME")</pre>
need it.
</p>
<p>
"join_symmetric_nets" can be used anywhere in the LVS script.
</p>
<h2>Purging (elimination of redundancy)</h2>
<p>

8
src/lvs/lvs/built-in-macros/_lvs_engine.rb
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@ -100,6 +100,12 @@ module LVS
# @synopsis join_symmetric_nets(circuit_filter)
# See \Netter#join_symmetric_nets for a description of that function.
# %LVS%
# @name blank_circuit
# @brief Removes the content from the given circuits (blackboxing)
# @synopsis blank_circuit(circuit_filter)
# See \Netter#blank_circuit for a description of that function.
# %LVS%
# @name align
# @brief Aligns the extracted netlist vs. the schematic by flattening circuits where required
@ -168,7 +174,7 @@ module LVS
# @synopsis tolerance(device_class_name, parameter_name [, :absolute => absolute_tolerance] [, :relative => relative_tolerance])
# See \Netter#tolerance for a description of that function.
%w(schematic compare join_symmetric_nets tolerance align same_nets same_circuits same_device_classes equivalent_pins min_caps max_res max_depth max_branch_complexity consider_net_names).each do |f|
%w(schematic compare join_symmetric_nets tolerance blank_circuit align same_nets same_circuits same_device_classes equivalent_pins min_caps max_res max_depth max_branch_complexity consider_net_names).each do |f|
eval <<"CODE"
def #{f}(*args)
_netter.#{f}(*args)

49
src/lvs/lvs/built-in-macros/_lvs_netter.rb
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@ -283,6 +283,55 @@ module LVS
end
# %LVS%
# @name blank_circuit
# @brief Removes the content from the given circuits (blackboxing)
# @synopsis blank_circuit(circuit_filter)
# This method will erase all content from the circuits matching the filter.
# The filter is a glob expression.
#
# This has the following effects:
#
# @ul
# @li The circuits are no longer compared (netlist vs. schematic) @/li
# @li Named pins are required to match (use labels on the nets to name pins in the layout) @/li
# @li Unnamed pins are treated as equivalent and can be swapped @/li
# @li The selected circuits will not be purged on netlist simplification @/li
# @/ul
#
# Using this method can be useful to reduce the verification overhead for
# blocks which are already verifified by other ways or for which no schematic
# is available - e.g. hard macros.
#
# Example:
#
# @code
# # skips all MEMORY* circuits from compare
# blank_circuit("MEMORY*")
# @/code
def blank_circuit(circuit_pattern)
circuit_pattern.is_a?(String) || raise("Circuit pattern argument of 'blank_circuit' must be a string")
if self._l2n_data
# already extracted
self._blank_circuit(self._l2n_data, circuit_pattern)
else
@post_extract_config << lambda { |l2n| self._blank_circuit(l2n, circuit_pattern) }
end
end
def _blank_circuit(l2n, circuit_pattern)
(n, s) = _ensure_two_netlists
n.blank_circuit(circuit_pattern)
s.blank_circuit(circuit_pattern)
end
def _comparer
comparer = RBA::NetlistComparer::new

5
src/lvs/unit_tests/lvsSimpleTests.cc
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@ -135,6 +135,11 @@ TEST(9_blackboxing)
run_test (_this, "ringo_simple_blackboxing", "ringo_for_blackboxing.gds");
}
TEST(9b_blackboxing_netter)
{
run_test (_this, "ringo_simple_blackboxing_netter", "ringo_for_blackboxing.gds");
}
TEST(10_simplification_with_align)
{
run_test (_this, "ringo_simple_simplification_with_align", "ringo_for_simplification.gds");

70
testdata/lvs/ringo_simple_blackboxing_netter.cir vendored Normal file
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@ -0,0 +1,70 @@
* Extracted by KLayout
* cell RINGO
* pin FB
* pin VDD
* pin OUT
* pin ENABLE
* pin VSS
.SUBCKT RINGO 5 6 7 8 9
* net 5 FB
* net 6 VDD
* net 7 OUT
* net 8 ENABLE
* net 9 VSS
* cell instance $1 r0 *1 1.8,0
X$1 6 1 9 6 5 8 9 ND2X1
* cell instance $2 r0 *1 4.2,0
X$2 6 2 9 6 1 9 INVX1
* cell instance $3 r0 *1 6,0
X$3 6 10 9 6 2 9 INVX1
* cell instance $4 r0 *1 16.8,0
X$4 6 3 9 6 11 9 INVX1
* cell instance $5 r0 *1 18.6,0
X$5 6 4 9 6 3 9 INVX1
* cell instance $6 r0 *1 20.4,0
X$6 6 5 9 6 4 9 INVX1
* cell instance $7 r0 *1 22.2,0
X$7 5 6 7 9 6 9 INVX2
* cell instance $17 r0 *1 7.8,0
X$17 6 12 9 6 10 9 INVX1
* cell instance $18 r0 *1 9.6,0
X$18 6 13 9 6 12 9 INVX1
* cell instance $19 r0 *1 11.4,0
X$19 6 14 9 6 13 9 INVX1
* cell instance $20 r0 *1 13.2,0
X$20 6 15 9 6 14 9 INVX1
* cell instance $21 r0 *1 15,0
X$21 6 11 9 6 15 9 INVX1
.ENDS RINGO
* cell INVX2
* pin IN
* pin VDD
* pin OUT
* pin VSS
* pin
* pin BULK
.SUBCKT INVX2 1 2 3 4 5 6
.ENDS INVX2
* cell INVX1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin IN
* pin BULK
.SUBCKT INVX1 1 2 3 4 5 6
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin BULK
.SUBCKT ND2X1 1 2 3 4 5 6 7
.ENDS ND2X1

87
testdata/lvs/ringo_simple_blackboxing_netter.lvs vendored Normal file
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@ -0,0 +1,87 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("ringo_for_blackboxing.cir")
blank_circuit("INVX1")
blank_circuit("INVX2")
blank_circuit("ND2X1")
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
pplus = input(3, 0)
nplus = input(4, 0)
poly = input(5, 0)
contact = input(8, 0)
metal1 = input(9, 0)
via1 = input(10, 0)
metal2 = input(11, 0)
# Bulk layer for terminal provisioning
# and to provide the BULK labels for
# the abstracts
bulk = labels(13, 0)
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
pgate = pactive & poly
psd = pactive - pgate
ntie = active_in_nwell & nplus
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ngate = nactive & poly
nsd = nactive - ngate
ptie = active_outside_nwell & pplus
# Device extraction
# PMOS transistor device extraction
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
# NMOS transistor device extraction
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
# Define connectivity for netlist extraction
# Inter-layer
connect(psd, contact)
connect(nsd, contact)
connect(poly, contact)
connect(ntie, contact)
connect(nwell, ntie)
connect(ptie, contact)
connect(contact, metal1)
connect(metal1, via1)
connect(via1, metal2)
# Global
connect_global(bulk, "SUBSTRATE")
connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.flatten_circuit("INVCHAIN")
netlist.make_top_level_pins
netlist.purge
netlist.combine_devices
netlist.purge_nets
consider_net_names(false)
compare

540
testdata/lvs/ringo_simple_blackboxing_netter.lvsdb vendored Normal file
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@ -0,0 +1,540 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7 '13/0')
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 250) (2600 7750))
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin()
pin(name(B))
pin(name(A))
pin(name(BULK))
)
circuit(INVX1
# Circuit boundary
rect((-100 250) (2000 7750))
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin()
pin(name(IN))
pin(name(BULK))
)
circuit(INVX2
# Circuit boundary
rect((-100 250) (2600 7750))
# Outgoing pins and their connections to nets
pin(name(IN))
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin()
pin(name(BULK))
)
circuit(RINGO
# Circuit boundary
rect((600 250) (25800 7750))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (610 300))
)
net(2
rect(l11 (5550 2950) (900 300))
)
net(3
rect(l11 (18150 2950) (900 300))
)
net(4
rect(l11 (19950 2950) (900 300))
)
net(5 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(6 name(VDD)
rect(l3 (1100 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-22341 859) (2 2))
rect(l11 (-1751 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-24850 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(7 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(8 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(9 name(VSS)
rect(l8 (1710 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-22341 -391) (2 2))
rect(l11 (-1301 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l10 (-24850 -800) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
net(10
rect(l11 (7350 2950) (900 300))
)
net(11
rect(l11 (16350 2950) (900 300))
)
net(12
rect(l11 (9150 2950) (900 300))
)
net(13
rect(l11 (10950 2950) (900 300))
)
net(14
rect(l11 (12750 2950) (900 300))
)
net(15
rect(l11 (14550 2950) (900 300))
)
# Outgoing pins and their connections to nets
pin(5 name(FB))
pin(6 name(VDD))
pin(7 name(OUT))
pin(8 name(ENABLE))
pin(9 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 6)
pin(1 1)
pin(2 9)
pin(3 6)
pin(4 5)
pin(5 8)
pin(6 9)
)
circuit(2 INVX1 location(4200 0)
pin(0 6)
pin(1 2)
pin(2 9)
pin(3 6)
pin(4 1)
pin(5 9)
)
circuit(3 INVX1 location(6000 0)
pin(0 6)
pin(1 10)
pin(2 9)
pin(3 6)
pin(4 2)
pin(5 9)
)
circuit(4 INVX1 location(16800 0)
pin(0 6)
pin(1 3)
pin(2 9)
pin(3 6)
pin(4 11)
pin(5 9)
)
circuit(5 INVX1 location(18600 0)
pin(0 6)
pin(1 4)
pin(2 9)
pin(3 6)
pin(4 3)
pin(5 9)
)
circuit(6 INVX1 location(20400 0)
pin(0 6)
pin(1 5)
pin(2 9)
pin(3 6)
pin(4 4)
pin(5 9)
)
circuit(7 INVX2 location(22200 0)
pin(0 5)
pin(1 6)
pin(2 7)
pin(3 9)
pin(4 6)
pin(5 9)
)
circuit(17 INVX1 location(7800 0)
pin(0 6)
pin(1 12)
pin(2 9)
pin(3 6)
pin(4 10)
pin(5 9)
)
circuit(18 INVX1 location(9600 0)
pin(0 6)
pin(1 13)
pin(2 9)
pin(3 6)
pin(4 12)
pin(5 9)
)
circuit(19 INVX1 location(11400 0)
pin(0 6)
pin(1 14)
pin(2 9)
pin(3 6)
pin(4 13)
pin(5 9)
)
circuit(20 INVX1 location(13200 0)
pin(0 6)
pin(1 15)
pin(2 9)
pin(3 6)
pin(4 14)
pin(5 9)
)
circuit(21 INVX1 location(15000 0)
pin(0 6)
pin(1 11)
pin(2 9)
pin(3 6)
pin(4 15)
pin(5 9)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin(name(NWELL))
pin(name(B))
pin(name(A))
pin(name(BULK))
)
circuit(INVX1
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin(name(NWELL))
pin(name(IN))
pin(name(BULK))
)
circuit(INVX2
# Outgoing pins and their connections to nets
pin(name(VDD))
pin(name(OUT))
pin(name(VSS))
pin(name(NWELL))
pin(name(IN))
pin(name(BULK))
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX2 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(0 0 match)
pin(2 2 match)
)
)
circuit(INVX2 INVX2 match
xref(
pin(4 3 match)
pin(5 5 match)
pin(0 4 match)
pin(2 1 match)
pin(1 0 match)
pin(3 2 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(6 6 match)
pin(1 1 match)
pin(0 0 match)
pin(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(4 15 match)
net(2 7 match)
net(10 8 match)
net(12 9 match)
net(13 10 match)
net(14 11 match)
net(15 12 match)
net(11 13 match)
net(3 14 match)
net(8 4 match)
net(5 3 match)
net(7 5 match)
net(6 2 match)
net(9 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(17 4 match)
circuit(18 5 match)
circuit(19 6 match)
circuit(20 7 match)
circuit(21 8 match)
circuit(4 9 match)
circuit(5 10 match)
circuit(6 11 match)
circuit(7 12 match)
circuit(1 1 match)
)
)
)