Bug fixes, adjusted test data

src/db/db/dbNetlistSpiceReaderDelegate.cc

@@ -87,6 +87,7 @@ static std::string unescape_name (const std::string &n)
 // ------------------------------------------------------------------------------------------------------
 
 NetlistSpiceReaderDelegate::NetlistSpiceReaderDelegate ()
+  : mp_netlist (0)
 {
   //  .. nothing yet ..
 }
@@ -195,7 +196,7 @@ void NetlistSpiceReaderDelegate::parse_element_components (const std::string &s,
       if (ex.try_read_word (n) && ex.test ("=")) {
 
         //  a parameter
-        pv [mp_netlist ? mp_netlist->normalize_name (n) : n] = read_value (ex, variables);
+        pv [mp_netlist ? mp_netlist->normalize_name (n) : tl::to_upper_case (n)] = read_value (ex, variables);
 
       } else {
 
@@ -206,10 +207,7 @@ void NetlistSpiceReaderDelegate::parse_element_components (const std::string &s,
         }
 
         std::string comp_name = parse_component (ex);
-
+        comp_name = mp_netlist ? mp_netlist->normalize_name (comp_name) : tl::to_upper_case (comp_name);
-        if (mp_netlist) {
-          comp_name = mp_netlist->normalize_name (comp_name);
-        }
 
         //  resolve variables if string type
         auto v = variables.find (comp_name);

src/tl/tl/tlVariant.cc

@@ -1060,7 +1060,7 @@ static const double epsilon = 1e-13;
 static inline bool fequal (double a, double b)
 {
   double avg = 0.5 * (fabs (a) + fabs (b));
-  return fabs (a - b) < epsilon * avg;
+  return fabs (a - b) <= epsilon * avg;
 }
 
 static inline bool fless (double a, double b)

src/tl/unit_tests/tlVariantTests.cc

@@ -1063,6 +1063,8 @@ TEST(5)
 TEST(6)
 {
   volatile double a = 10.0;
+  EXPECT_EQ (tl::Variant (0.0) == tl::Variant (0.0), true);
+
   EXPECT_EQ (tl::Variant (0.1) == tl::Variant (1.0 / a), true);
   EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 1e-14)), true);
   EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 0.9e-13)), true);

testdata/algo/lvs_test2_au.lvsdb.1

@@ -497,6 +497,37 @@ reference(
    pin(5 1)
   )
 
+ )
+ circuit(INV2PAIRX
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
  )
  circuit(RINGO
 
@@ -567,37 +598,6 @@ reference(
   )
 
  )
- circuit(INV2PAIRX
-
-  # Nets
-  net(1 name('1'))
-  net(2 name('2'))
-  net(3 name('3'))
-  net(4 name('4'))
-  net(5 name('5'))
-  net(6 name('6'))
-  net(7 name('7'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name('1'))
-  pin(2 name('2'))
-  pin(3 name('3'))
-  pin(4 name('4'))
-  pin(5 name('5'))
-  pin(6 name('6'))
-  pin(7 name('7'))
-
-  # Subcircuits and their connections
-  circuit(1 INV2 name($2)
-   pin(0 7)
-   pin(1 4)
-   pin(2 6)
-   pin(3 3)
-   pin(4 2)
-   pin(5 1)
-  )
-
- )
 )
 
 # Cross reference

testdata/algo/lvs_test2_au.lvsdb.2

@@ -497,6 +497,37 @@ reference(
    pin(5 1)
   )
 
+ )
+ circuit(INV2PAIRX
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
  )
  circuit(RINGO
 
@@ -567,37 +598,6 @@ reference(
   )
 
  )
- circuit(INV2PAIRX
-
-  # Nets
-  net(1 name('1'))
-  net(2 name('2'))
-  net(3 name('3'))
-  net(4 name('4'))
-  net(5 name('5'))
-  net(6 name('6'))
-  net(7 name('7'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name('1'))
-  pin(2 name('2'))
-  pin(3 name('3'))
-  pin(4 name('4'))
-  pin(5 name('5'))
-  pin(6 name('6'))
-  pin(7 name('7'))
-
-  # Subcircuits and their connections
-  circuit(1 INV2 name($2)
-   pin(0 7)
-   pin(1 4)
-   pin(2 6)
-   pin(3 3)
-   pin(4 2)
-   pin(5 1)
-  )
-
- )
 )
 
 # Cross reference

testdata/algo/lvs_test2b_au.lvsdb.1

@@ -497,6 +497,37 @@ reference(
    pin(5 1)
   )
 
+ )
+ circuit(INV2PAIRX
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
  )
  circuit(RINGO
 
@@ -567,37 +598,6 @@ reference(
   )
 
  )
- circuit(INV2PAIRX
-
-  # Nets
-  net(1 name('1'))
-  net(2 name('2'))
-  net(3 name('3'))
-  net(4 name('4'))
-  net(5 name('5'))
-  net(6 name('6'))
-  net(7 name('7'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name('1'))
-  pin(2 name('2'))
-  pin(3 name('3'))
-  pin(4 name('4'))
-  pin(5 name('5'))
-  pin(6 name('6'))
-  pin(7 name('7'))
-
-  # Subcircuits and their connections
-  circuit(1 INV2 name($2)
-   pin(0 7)
-   pin(1 4)
-   pin(2 6)
-   pin(3 3)
-   pin(4 2)
-   pin(5 1)
-  )
-
- )
 )
 
 # Cross reference

testdata/algo/lvs_test2b_au.lvsdb.2

@@ -497,6 +497,37 @@ reference(
    pin(5 1)
   )
 
+ )
+ circuit(INV2PAIRX
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
  )
  circuit(RINGO
 
@@ -567,37 +598,6 @@ reference(
   )
 
  )
- circuit(INV2PAIRX
-
-  # Nets
-  net(1 name('1'))
-  net(2 name('2'))
-  net(3 name('3'))
-  net(4 name('4'))
-  net(5 name('5'))
-  net(6 name('6'))
-  net(7 name('7'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name('1'))
-  pin(2 name('2'))
-  pin(3 name('3'))
-  pin(4 name('4'))
-  pin(5 name('5'))
-  pin(6 name('6'))
-  pin(7 name('7'))
-
-  # Subcircuits and their connections
-  circuit(1 INV2 name($2)
-   pin(0 7)
-   pin(1 4)
-   pin(2 6)
-   pin(3 3)
-   pin(4 2)
-   pin(5 1)
-  )
-
- )
 )
 
 # Cross reference

testdata/lvs/ringo_simple_dummy_device.lvsdb.1

@@ -609,8 +609,8 @@ layout(
 reference(
 
  # Device class section
- class(NMOS MOS4)
  class(PMOS MOS4)
+ class(NMOS MOS4)
 
  # Circuit section
  # Circuits are the hierarchical building blocks of the netlist.

testdata/lvs/ringo_simple_dummy_device.lvsdb.2

@@ -609,8 +609,8 @@ layout(
 reference(
 
  # Device class section
- class(NMOS MOS4)
  class(PMOS MOS4)
+ class(NMOS MOS4)
 
  # Circuit section
  # Circuits are the hierarchical building blocks of the netlist.

testdata/ruby/dbNetlistReaderTests.rb

@@ -116,6 +116,9 @@ class DBNetlistReaderTests_TestClass < TestBase
     assert_equal(nl.description, "Read by MyDelegate (sucessfully)")
 
     assert_equal(nl.to_s, <<"END")
+circuit .TOP ();
+  subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS);
+end;
 circuit SUBCKT ($1=$1,A=A,VDD=VDD,Z=Z,GND=GND,GND$1=GND$1);
   device HVPMOS $1 (S=VDD,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);
   device HVPMOS $2 (S=VDD,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);
@@ -124,9 +127,6 @@ circuit SUBCKT ($1=$1,A=A,VDD=VDD,Z=Z,GND=GND,GND$1=GND$1);
   device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);
   device RES $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0);
 end;
-circuit .TOP ();
-  subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS);
-end;
 END
 
   end
@@ -147,6 +147,9 @@ END
     assert_equal(nl.description, "Read by MyDelegate2 (sucessfully)")
 
     assert_equal(nl.to_s, <<"END")
+circuit .TOP ();
+  subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VXX=VXX,Z=Z,GND=VSS,GND$1=VSS);
+end;
 circuit SUBCKT ($1=$1,A=A,VXX=VXX,Z=Z,GND=GND,GND$1=GND$1);
   device HVPMOS $1 (S=VXX,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);
   device HVPMOS $2 (S=VXX,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);
@@ -155,9 +158,6 @@ circuit SUBCKT ($1=$1,A=A,VXX=VXX,Z=Z,GND=GND,GND$1=GND$1);
   device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);
   device WIDERSTAND $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0);
 end;
-circuit .TOP ();
-  subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VXX=VXX,Z=Z,GND=VSS,GND$1=VSS);
-end;
 END
 
   end
@@ -212,7 +212,7 @@ END
     pd.net_names = [ "x", "y", "z" ]
     assert_equal(pd.net_names.join(","), "x,y,z")
     pd.parameters = { "A" => 17.5, "B" => 1 }
-    assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1.0}")
+    assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1}")
 
   end
 
@@ -222,7 +222,7 @@ END
     pd.strings = [ "x", "y", "z" ]
     assert_equal(pd.strings.join(","), "x,y,z")
     pd.parameters = { "A" => 17.5, "B" => 1 }
-    assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1.0}")
+    assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1}")
 
   end
 
@@ -230,7 +230,7 @@ END
 
     dg = RBA::NetlistSpiceReaderDelegate::new
     pd = dg.parse_element_components("17 5 1e-9 a=17 b=1k")
-    assert_equal(pd.strings.join(","), "17,5,1e-9")
+    assert_equal(pd.strings.join(","), "17,5,1E-9")
     assert_equal(pd.parameters.inspect, "{\"A\"=>17.0, \"B\"=>1000.0}")
 
   end