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WIP: reverted modifications on SPICE reader.

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This commit is contained in:
Matthias Koefferlein
2019-07-08 21:51:59 +02:00
parent 9625caea65
commit bdb8a7bcc2
2 changed files with 4 additions and 4 deletions
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testdata/lvs/vexriscv.lvs
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+2 -2
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@@ -87,8 +87,8 @@ connect_implicit("VSS")
netlist.flatten_circuit("*_{x0,x1,x2,x4}")
same_device_classes("PMOS", "tp")
same_device_classes("NMOS", "tn")
same_device_classes("PMOS", "TP")
same_device_classes("NMOS", "TN")
# Ignore all caps from the schematic
same_device_classes(nil, "CAP")