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https://github.com/KLayout/klayout.git
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Netlist compare enhancement
This enhancement targets towards a better resolution of ambiguities. The enhancement is to utilize knowledge about device and subcircuit equivalences to avoid stale branches of the ambiguity resolution tree. So far following these branches could lead to a contradictions which render an ambiguitiy resolution choice useless. One effect of this change is enhanced reproducibility of the matching log because some pointers are not involved anymore.
This commit is contained in:
Matthias Koefferlein
+960
-327
File diff suppressed because it is too large
Load Diff
@@ -38,6 +38,8 @@ class DeviceCategorizer;
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class CircuitCategorizer;
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class CircuitMapper;
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class NetGraph;
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class SubCircuitEquivalenceTracker;
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class DeviceEquivalenceTracker;
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/**
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* @brief A receiver for netlist compare events
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@@ -285,6 +287,26 @@ public:
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return m_max_n_branch;
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}
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/**
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* @brief Sets a value indicating depth-first traversal
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*
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* With depth first (the default), the algorithm looks for further identities before moving to another
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* node. With breadth first (false), the algorithm will work in "waves" rather than digging deerly
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* into the direction of a node.
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*/
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void set_depth_first (bool df)
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{
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m_depth_first = df;
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}
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/**
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* @brief Gets a value indicating depth-first traversal
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*/
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bool depth_first () const
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{
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return m_depth_first;
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}
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/**
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* @brief Gets the list of circuits without matching circuit in the other netlist
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* The result can be used to flatten these circuits prior to compare.
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@@ -326,8 +348,8 @@ protected:
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bool all_subcircuits_verified (const db::Circuit *c, const std::set<const db::Circuit *> &verified_circuits) const;
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static void derive_pin_equivalence (const db::Circuit *ca, const db::Circuit *cb, CircuitPinMapper *circuit_pin_mapper);
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void do_pin_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, std::map<const db::Circuit *, CircuitMapper> &c12_circuit_and_pin_mapping, std::map<const db::Circuit *, CircuitMapper> &c22_circuit_and_pin_mapping, bool &pin_mismatch, bool &good) const;
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void do_device_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, const db::DeviceFilter &device_filter, DeviceCategorizer &device_categorizer, bool &good) const;
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void do_subcircuit_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, CircuitCategorizer &circuit_categorizer, const db::CircuitPinMapper &circuit_pin_mapper, std::map<const db::Circuit *, CircuitMapper> &c12_circuit_and_pin_mapping, std::map<const db::Circuit *, CircuitMapper> &c22_circuit_and_pin_mapping, bool &good) const;
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void do_device_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, const db::DeviceFilter &device_filter, DeviceCategorizer &device_categorizer, db::DeviceEquivalenceTracker &device_eq, bool &good) const;
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void do_subcircuit_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, CircuitCategorizer &circuit_categorizer, const db::CircuitPinMapper &circuit_pin_mapper, std::map<const db::Circuit *, CircuitMapper> &c12_circuit_and_pin_mapping, std::map<const db::Circuit *, CircuitMapper> &c22_circuit_and_pin_mapping, db::SubCircuitEquivalenceTracker &subcircuit_eq, bool &good) const;
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bool handle_pin_mismatch (const NetGraph &g1, const db::Circuit *c1, const db::Pin *pin1, const NetGraph &g2, const db::Circuit *c2, const db::Pin *p2) const;
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mutable NetlistCompareLogger *mp_logger;
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@@ -339,6 +361,7 @@ protected:
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double m_res_threshold;
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size_t m_max_n_branch;
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size_t m_max_depth;
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bool m_depth_first;
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bool m_dont_consider_net_names;
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};
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@@ -1147,8 +1147,8 @@ TEST(5_BufferTwoPathsDifferentDeviceClasses)
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"begin_circuit BUF BUF\n"
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"match_nets INT $10\n"
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"match_nets IN IN\n"
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"net_mismatch OUT OUT\n"
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"net_mismatch INT2 $11\n"
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"net_mismatch OUT OUT\n"
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"match_pins $0 $1\n"
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"match_pins $1 $3\n"
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"match_pins $2 $0\n"
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@@ -1212,8 +1212,35 @@ TEST(6_BufferTwoPathsAdditionalResistor)
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"begin_circuit BUF BUF\n"
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"net_mismatch INT $10\n"
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"match_nets IN IN\n"
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"net_mismatch INT2 $11\n"
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"match_nets OUT OUT\n"
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"match_pins $0 $1\n"
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"match_pins $1 $3\n"
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"match_pins $2 $0\n"
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"match_pins $3 $2\n"
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"match_devices $1 $1\n"
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"match_devices $3 $2\n"
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"match_devices $5 $3\n"
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"match_devices $7 $4\n"
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"match_devices $2 $5\n"
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"match_devices $4 $6\n"
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"match_devices $6 $7\n"
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"match_devices $8 $8\n"
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"device_mismatch (null) $9\n"
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"end_circuit BUF BUF NOMATCH"
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);
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EXPECT_EQ (good, false);
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comp.set_depth_first (false);
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logger.clear ();
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good = comp.compare (&nl1, &nl2);
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EXPECT_EQ (logger.text (),
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"begin_circuit BUF BUF\n"
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"net_mismatch INT $10\n"
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"match_nets OUT OUT\n"
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"net_mismatch INT2 $11\n"
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"match_nets IN IN\n"
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"match_pins $0 $1\n"
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"match_pins $1 $3\n"
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"match_pins $2 $0\n"
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@@ -1274,9 +1301,9 @@ TEST(6_BufferTwoPathsAdditionalDevices)
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"match_nets INT $11\n"
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"net_mismatch VDD VDD\n"
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"match_nets IN IN\n"
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"net_mismatch INT2 $10\n"
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"net_mismatch VSS VSS\n"
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"net_mismatch OUT OUT\n"
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"net_mismatch INT2 $10\n"
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"match_pins $0 $1\n"
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"match_pins $1 $3\n"
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"match_pins $2 $0\n"
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@@ -2552,8 +2579,8 @@ TEST(17_InherentlyAmbiguousDecoder)
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"match_ambiguous_nets NQ1 NQ1\n"
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"match_ambiguous_nets NQ2 NQ2\n"
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"match_nets NQ3 NQ3\n"
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"match_ambiguous_nets NA NA\n"
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"match_ambiguous_nets NB NB\n"
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"match_nets NA NA\n"
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"match_nets NB NB\n"
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"match_nets B B\n"
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"match_nets A A\n"
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"match_pins $0 $1\n"
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@@ -2657,10 +2684,61 @@ TEST(17_InherentlyAmbiguousDecoder)
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"match_nets B B\n"
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"match_nets NB NB\n"
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"match_nets NA NA\n"
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"match_nets NQ0 NQ0\n"
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"match_nets NQ2 NQ2\n"
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"match_nets NQ1 NQ1\n"
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"match_nets NQ3 NQ3\n"
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"match_nets NQ2 NQ2\n"
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"match_nets NQ0 NQ0\n"
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"match_pins $0 $1\n"
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"match_pins $1 $0\n"
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"match_pins $2 $2\n"
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"match_pins $3 $3\n"
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"match_pins $4 $4\n"
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"match_pins $5 $5\n"
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"match_pins $6 $6\n"
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"match_pins $7 $7\n"
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"match_subcircuits $1 $1\n"
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"match_subcircuits $2 $2\n"
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"match_subcircuits $4 $3\n"
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"match_subcircuits $6 $4\n"
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"match_subcircuits $3 $5\n"
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"match_subcircuits $5 $6\n"
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"end_circuit DECODER DECODER MATCH"
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);
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EXPECT_EQ (good, true);
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comp.set_depth_first (false);
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logger.clear ();
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good = comp.compare (&nl1, &nl2);
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EXPECT_EQ (logger.text (),
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"begin_circuit NAND NAND\n"
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"match_nets VSS VSS\n"
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"match_nets INT INT\n"
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"match_nets OUT OUT\n"
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"match_nets VDD VDD\n"
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"match_nets B B\n"
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"match_nets A A\n"
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"match_pins $0 $0\n"
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"match_pins $1 $1\n"
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"match_pins $2 $2\n"
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"match_pins $3 $3\n"
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"match_pins $4 $4\n"
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"match_devices $1 $1\n"
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"match_devices $2 $2\n"
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"match_devices $3 $3\n"
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"match_devices $4 $4\n"
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"end_circuit NAND NAND MATCH\n"
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"begin_circuit DECODER DECODER\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_nets NA NA\n"
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"match_nets NB NB\n"
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"match_nets B B\n"
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"match_nets NQ1 NQ1\n"
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"match_nets NQ3 NQ3\n"
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"match_nets NQ2 NQ2\n"
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"match_nets NQ0 NQ0\n"
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"match_pins $0 $1\n"
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"match_pins $1 $0\n"
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"match_pins $2 $2\n"
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@@ -2794,6 +2872,67 @@ TEST(18_ClockTree)
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"end_circuit TXEE TXEE MATCH"
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);
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EXPECT_EQ (good, true);
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comp.set_depth_first (false);
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logger.clear ();
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good = comp.compare (&nl1, &nl2);
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txt = logger.text ();
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// because L/R matching is ambiguous, we need to do this to
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// establish reproducability on different platforms:
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txt = tl::replaced (txt, "L", "X");
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txt = tl::replaced (txt, "R", "X");
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EXPECT_EQ (txt,
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"begin_circuit INV INV\n"
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"match_nets VDD VDD\n"
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"match_nets OUT OUT\n"
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"match_nets IN IN\n"
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"match_nets VSS VSS\n"
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"match_pins IN IN\n"
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"match_pins OUT OUT\n"
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"match_pins VDD VDD\n"
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"match_pins VSS VSS\n"
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"match_devices $1 $1\n"
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"match_devices $2 $2\n"
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"end_circuit INV INV MATCH\n"
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"begin_circuit TXEE TXEE\n"
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"match_nets IN IN\n"
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"match_nets VSS VSS\n"
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"match_nets VDD VDD\n"
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"match_nets S S\n"
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"match_ambiguous_nets SX SX\n"
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"match_ambiguous_nets SX SX\n"
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"match_ambiguous_nets SXX SXX\n"
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"match_ambiguous_nets SXX SXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_ambiguous_nets SXX SXX\n"
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"match_ambiguous_nets SXX SXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_ambiguous_nets SXXX SXXX\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits TX TX\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits TXX TXX\n"
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"match_subcircuits TXX TXX\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits T T\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits TX TX\n"
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"match_subcircuits TXX TXX\n"
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"match_subcircuits TXXX TXXX\n"
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"match_subcircuits TXX TXX\n"
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"end_circuit TXEE TXEE MATCH"
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);
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EXPECT_EQ (good, true);
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}
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TEST(19_SymmetricCircuit)
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@@ -2922,24 +3061,123 @@ TEST(19_SymmetricCircuit)
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"match_nets g1 G1\n"
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"match_nets $44 YI\n"
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"match_nets $14 WELL\n"
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"match_nets $8 NET215\n"
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"match_nets $9 NET175\n"
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"match_nets $6 NET181\n"
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"match_nets $4 NET200\n"
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"match_nets nn1 NN1\n"
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"match_nets $11 CS0\n"
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"match_nets $13 CS1\n"
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"match_nets nn2 NN2\n"
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"match_nets nn2_ NN2_\n"
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"match_nets q0 Q0\n"
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"match_nets q1 Q1\n"
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"match_ambiguous_nets q0 Q0\n"
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"match_ambiguous_nets q1 Q1\n"
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"match_nets $11 CS0\n"
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"match_nets q0_ Q0_\n"
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"match_nets $6 NET181\n"
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"match_nets nn1 NN1\n"
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"match_nets $8 NET215\n"
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"match_nets $13 CS1\n"
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"match_nets q1_ Q1_\n"
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"match_nets a0_ A0_\n"
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"match_nets $34 HNET48\n"
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"match_nets nn1_ NN1_\n"
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"match_nets a0 A0\n"
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"match_nets $35 HNET44\n"
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"match_nets nn1_ NN1_\n"
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"match_nets $9 NET175\n"
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"match_nets $4 NET200\n"
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"match_nets a0_ A0_\n"
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"match_nets $34 HNET48\n"
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"match_pins VDD VDD\n"
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"match_pins nn1_ NN1_\n"
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"match_pins nn1 NN1\n"
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"match_pins q0 Q0\n"
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"match_pins q0_ Q0_\n"
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"match_pins q1_ Q1_\n"
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"match_pins q1 Q1\n"
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"match_pins nn2 NN2\n"
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"match_pins nn2_ NN2_\n"
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"match_pins a0 A0\n"
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"match_pins a0_ A0_\n"
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"match_pins g1 G1\n"
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"match_pins g0 G0\n"
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"match_pins gtp NN3\n"
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"match_pins VSS VSS\n"
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"match_pins WELL WELL\n"
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"match_devices $30 0\n"
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"match_devices $29 1\n"
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"match_devices $9 10\n"
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"match_devices $10 11\n"
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"match_devices $36 12\n"
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"match_devices $35 13\n"
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"match_devices $34 14\n"
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"match_devices $38 15\n"
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"match_devices $37 16\n"
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"match_devices $33 17\n"
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"match_devices $27 18\n"
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"match_devices $28 19\n"
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"match_devices $17 2\n"
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"match_devices $31 20\n"
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"match_devices $32 21\n"
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"match_devices $22 22\n"
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"match_devices $26 23\n"
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"match_devices $23 24\n"
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"match_devices $43 25\n"
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"match_devices $20 26\n"
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"match_devices $25 27\n"
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"match_devices $15 28\n"
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"match_devices $14 29\n"
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"match_devices $16 3\n"
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"match_devices $18 30\n"
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"match_devices $21 31\n"
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"match_devices $13 32\n"
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"match_devices $19 33\n"
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"match_devices $7 34\n"
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"match_devices $8 35\n"
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"match_devices $24 36\n"
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"match_devices $3 37\n"
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"match_devices $6 38\n"
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"match_devices $4 39\n"
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"match_devices $39 4\n"
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"match_devices $5 40\n"
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"match_devices $2 41\n"
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"match_devices $1 42\n"
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"match_devices $40 5\n"
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"match_devices $11 6\n"
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"match_devices $12 7\n"
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"match_devices $41 8\n"
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"match_devices $42 9\n"
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"end_circuit DECODE DECODE MATCH"
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);
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EXPECT_EQ (good, true);
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comp.set_depth_first (false);
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logger.clear ();
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good = comp.compare (&nl1, &nl2);
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EXPECT_EQ (logger.text (),
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"begin_circuit DECODE DECODE\n"
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"match_nets $41 WL1_EN_\n"
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"match_nets VDD VDD\n"
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"match_nets $39 NET194\n"
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"match_nets g0 G0\n"
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"match_nets $40 HNET52\n"
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"match_nets VSS VSS\n"
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"match_nets $42 NET189\n"
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"match_nets gtp NN3\n"
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"match_nets $37 NET193\n"
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"match_nets g1 G1\n"
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"match_nets $44 YI\n"
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"match_nets $14 WELL\n"
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"match_nets nn2 NN2\n"
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"match_nets nn2_ NN2_\n"
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"match_ambiguous_nets q0 Q0\n"
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"match_ambiguous_nets q1 Q1\n"
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"match_nets $11 CS0\n"
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"match_nets q0_ Q0_\n"
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"match_nets $4 NET200\n"
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"match_nets $13 CS1\n"
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"match_nets q1_ Q1_\n"
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"match_nets $9 NET175\n"
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"match_nets a0 A0\n"
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"match_nets a0_ A0_\n"
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"match_nets $35 HNET44\n"
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"match_nets $34 HNET48\n"
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"match_nets $6 NET181\n"
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"match_nets $8 NET215\n"
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"match_nets nn1 NN1\n"
|
||||
"match_nets nn1_ NN1_\n"
|
||||
"match_pins VDD VDD\n"
|
||||
"match_pins nn1_ NN1_\n"
|
||||
"match_pins nn1 NN1\n"
|
||||
@@ -3805,11 +4043,11 @@ TEST(25c_JoinSymmetricNetsMultipleMessedUp)
|
||||
// NOTE $1 and $2 are joined because they are symmetric
|
||||
EXPECT_EQ (nl.to_string (),
|
||||
"circuit NOR3 (A=A,C=C,B=B,OUT=OUT,VSS=VSS,VDD=VDD);\n"
|
||||
" device PMOS $1 (S=$5,G=B,D=$3) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
" device PMOS $1 (S=$6,G=B,D=$3) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
" device NMOS $2 (S=OUT,G=A,D=VSS) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
" device PMOS $3 (S=$3,G=A,D=OUT) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
" device NMOS $4 (S=OUT,G=B,D=VSS) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
" device PMOS $8 (S=VDD,G=C,D=$5) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
" device PMOS $8 (S=VDD,G=C,D=$6) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
" device NMOS $12 (S=VSS,G=C,D=OUT) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
|
||||
"end;\n"
|
||||
)
|
||||
|
||||
Reference in New Issue
Block a user