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klayout
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Provide special LVS test golden data for Windows (slight differences in shape order etc.)

This commit is contained in:
Matthias Köfferlein 2019-07-16 00:40:43 +02:00
parent df23830a1c
commit b3e9915259
30 changed files with 8603 additions and 98 deletions
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46
src/db/unit_tests/dbLayoutToNetlistReaderTests.cc
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@ -53,14 +53,7 @@ TEST(1_ReaderBasic)
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au.txt");
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
compare_text_files (path, au_path);
// test build_all_nets from read l2n
@ -270,15 +263,7 @@ TEST(1b_ReaderBasicShort)
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_s.txt");
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
compare_text_files (path, au_path);
}
TEST(2_ReaderWithGlobalNets)
@ -302,14 +287,7 @@ TEST(2_ReaderWithGlobalNets)
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt");
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
compare_text_files (path, au_path);
// test build_all_nets from read l2n
@ -366,14 +344,7 @@ TEST(3_ReaderAbsoluteCoordinates)
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt");
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
compare_text_files (path, au_path);
// test build_all_nets from read l2n
@ -432,14 +403,7 @@ TEST(4_ReaderCombinedDevices)
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_reader_au_4.l2n");
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
compare_text_files (path, au_path);
// test build_all_nets from read l2n

44
src/db/unit_tests/dbLayoutToNetlistWriterTests.cc
View File

@ -176,16 +176,7 @@ TEST(1_WriterBasic)
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au.txt");
{
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
}
compare_text_files (path, au_path);
path = tmp_file ("tmp_l2nwriter_1s.txt");
{
@ -196,16 +187,7 @@ TEST(1_WriterBasic)
au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_s.txt");
{
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
}
compare_text_files (path, au_path);
// test build_all_nets (verify reference for reader)
@ -398,16 +380,7 @@ TEST(2_WriterWithGlobalNets)
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt");
{
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
}
compare_text_files (path, au_path);
path = tmp_file ("tmp_l2nwriter_2s.txt");
{
@ -418,16 +391,7 @@ TEST(2_WriterWithGlobalNets)
au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2s.txt");
{
tl::InputStream is (path);
tl::InputStream is_au (au_path);
if (is.read_all () != is_au.read_all ()) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
}
compare_text_files (path, au_path);
// test build_all_nets as reference for the reader

12
src/db/unit_tests/dbLayoutVsSchematicTests.cc
View File

@ -56,17 +56,7 @@ static unsigned int define_layer (db::Layout &ly, db::LayerMap &lmap, int gds_la
static void compare_lvsdbs (tl::TestBase *_this, const std::string &path, const std::string &au_path)
{
tl::InputStream is (path);
tl::InputStream is_au (au_path);
std::string netlist = is.read_all ();
std::string netlist_au = is_au.read_all ();
if (netlist != netlist_au) {
_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
tl::absolute_file_path (path),
tl::absolute_file_path (au_path)));
}
_this->compare_text_files (path, au_path);
}
TEST(1_BasicFlow)

46
src/tl/tl/tlUnitTest.cc
View File

@ -344,13 +344,49 @@ static std::string read_file (const std::string &path)
void TestBase::compare_text_files (const std::string &path_a, const std::string &path_b)
{
std::string text_a = read_file (path_a);
std::string text_b = read_file (path_b);
bool equal = false;
bool any = false;
if (text_a != text_b) {
raise (tl::sprintf ("Compare failed - see:\n file 1: %s\n file 2: %s",
int n = 0;
for ( ; ! equal; ++n) {
std::string fn_a = path_a; // no variants for a
std::string fn_b = path_b;
if (n > 0) {
fn_b += tl::sprintf (".%d", n);
}
if (tl::file_exists (fn_b)) {
if (n == 1 && any) {
throw tl::Exception (tl::sprintf ("Inconsistent reference variants for %s: there can be either variants (.1,.2,... suffix) or a single file (without suffix)", path_b));
}
any = true;
std::string text_a = read_file (fn_a);
std::string text_b = read_file (fn_b);
equal = (text_a == text_b);
if (equal && n > 0) {
tl::info << tl::sprintf ("Found match on golden reference variant %s", fn_b);
}
} else if (n > 0) {
if (! any) {
tl::warn << tl::sprintf ("No golden data found (%s)", path_b);
}
break;
}
}
if (! equal) {
throw tl::Exception (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s%s",
tl::absolute_file_path (path_a),
tl::absolute_file_path (path_b)));
tl::absolute_file_path (path_b),
(n > 1 ? "\nand variants" : "")));
}
}

0
testdata/lvs/ringo_simple.lvsdb → testdata/lvs/ringo_simple.lvsdb.1 vendored
View File

971
testdata/lvs/ringo_simple.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,971 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l1)
layer(l9)
layer(l5)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l1 l9 l5 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l1 l8 l1)
connect(l9 l3 l8 l9)
connect(l5 l8 l5)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l1 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l5 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l1 (-276 -2151) (425 1500))
rect(l1 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l1 (-375 -1450) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l5 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l5 (975 1660) (425 950))
rect(l5 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l1 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l1 (-226 1049) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l5 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l1 (-1175 1800) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(2
rect(l8 (6510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3
rect(l8 (8310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(4
rect(l8 (10110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(5
rect(l8 (11910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(6
rect(l8 (13710 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(7
rect(l8 (15510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(8
rect(l8 (17310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(9
rect(l8 (19110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(10
rect(l8 (20910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(11 name(FB)
rect(l8 (22710 3010) (180 180))
rect(l8 (-19700 720) (180 180))
rect(l11 (18380 -1140) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
rect(l1 (-245 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l1 (-23025 -2550) (425 1500))
rect(l1 (-400 -1500) (425 1500))
rect(l1 (1275 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l9 (-21975 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
rect(l1 (-625 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(14 name(ENABLE)
rect(l8 (2510 3010) (180 180))
rect(l11 (-250 -250) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l5 (-23700 460) (425 950))
rect(l5 (1975 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l10 (-21975 -2210) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
device(3 3 match)
device(4 4 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(1 1 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
)
)
)

0
testdata/lvs/ringo_simple_implicit_connections.lvsdb → testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 vendored
View File

990
testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,990 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l1)
layer(l9)
layer(l5)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l1 l9 l5 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l1 l8 l1)
connect(l9 l3 l8 l9)
connect(l5 l8 l5)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l1 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l5 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l1 (-276 -2151) (425 1500))
rect(l1 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l1 (-375 -1450) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l5 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l5 (975 1660) (425 950))
rect(l5 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l1 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l1 (-226 1049) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l5 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (28300 7650))
# Nets with their geometries
net(1
rect(l8 (5210 3010) (180 180))
rect(l11 (-1350 -240) (1160 300))
rect(l1 (-1725 1800) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(2
rect(l8 (7010 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3
rect(l8 (8810 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(4
rect(l8 (10610 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(5
rect(l8 (12410 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(6
rect(l8 (14210 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(7
rect(l8 (16010 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(8
rect(l8 (17810 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(9
rect(l8 (19610 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(10
rect(l8 (21410 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(11 name(FB)
rect(l8 (25210 3010) (180 180))
rect(l8 (-22200 720) (180 180))
rect(l11 (18880 -1140) (2900 300))
rect(l11 (-21980 590) (320 320))
rect(l11 (18570 -320) (320 320))
rect(l12 (-19150 -260) (200 200))
rect(l12 (18690 -200) (200 200))
rect(l13 (-18840 -300) (18890 400))
rect(l13 (-19071 -201) (2 2))
rect(l13 (-171 -201) (400 400))
rect(l13 (18490 -400) (400 400))
rect(l1 (-545 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(12 name(VDD)
rect(l3 (22600 4500) (1400 3500))
rect(l3 (-23500 -3500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (25800 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-5090 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (25720 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-4891 1009) (2 2))
rect(l11 (2798 -52) (2 2))
rect(l11 (-22152 -102) (2 2))
rect(l11 (19749 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-22751 -401) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (25900 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l1 (-23300 -2550) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (-18850 -1500) (425 1500))
rect(l1 (-400 -1500) (425 1500))
rect(l1 (21775 -1500) (425 1500))
rect(l9 (-2375 -450) (500 1500))
rect(l9 (-22600 -1500) (500 1500))
rect(l9 (25400 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (25990 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-151 -101) (2 2))
rect(l13 (-151 -201) (400 400))
rect(l1 (-675 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(14 name(ENABLE)
rect(l8 (2510 3010) (180 180))
rect(l11 (-200 -250) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-151 -101) (2 2))
rect(l13 (-151 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (27010 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-3980 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (24709 -291) (2 2))
rect(l11 (-3852 -2) (2 2))
rect(l11 (-19202 -102) (2 2))
rect(l11 (23999 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l11 (-5150 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-22301 -351) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l5 (24400 460) (425 950))
rect(l5 (-20425 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (-19525 -950) (425 950))
rect(l10 (24325 -2210) (500 1500))
rect(l10 (-4300 -1500) (500 1500))
rect(l10 (-22600 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4700 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6500 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(8300 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(10100 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11900 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13700 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15500 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(17300 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(19100 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20900 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(24700 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
device(3 3 match)
device(4 4 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(1 1 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
)
)
)

0
testdata/lvs/ringo_simple_io.cir → testdata/lvs/ringo_simple_io.cir.1 vendored
View File

31
testdata/lvs/ringo_simple_io.cir.2 vendored Normal file
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@ -0,0 +1,31 @@
* Extracted by KLayout
.SUBCKT RINGO FB VDD OUT ENABLE VSS
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
X$11 VDD FB VSS VDD \$10 VSS INVX1
X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I5 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1

0
testdata/lvs/ringo_simple_io.lvsdb → testdata/lvs/ringo_simple_io.lvsdb.1 vendored
View File

891
testdata/lvs/ringo_simple_io.lvsdb.2 vendored Normal file
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@ -0,0 +1,891 @@
#%lvsdb-klayout
J(
W(RINGO)
U(0.001)
L(l3 '1/0')
L(l4 '5/0')
L(l8 '8/0')
L(l11 '9/0')
L(l12 '10/0')
L(l13 '11/0')
L(l7)
L(l1)
L(l9)
L(l5)
L(l10)
C(l3 l3 l9)
C(l4 l4 l8)
C(l8 l4 l8 l11 l1 l9 l5 l10)
C(l11 l8 l11 l12)
C(l12 l11 l12 l13)
C(l13 l12 l13)
C(l7 l7)
C(l1 l8 l1)
C(l9 l3 l8 l9)
C(l5 l8 l5)
C(l10 l8 l10)
G(l7 SUBSTRATE)
G(l10 SUBSTRATE)
D(D$PMOS PMOS
T(S
R(l1 (-550 -750) (425 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l1 (125 -750) (450 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$PMOS$1 PMOS
T(S
R(l1 (-575 -750) (450 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l1 (125 -750) (425 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$PMOS$2 PMOS
T(S
R(l1 (-550 -750) (425 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l1 (125 -750) (425 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$NMOS NMOS
T(S
R(l5 (-550 -475) (425 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (450 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
D(D$NMOS$1 NMOS
T(S
R(l5 (-575 -475) (450 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (425 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
D(D$NMOS$2 NMOS
T(S
R(l5 (-550 -475) (425 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (425 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
X(ND2X1
R((-100 400) (2600 7600))
N(1 I(VDD)
R(l8 (1110 5160) (180 180))
R(l8 (-180 920) (180 180))
R(l8 (-180 -730) (180 180))
R(l11 (-240 -790) (300 1700))
R(l11 (-1350 0) (2400 800))
R(l11 (-1151 -401) (2 2))
R(l1 (-276 -2151) (425 1500))
R(l1 (-400 -1500) (425 1500))
)
N(2 I(OUT)
R(l8 (1810 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-1580 3760) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (1220 920) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
R(l11 (-110 1390) (300 1400))
Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
R(l11 (-141 -501) (2 2))
R(l11 (-1751 1099) (300 1400))
R(l11 (1100 -1700) (300 300))
R(l11 (-300 0) (300 1400))
R(l1 (-375 -1450) (425 1500))
R(l1 (-1800 -1500) (425 1500))
R(l5 (950 -4890) (425 950))
)
N(3 I(VSS)
R(l8 (410 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -1300) (300 1360))
R(l11 (-650 -2160) (2400 800))
R(l11 (-1151 -401) (2 2))
R(l5 (-951 859) (425 950))
)
N(4
R(l3 (-100 4500) (2600 3500))
)
N(5 I(B)
R(l4 (1425 2860) (250 1940))
R(l4 (-345 -950) (300 300))
R(l4 (-205 650) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-285 1050) (180 180))
R(l11 (-71 -91) (2 2))
R(l11 (-171 -151) (300 300))
)
N(6 I(A)
R(l4 (725 2860) (250 1940))
R(l4 (-325 -1850) (300 300))
R(l4 (-225 1550) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-265 150) (180 180))
R(l11 (-91 -91) (2 2))
R(l11 (-151 -151) (300 300))
)
N(7 I(SUBSTRATE))
N(8
R(l5 (975 1660) (425 950))
R(l5 (-400 -950) (425 950))
)
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4)
P(5 I(B))
P(6 I(A))
P(7 I(SUBSTRATE))
D(1 D$PMOS
Y(850 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.6375)
E(AD 0.3375)
E(PS 3.85)
E(PD 1.95)
T(S 2)
T(G 6)
T(D 1)
T(B 4)
)
D(2 D$PMOS$1
Y(1550 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.3375)
E(AD 0.6375)
E(PS 1.95)
E(PD 3.85)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(3 D$NMOS
Y(850 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.40375)
E(AD 0.21375)
E(PS 2.75)
E(PD 1.4)
T(S 3)
T(G 6)
T(D 8)
T(B 7)
)
D(4 D$NMOS$1
Y(1550 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.21375)
E(AD 0.40375)
E(PS 1.4)
E(PD 2.75)
T(S 8)
T(G 5)
T(D 2)
T(B 7)
)
)
X(INVX1
R((-100 400) (2000 7600))
N(1 I(VDD)
R(l8 (410 6260) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -730) (180 180))
R(l11 (-240 -240) (300 1400))
R(l11 (-650 300) (1800 800))
R(l11 (-1450 -1100) (300 300))
R(l11 (299 399) (2 2))
R(l1 (-651 -2151) (425 1500))
)
N(2 I(OUT)
R(l8 (1110 5160) (180 180))
R(l8 (-180 920) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -4120) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -790) (300 4790))
R(l11 (-151 -2501) (2 2))
R(l1 (-226 1049) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(3 I(VSS)
R(l8 (410 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -1300) (300 1360))
R(l11 (-650 -2160) (1800 800))
R(l11 (-851 -401) (2 2))
R(l5 (-651 859) (425 950))
)
N(4
R(l3 (-100 4500) (2000 3500))
)
N(5 I(IN)
R(l4 (725 2860) (250 1940))
R(l4 (-525 -1850) (300 300))
R(l4 (-25 1550) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-465 150) (180 180))
R(l11 (-91 -91) (2 2))
R(l11 (-151 -151) (300 300))
)
N(6 I(SUBSTRATE))
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4)
P(5 I(IN))
P(6 I(SUBSTRATE))
D(1 D$PMOS$2
Y(850 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.6375)
E(AD 0.6375)
E(PS 3.85)
E(PD 3.85)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(2 D$NMOS$2
Y(850 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.40375)
E(AD 0.40375)
E(PS 2.75)
E(PD 2.75)
T(S 3)
T(G 5)
T(D 2)
T(B 6)
)
)
X(RINGO
R((0 350) (25800 7650))
N(1
R(l8 (4710 3010) (180 180))
R(l11 (-850 -240) (610 300))
R(l1 (-1175 1800) (425 1500))
R(l1 (-1800 -1500) (425 1500))
R(l5 (950 -4890) (425 950))
)
N(2
R(l8 (6510 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(3
R(l8 (8310 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(4
R(l8 (10110 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(5
R(l8 (11910 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(6
R(l8 (13710 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(7
R(l8 (15510 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(8
R(l8 (17310 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(9
R(l8 (19110 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(10
R(l8 (20910 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(11 I(FB)
R(l8 (22710 3010) (180 180))
R(l8 (-19700 720) (180 180))
R(l11 (18380 -1140) (900 300))
R(l11 (-19530 590) (320 320))
R(l11 (17820 -320) (320 320))
R(l12 (-18400 -260) (200 200))
R(l12 (17940 -200) (200 200))
R(l13 (-18040 -300) (17740 400))
R(l13 (-17921 -201) (2 2))
R(l13 (-221 -201) (400 400))
R(l13 (17740 -400) (400 400))
R(l1 (-245 850) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(12 I(VDD)
R(l3 (500 4500) (1400 3500))
R(l3 (-1900 -3500) (600 3500))
R(l3 (23300 -3500) (1400 3500))
R(l3 (-100 -3500) (600 3500))
R(l8 (-24690 -1240) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (23220 370) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l11 (-21741 859) (2 2))
R(l11 (-2351 -451) (1200 800))
R(l11 (-750 -1450) (300 1400))
R(l11 (-101 -351) (2 2))
R(l11 (-1251 -401) (600 800))
R(l11 (23400 -800) (1200 800))
R(l11 (-750 -1450) (300 1400))
R(l11 (-101 -351) (2 2))
R(l11 (549 -401) (600 800))
R(l1 (-23025 -2550) (425 1500))
R(l1 (-400 -1500) (425 1500))
R(l1 (1275 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l9 (-21975 -450) (500 1500))
R(l9 (22900 -1500) (500 1500))
)
N(13 I(OUT)
R(l11 (23440 3840) (320 320))
R(l12 (-260 -260) (200 200))
R(l13 (-101 -101) (2 2))
R(l13 (-201 -201) (400 400))
R(l1 (-625 850) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(14 I(ENABLE)
R(l8 (2510 3010) (180 180))
R(l11 (-250 -250) (320 320))
R(l12 (-260 -260) (200 200))
R(l13 (-101 -101) (2 2))
R(l13 (-201 -201) (400 400))
)
N(15 I(VSS)
R(l8 (1110 1610) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (23220 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-21741 -391) (2 2))
R(l11 (-1901 -401) (300 1400))
R(l11 (-750 -1450) (1200 800))
R(l11 (-551 -401) (2 2))
R(l11 (-1251 -401) (600 800))
R(l11 (23850 -750) (300 1400))
R(l11 (-750 -1450) (1200 800))
R(l11 (-551 -401) (2 2))
R(l11 (549 -401) (600 800))
R(l5 (-23700 460) (425 950))
R(l5 (1975 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l10 (-21975 -2210) (500 1500))
R(l10 (22900 -1500) (500 1500))
)
P(11 I(FB))
P(12 I(VDD))
P(13 I(OUT))
P(14 I(ENABLE))
P(15 I(VSS))
X(1 ND2X1 Y(1800 0)
P(0 12)
P(1 1)
P(2 15)
P(3 12)
P(4 11)
P(5 14)
P(6 15)
)
X(2 INVX1 Y(4200 0)
P(0 12)
P(1 2)
P(2 15)
P(3 12)
P(4 1)
P(5 15)
)
X(3 INVX1 Y(6000 0)
P(0 12)
P(1 3)
P(2 15)
P(3 12)
P(4 2)
P(5 15)
)
X(4 INVX1 Y(7800 0)
P(0 12)
P(1 4)
P(2 15)
P(3 12)
P(4 3)
P(5 15)
)
X(5 INVX1 Y(9600 0)
P(0 12)
P(1 5)
P(2 15)
P(3 12)
P(4 4)
P(5 15)
)
X(6 INVX1 Y(11400 0)
P(0 12)
P(1 6)
P(2 15)
P(3 12)
P(4 5)
P(5 15)
)
X(7 INVX1 Y(13200 0)
P(0 12)
P(1 7)
P(2 15)
P(3 12)
P(4 6)
P(5 15)
)
X(8 INVX1 Y(15000 0)
P(0 12)
P(1 8)
P(2 15)
P(3 12)
P(4 7)
P(5 15)
)
X(9 INVX1 Y(16800 0)
P(0 12)
P(1 9)
P(2 15)
P(3 12)
P(4 8)
P(5 15)
)
X(10 INVX1 Y(18600 0)
P(0 12)
P(1 10)
P(2 15)
P(3 12)
P(4 9)
P(5 15)
)
X(11 INVX1 Y(20400 0)
P(0 12)
P(1 11)
P(2 15)
P(3 12)
P(4 10)
P(5 15)
)
X(12 INVX1 Y(22200 0)
P(0 12)
P(1 13)
P(2 15)
P(3 12)
P(4 11)
P(5 15)
)
)
)
H(
X(ND2X1
N(1 I(VDD))
N(2 I(OUT))
N(3 I(VSS))
N(4 I(NWELL))
N(5 I(B))
N(6 I(A))
N(7 I(BULK))
N(8 I('1'))
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4 I(NWELL))
P(5 I(B))
P(6 I(A))
P(7 I(BULK))
D(1 PMOS
I($1)
E(L 0.25)
E(W 1.5)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(G 6)
T(D 1)
T(B 4)
)
D(2 PMOS
I($2)
E(L 0.25)
E(W 1.5)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(3 NMOS
I($3)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 3)
T(G 6)
T(D 8)
T(B 7)
)
D(4 NMOS
I($4)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 8)
T(G 5)
T(D 2)
T(B 7)
)
)
X(INVX1
N(1 I(VDD))
N(2 I(OUT))
N(3 I(VSS))
N(4 I(NWELL))
N(5 I(IN))
N(6 I(BULK))
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4 I(NWELL))
P(5 I(IN))
P(6 I(BULK))
D(1 PMOS
I($1)
E(L 0.25)
E(W 1.5)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(2 NMOS
I($2)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 3)
T(G 5)
T(D 2)
T(B 6)
)
)
X(RINGO
N(1 I(VSS))
N(2 I(VDD))
N(3 I(FB))
N(4 I(ENABLE))
N(5 I(OUT))
N(6 I('1'))
N(7 I('2'))
N(8 I('3'))
N(9 I('4'))
N(10 I('5'))
N(11 I('6'))
N(12 I('7'))
N(13 I('8'))
N(14 I('9'))
N(15 I('10'))
P(1 I(VSS))
P(2 I(VDD))
P(3 I(FB))
P(4 I(ENABLE))
P(5 I(OUT))
X(1 ND2X1 I($1)
P(0 2)
P(1 6)
P(2 1)
P(3 2)
P(4 3)
P(5 4)
P(6 1)
)
X(2 INVX1 I($2)
P(0 2)
P(1 7)
P(2 1)
P(3 2)
P(4 6)
P(5 1)
)
X(3 INVX1 I($3)
P(0 2)
P(1 8)
P(2 1)
P(3 2)
P(4 7)
P(5 1)
)
X(4 INVX1 I($4)
P(0 2)
P(1 9)
P(2 1)
P(3 2)
P(4 8)
P(5 1)
)
X(5 INVX1 I($5)
P(0 2)
P(1 10)
P(2 1)
P(3 2)
P(4 9)
P(5 1)
)
X(6 INVX1 I($6)
P(0 2)
P(1 11)
P(2 1)
P(3 2)
P(4 10)
P(5 1)
)
X(7 INVX1 I($7)
P(0 2)
P(1 12)
P(2 1)
P(3 2)
P(4 11)
P(5 1)
)
X(8 INVX1 I($8)
P(0 2)
P(1 13)
P(2 1)
P(3 2)
P(4 12)
P(5 1)
)
X(9 INVX1 I($9)
P(0 2)
P(1 14)
P(2 1)
P(3 2)
P(4 13)
P(5 1)
)
X(10 INVX1 I($10)
P(0 2)
P(1 15)
P(2 1)
P(3 2)
P(4 14)
P(5 1)
)
X(11 INVX1 I($11)
P(0 2)
P(1 3)
P(2 1)
P(3 2)
P(4 15)
P(5 1)
)
X(12 INVX1 I($12)
P(0 2)
P(1 5)
P(2 1)
P(3 2)
P(4 3)
P(5 1)
)
)
)
Z(
X(INVX1 INVX1 1
Z(
N(4 4 1)
N(5 5 1)
N(2 2 1)
N(6 6 1)
N(1 1 1)
N(3 3 1)
P(3 3 1)
P(4 4 1)
P(1 1 1)
P(5 5 1)
P(0 0 1)
P(2 2 1)
D(1 1 1)
D(2 2 1)
)
)
X(ND2X1 ND2X1 1
Z(
N(8 8 1)
N(4 4 1)
N(6 6 1)
N(5 5 1)
N(2 2 1)
N(7 7 1)
N(1 1 1)
N(3 3 1)
P(3 3 1)
P(5 5 1)
P(4 4 1)
P(1 1 1)
P(6 6 1)
P(0 0 1)
P(2 2 1)
D(1 1 1)
D(2 2 1)
D(3 3 1)
D(4 4 1)
)
)
X(RINGO RINGO 1
Z(
N(1 6 1)
N(10 15 1)
N(2 7 1)
N(3 8 1)
N(4 9 1)
N(5 10 1)
N(6 11 1)
N(7 12 1)
N(8 13 1)
N(9 14 1)
N(14 4 1)
N(11 3 1)
N(13 5 1)
N(12 2 1)
N(15 1 1)
P(3 3 1)
P(0 2 1)
P(2 4 1)
P(1 1 1)
P(4 0 1)
X(1 1 1)
X(10 10 1)
X(11 11 1)
X(12 12 1)
X(2 2 1)
X(3 3 1)
X(4 4 1)
X(5 5 1)
X(6 6 1)
X(7 7 1)
X(8 8 1)
X(9 9 1)
)
)
)

0
testdata/lvs/ringo_simple_io2.cir → testdata/lvs/ringo_simple_io2.cir.1 vendored
View File

32
testdata/lvs/ringo_simple_io2.cir.2 vendored Normal file
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@ -0,0 +1,32 @@
* Extracted by KLayout
.INCLUDE 'models.cir'
.SUBCKT RINGO FB VDD OUT ENABLE VSS
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
X$11 VDD FB VSS VDD \$10 VSS INVX1
X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
X$1 VDD IN OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.6375 PS=3.85 PD=3.85
X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.40375
+ PS=2.75 PD=2.75
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
X$1 OUT A VDD \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.3375 PS=3.85 PD=1.95
X$2 VDD B OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.3375 AD=0.6375 PS=1.95 PD=3.85
X$3 VSS A \$I5 SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.21375
+ PS=2.75 PD=1.4
X$4 \$I5 B OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.21375 AD=0.40375
+ PS=1.4 PD=2.75
.ENDS ND2X1

0
testdata/lvs/ringo_simple_io2.l2n → testdata/lvs/ringo_simple_io2.l2n.1 vendored
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580
testdata/lvs/ringo_simple_io2.l2n.2 vendored Normal file
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@ -0,0 +1,580 @@
#%l2n-klayout
W(RINGO)
U(0.001)
L(l3 '1/0')
L(l4 '5/0')
L(l8 '8/0')
L(l11 '9/0')
L(l12 '10/0')
L(l13 '11/0')
L(l7)
L(l1)
L(l9)
L(l5)
L(l10)
C(l3 l3 l9)
C(l4 l4 l8)
C(l8 l4 l8 l11 l1 l9 l5 l10)
C(l11 l8 l11 l12)
C(l12 l11 l12 l13)
C(l13 l12 l13)
C(l7 l7)
C(l1 l8 l1)
C(l9 l3 l8 l9)
C(l5 l8 l5)
C(l10 l8 l10)
G(l7 SUBSTRATE)
G(l10 SUBSTRATE)
D(D$PMOS PMOS
T(S
R(l1 (-550 -750) (425 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l1 (125 -750) (450 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$PMOS$1 PMOS
T(S
R(l1 (-575 -750) (450 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l1 (125 -750) (425 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$PMOS$2 PMOS
T(S
R(l1 (-550 -750) (425 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l1 (125 -750) (425 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$NMOS NMOS
T(S
R(l5 (-550 -475) (425 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (450 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
D(D$NMOS$1 NMOS
T(S
R(l5 (-575 -475) (450 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (425 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
D(D$NMOS$2 NMOS
T(S
R(l5 (-550 -475) (425 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (425 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
X(ND2X1
R((-100 400) (2600 7600))
N(1 I(VDD)
R(l8 (1110 5160) (180 180))
R(l8 (-180 920) (180 180))
R(l8 (-180 -730) (180 180))
R(l11 (-240 -790) (300 1700))
R(l11 (-1350 0) (2400 800))
R(l11 (-1151 -401) (2 2))
R(l1 (-276 -2151) (425 1500))
R(l1 (-400 -1500) (425 1500))
)
N(2 I(OUT)
R(l8 (1810 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-1580 3760) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (1220 920) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
R(l11 (-110 1390) (300 1400))
Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
R(l11 (-141 -501) (2 2))
R(l11 (-1751 1099) (300 1400))
R(l11 (1100 -1700) (300 300))
R(l11 (-300 0) (300 1400))
R(l1 (-375 -1450) (425 1500))
R(l1 (-1800 -1500) (425 1500))
R(l5 (950 -4890) (425 950))
)
N(3 I(VSS)
R(l8 (410 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -1300) (300 1360))
R(l11 (-650 -2160) (2400 800))
R(l11 (-1151 -401) (2 2))
R(l5 (-951 859) (425 950))
)
N(4
R(l3 (-100 4500) (2600 3500))
)
N(5 I(B)
R(l4 (1425 2860) (250 1940))
R(l4 (-345 -950) (300 300))
R(l4 (-205 650) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-285 1050) (180 180))
R(l11 (-71 -91) (2 2))
R(l11 (-171 -151) (300 300))
)
N(6 I(A)
R(l4 (725 2860) (250 1940))
R(l4 (-325 -1850) (300 300))
R(l4 (-225 1550) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-265 150) (180 180))
R(l11 (-91 -91) (2 2))
R(l11 (-151 -151) (300 300))
)
N(7 I(SUBSTRATE))
N(8
R(l5 (975 1660) (425 950))
R(l5 (-400 -950) (425 950))
)
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4)
P(5 I(B))
P(6 I(A))
P(7 I(SUBSTRATE))
D(1 D$PMOS
Y(850 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.6375)
E(AD 0.3375)
E(PS 3.85)
E(PD 1.95)
T(S 2)
T(G 6)
T(D 1)
T(B 4)
)
D(2 D$PMOS$1
Y(1550 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.3375)
E(AD 0.6375)
E(PS 1.95)
E(PD 3.85)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(3 D$NMOS
Y(850 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.40375)
E(AD 0.21375)
E(PS 2.75)
E(PD 1.4)
T(S 3)
T(G 6)
T(D 8)
T(B 7)
)
D(4 D$NMOS$1
Y(1550 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.21375)
E(AD 0.40375)
E(PS 1.4)
E(PD 2.75)
T(S 8)
T(G 5)
T(D 2)
T(B 7)
)
)
X(INVX1
R((-100 400) (2000 7600))
N(1 I(VDD)
R(l8 (410 6260) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -730) (180 180))
R(l11 (-240 -240) (300 1400))
R(l11 (-650 300) (1800 800))
R(l11 (-1450 -1100) (300 300))
R(l11 (299 399) (2 2))
R(l1 (-651 -2151) (425 1500))
)
N(2 I(OUT)
R(l8 (1110 5160) (180 180))
R(l8 (-180 920) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -4120) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -790) (300 4790))
R(l11 (-151 -2501) (2 2))
R(l1 (-226 1049) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(3 I(VSS)
R(l8 (410 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -1300) (300 1360))
R(l11 (-650 -2160) (1800 800))
R(l11 (-851 -401) (2 2))
R(l5 (-651 859) (425 950))
)
N(4
R(l3 (-100 4500) (2000 3500))
)
N(5 I(IN)
R(l4 (725 2860) (250 1940))
R(l4 (-525 -1850) (300 300))
R(l4 (-25 1550) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-465 150) (180 180))
R(l11 (-91 -91) (2 2))
R(l11 (-151 -151) (300 300))
)
N(6 I(SUBSTRATE))
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4)
P(5 I(IN))
P(6 I(SUBSTRATE))
D(1 D$PMOS$2
Y(850 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.6375)
E(AD 0.6375)
E(PS 3.85)
E(PD 3.85)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(2 D$NMOS$2
Y(850 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.40375)
E(AD 0.40375)
E(PS 2.75)
E(PD 2.75)
T(S 3)
T(G 5)
T(D 2)
T(B 6)
)
)
X(RINGO
R((0 350) (25800 7650))
N(1
R(l8 (4710 3010) (180 180))
R(l11 (-850 -240) (610 300))
R(l1 (-1175 1800) (425 1500))
R(l1 (-1800 -1500) (425 1500))
R(l5 (950 -4890) (425 950))
)
N(2
R(l8 (6510 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(3
R(l8 (8310 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(4
R(l8 (10110 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(5
R(l8 (11910 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(6
R(l8 (13710 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(7
R(l8 (15510 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(8
R(l8 (17310 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(9
R(l8 (19110 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(10
R(l8 (20910 3010) (180 180))
R(l11 (-1140 -240) (900 300))
R(l1 (-1275 1800) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(11 I(FB)
R(l8 (22710 3010) (180 180))
R(l8 (-19700 720) (180 180))
R(l11 (18380 -1140) (900 300))
R(l11 (-19530 590) (320 320))
R(l11 (17820 -320) (320 320))
R(l12 (-18400 -260) (200 200))
R(l12 (17940 -200) (200 200))
R(l13 (-18040 -300) (17740 400))
R(l13 (-17921 -201) (2 2))
R(l13 (-221 -201) (400 400))
R(l13 (17740 -400) (400 400))
R(l1 (-245 850) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(12 I(VDD)
R(l3 (500 4500) (1400 3500))
R(l3 (-1900 -3500) (600 3500))
R(l3 (23300 -3500) (1400 3500))
R(l3 (-100 -3500) (600 3500))
R(l8 (-24690 -1240) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (23220 370) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l11 (-21741 859) (2 2))
R(l11 (-2351 -451) (1200 800))
R(l11 (-750 -1450) (300 1400))
R(l11 (-101 -351) (2 2))
R(l11 (-1251 -401) (600 800))
R(l11 (23400 -800) (1200 800))
R(l11 (-750 -1450) (300 1400))
R(l11 (-101 -351) (2 2))
R(l11 (549 -401) (600 800))
R(l1 (-23025 -2550) (425 1500))
R(l1 (-400 -1500) (425 1500))
R(l1 (1275 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l1 (1375 -1500) (425 1500))
R(l9 (-21975 -450) (500 1500))
R(l9 (22900 -1500) (500 1500))
)
N(13 I(OUT)
R(l11 (23440 3840) (320 320))
R(l12 (-260 -260) (200 200))
R(l13 (-101 -101) (2 2))
R(l13 (-201 -201) (400 400))
R(l1 (-625 850) (425 1500))
R(l5 (-425 -4890) (425 950))
)
N(14 I(ENABLE)
R(l8 (2510 3010) (180 180))
R(l11 (-250 -250) (320 320))
R(l12 (-260 -260) (200 200))
R(l13 (-101 -101) (2 2))
R(l13 (-201 -201) (400 400))
)
N(15 I(VSS)
R(l8 (1110 1610) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (23220 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-21741 -391) (2 2))
R(l11 (-1901 -401) (300 1400))
R(l11 (-750 -1450) (1200 800))
R(l11 (-551 -401) (2 2))
R(l11 (-1251 -401) (600 800))
R(l11 (23850 -750) (300 1400))
R(l11 (-750 -1450) (1200 800))
R(l11 (-551 -401) (2 2))
R(l11 (549 -401) (600 800))
R(l5 (-23700 460) (425 950))
R(l5 (1975 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l5 (1375 -950) (425 950))
R(l10 (-21975 -2210) (500 1500))
R(l10 (22900 -1500) (500 1500))
)
P(11 I(FB))
P(12 I(VDD))
P(13 I(OUT))
P(14 I(ENABLE))
P(15 I(VSS))
X(1 ND2X1 Y(1800 0)
P(0 12)
P(1 1)
P(2 15)
P(3 12)
P(4 11)
P(5 14)
P(6 15)
)
X(2 INVX1 Y(4200 0)
P(0 12)
P(1 2)
P(2 15)
P(3 12)
P(4 1)
P(5 15)
)
X(3 INVX1 Y(6000 0)
P(0 12)
P(1 3)
P(2 15)
P(3 12)
P(4 2)
P(5 15)
)
X(4 INVX1 Y(7800 0)
P(0 12)
P(1 4)
P(2 15)
P(3 12)
P(4 3)
P(5 15)
)
X(5 INVX1 Y(9600 0)
P(0 12)
P(1 5)
P(2 15)
P(3 12)
P(4 4)
P(5 15)
)
X(6 INVX1 Y(11400 0)
P(0 12)
P(1 6)
P(2 15)
P(3 12)
P(4 5)
P(5 15)
)
X(7 INVX1 Y(13200 0)
P(0 12)
P(1 7)
P(2 15)
P(3 12)
P(4 6)
P(5 15)
)
X(8 INVX1 Y(15000 0)
P(0 12)
P(1 8)
P(2 15)
P(3 12)
P(4 7)
P(5 15)
)
X(9 INVX1 Y(16800 0)
P(0 12)
P(1 9)
P(2 15)
P(3 12)
P(4 8)
P(5 15)
)
X(10 INVX1 Y(18600 0)
P(0 12)
P(1 10)
P(2 15)
P(3 12)
P(4 9)
P(5 15)
)
X(11 INVX1 Y(20400 0)
P(0 12)
P(1 11)
P(2 15)
P(3 12)
P(4 10)
P(5 15)
)
X(12 INVX1 Y(22200 0)
P(0 12)
P(1 13)
P(2 15)
P(3 12)
P(4 11)
P(5 15)
)
)

0
testdata/lvs/ringo_simple_io2.lvsdb → testdata/lvs/ringo_simple_io2.lvsdb.1 vendored
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971
testdata/lvs/ringo_simple_io2.lvsdb.2 vendored Normal file
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@ -0,0 +1,971 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l1)
layer(l9)
layer(l5)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l1 l9 l5 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l1 l8 l1)
connect(l9 l3 l8 l9)
connect(l5 l8 l5)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l1 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l5 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l1 (-276 -2151) (425 1500))
rect(l1 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l1 (-375 -1450) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l5 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l5 (975 1660) (425 950))
rect(l5 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l1 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l1 (-226 1049) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l5 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l1 (-1175 1800) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(2
rect(l8 (6510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3
rect(l8 (8310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(4
rect(l8 (10110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(5
rect(l8 (11910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(6
rect(l8 (13710 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(7
rect(l8 (15510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(8
rect(l8 (17310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(9
rect(l8 (19110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(10
rect(l8 (20910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(11 name(FB)
rect(l8 (22710 3010) (180 180))
rect(l8 (-19700 720) (180 180))
rect(l11 (18380 -1140) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
rect(l1 (-245 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l1 (-23025 -2550) (425 1500))
rect(l1 (-400 -1500) (425 1500))
rect(l1 (1275 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l9 (-21975 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
rect(l1 (-625 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(14 name(ENABLE)
rect(l8 (2510 3010) (180 180))
rect(l11 (-250 -250) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l5 (-23700 460) (425 950))
rect(l5 (1975 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l10 (-21975 -2210) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
device(3 3 match)
device(4 4 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(1 1 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
)
)
)

0
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb → testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 vendored
View File

970
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,970 @@
#%lvsdb-klayout
# Layout
layout(
top(top)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l1)
layer(l9)
layer(l5)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l1 l9 l5 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l1 l8 l1)
connect(l9 l3 l8 l9)
connect(l5 l8 l5)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l1 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l5 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(nd2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l1 (-276 -2151) (425 1500))
rect(l1 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l1 (-375 -1450) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l5 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l5 (975 1660) (425 950))
rect(l5 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INV
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l1 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l1 (-226 1049) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l5 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(top
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l1 (-1175 1800) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(2
rect(l8 (6510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3
rect(l8 (8310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(4
rect(l8 (10110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(5
rect(l8 (11910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(6
rect(l8 (13710 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(7
rect(l8 (15510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(8
rect(l8 (17310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(9
rect(l8 (19110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(10
rect(l8 (20910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(11 name(FB)
rect(l8 (22710 3010) (180 180))
rect(l8 (-19700 720) (180 180))
rect(l11 (18380 -1140) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
rect(l1 (-245 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l1 (-23025 -2550) (425 1500))
rect(l1 (-400 -1500) (425 1500))
rect(l1 (1275 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l9 (-21975 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
rect(l1 (-625 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(14 name(ENABLE)
rect(l8 (2510 3010) (180 180))
rect(l11 (-250 -250) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l5 (-23700 460) (425 950))
rect(l5 (1975 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l10 (-21975 -2210) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 nd2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INV location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INV location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INV location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INV location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INV location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INV location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INV location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INV location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INV location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INV location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INV location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INV INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(nd2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
device(3 3 match)
device(4 4 match)
)
)
circuit(top RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(1 1 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
)
)
)

0
testdata/lvs/ringo_simple_pin_swapping.lvsdb → testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 vendored
View File

971
testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,971 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l1)
layer(l9)
layer(l5)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l1 l9 l5 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l1 l8 l1)
connect(l9 l3 l8 l9)
connect(l5 l8 l5)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l1 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l5 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l1 (-276 -2151) (425 1500))
rect(l1 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l1 (-375 -1450) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l5 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l5 (975 1660) (425 950))
rect(l5 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l1 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l1 (-226 1049) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l5 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l1 (-1175 1800) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(2
rect(l8 (6510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3
rect(l8 (8310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(4
rect(l8 (10110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(5
rect(l8 (11910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(6
rect(l8 (13710 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(7
rect(l8 (15510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(8
rect(l8 (17310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(9
rect(l8 (19110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(10
rect(l8 (20910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(11 name(FB)
rect(l8 (22710 3010) (180 180))
rect(l8 (-19700 720) (180 180))
rect(l11 (18380 -1140) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
rect(l1 (-245 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l1 (-23025 -2550) (425 1500))
rect(l1 (-400 -1500) (425 1500))
rect(l1 (1275 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l9 (-21975 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
rect(l1 (-625 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(14 name(ENABLE)
rect(l8 (2510 3010) (180 180))
rect(l11 (-250 -250) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l5 (-23700 460) (425 950))
rect(l5 (1975 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l10 (-21975 -2210) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(A))
net(6 name(B))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(A))
pin(6 name(B))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 5)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 6)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 5 match)
net(5 6 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 4 match)
pin(4 5 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
device(3 3 match)
device(4 4 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(1 1 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
)
)
)

0
testdata/lvs/ringo_simple_same_device_classes.cir → testdata/lvs/ringo_simple_same_device_classes.cir.1 vendored
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31
testdata/lvs/ringo_simple_same_device_classes.cir.2 vendored Normal file
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@ -0,0 +1,31 @@
* Extracted by KLayout
.SUBCKT RINGO FB VDD OUT ENABLE VSS
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
X$11 VDD FB VSS VDD \$10 VSS INVX1
X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I5 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I5 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1

0
testdata/lvs/ringo_simple_same_device_classes.lvsdb → testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 vendored
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971
testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 vendored Normal file
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@ -0,0 +1,971 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l1)
layer(l9)
layer(l5)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l1 l9 l5 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l1 l8 l1)
connect(l9 l3 l8 l9)
connect(l5 l8 l5)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PM MOS4)
class(NM MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PM PM
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PM$1 PM
terminal(S
rect(l1 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PM$2 PM
terminal(S
rect(l1 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NM NM
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NM$1 NM
terminal(S
rect(l5 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NM$2 NM
terminal(S
rect(l5 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l5 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l1 (-276 -2151) (425 1500))
rect(l1 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l1 (-375 -1450) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l5 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l5 (975 1660) (425 950))
rect(l5 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PM
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PM$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NM
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NM$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l1 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l1 (-226 1049) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l5 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PM$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NM$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l8 (4710 3010) (180 180))
rect(l11 (-850 -240) (610 300))
rect(l1 (-1175 1800) (425 1500))
rect(l1 (-1800 -1500) (425 1500))
rect(l5 (950 -4890) (425 950))
)
net(2
rect(l8 (6510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(3
rect(l8 (8310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(4
rect(l8 (10110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(5
rect(l8 (11910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(6
rect(l8 (13710 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(7
rect(l8 (15510 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(8
rect(l8 (17310 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(9
rect(l8 (19110 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(10
rect(l8 (20910 3010) (180 180))
rect(l11 (-1140 -240) (900 300))
rect(l1 (-1275 1800) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(11 name(FB)
rect(l8 (22710 3010) (180 180))
rect(l8 (-19700 720) (180 180))
rect(l11 (18380 -1140) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
rect(l1 (-245 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l1 (-23025 -2550) (425 1500))
rect(l1 (-400 -1500) (425 1500))
rect(l1 (1275 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l1 (1375 -1500) (425 1500))
rect(l9 (-21975 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
rect(l1 (-625 850) (425 1500))
rect(l5 (-425 -4890) (425 950))
)
net(14 name(ENABLE)
rect(l8 (2510 3010) (180 180))
rect(l11 (-250 -250) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l5 (-23700 460) (425 950))
rect(l5 (1975 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l5 (1375 -950) (425 950))
rect(l10 (-21975 -2210) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(1 1 match)
device(2 2 match)
device(3 3 match)
device(4 4 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(1 1 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
)
)
)

0
testdata/lvs/ringo_simple_simplification.lvsdb → testdata/lvs/ringo_simple_simplification.lvsdb.1 vendored
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1142
testdata/lvs/ringo_simple_simplification.lvsdb.2 vendored Normal file
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0
testdata/lvs/vexriscv.cir.gz → testdata/lvs/vexriscv.cir.gz.1 vendored
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BIN
testdata/lvs/vexriscv.cir.gz.2 vendored Normal file
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