mirror of
https://github.com/KLayout/klayout.git
synced 2026-08-29 01:14:35 +02:00
Added "device_scaling" to LVS
Plus: added some missing files Implementation details: * scaling factor was introduced in DeviceExtractor::extract * for easy implementation this is available in "sdbu" * "sdbu" is made available in GSI * to test this, the db::compare_netlist had to be enhanced to exactly check device parameters * enhancement of LVS script framework and doc updates
This commit is contained in:
Matthias Koefferlein
Vendored
+27
@@ -0,0 +1,27 @@
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.SUBCKT RINGO VSS VDD FB ENABLE OUT
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X$1 VDD 1 VSS VDD FB ENABLE VSS ND2X1
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X$2 VDD 2 VSS VDD 1 VSS INVX1
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X$3 VDD 3 VSS VDD 2 VSS INVX1
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X$4 VDD 4 VSS VDD 3 VSS INVX1
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X$5 VDD 5 VSS VDD 4 VSS INVX1
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X$6 VDD 6 VSS VDD 5 VSS INVX1
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X$7 VDD 7 VSS VDD 6 VSS INVX1
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X$8 VDD 8 VSS VDD 7 VSS INVX1
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X$9 VDD 9 VSS VDD 8 VSS INVX1
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X$10 VDD 10 VSS VDD 9 VSS INVX1
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X$11 VDD FB VSS VDD 10 VSS INVX1
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X$12 VDD OUT VSS VDD FB VSS INVX1
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.ENDS RINGO
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.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK
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M$1 OUT A VDD NWELL PMOS L=0.5U W=3U
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M$2 VDD B OUT NWELL PMOS L=0.5U W=3U
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M$3 VSS A 1 BULK NMOS L=0.5U W=1.9U
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M$4 1 B OUT BULK NMOS L=0.5U W=1.9U
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.ENDS ND2X1
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.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK
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M$1 VDD IN OUT NWELL PMOS L=0.5U W=3U
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M$2 VSS IN OUT BULK NMOS L=0.5U W=1.9U
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.ENDS INVX1
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+83
@@ -0,0 +1,83 @@
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* Extracted by KLayout
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* cell RINGO
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* pin FB
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* pin VDD
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* pin OUT
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* pin ENABLE
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* pin VSS
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.SUBCKT RINGO 11 12 13 14 15
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* net 11 FB
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* net 12 VDD
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* net 13 OUT
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* net 14 ENABLE
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* net 15 VSS
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* cell instance $1 r0 *1 1.8,0
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X$1 12 1 15 12 11 14 15 ND2X1
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* cell instance $2 r0 *1 4.2,0
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X$2 12 2 15 12 1 15 INVX1
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* cell instance $3 r0 *1 6,0
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X$3 12 3 15 12 2 15 INVX1
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* cell instance $4 r0 *1 7.8,0
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X$4 12 4 15 12 3 15 INVX1
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* cell instance $5 r0 *1 9.6,0
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X$5 12 5 15 12 4 15 INVX1
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* cell instance $6 r0 *1 11.4,0
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X$6 12 6 15 12 5 15 INVX1
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* cell instance $7 r0 *1 13.2,0
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X$7 12 7 15 12 6 15 INVX1
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* cell instance $8 r0 *1 15,0
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X$8 12 8 15 12 7 15 INVX1
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* cell instance $9 r0 *1 16.8,0
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X$9 12 9 15 12 8 15 INVX1
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* cell instance $10 r0 *1 18.6,0
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X$10 12 10 15 12 9 15 INVX1
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* cell instance $11 r0 *1 20.4,0
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X$11 12 11 15 12 10 15 INVX1
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* cell instance $12 r0 *1 22.2,0
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X$12 12 13 15 12 11 15 INVX1
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.ENDS RINGO
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* cell INVX1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin IN
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* pin SUBSTRATE
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.SUBCKT INVX1 1 2 3 4 5 6
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* net 1 VDD
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* net 2 OUT
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* net 3 VSS
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* net 5 IN
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* net 6 SUBSTRATE
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* device instance $1 r0 *1 0.85,5.8 PMOS
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M$1 1 5 2 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U
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* device instance $2 r0 *1 0.85,2.135 NMOS
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M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
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.ENDS INVX1
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* cell ND2X1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin B
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* pin A
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* pin SUBSTRATE
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.SUBCKT ND2X1 1 2 3 4 5 6 7
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* net 1 VDD
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* net 2 OUT
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* net 3 VSS
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* net 5 B
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* net 6 A
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* net 7 SUBSTRATE
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* device instance $1 r0 *1 0.85,5.8 PMOS
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M$1 2 6 1 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U
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* device instance $2 r0 *1 1.55,5.8 PMOS
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M$2 1 5 2 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U
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* device instance $3 r0 *1 0.85,2.135 NMOS
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M$3 3 6 8 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U
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* device instance $4 r0 *1 1.55,2.135 NMOS
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M$4 8 5 2 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U
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.ENDS ND2X1
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+76
@@ -0,0 +1,76 @@
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source($lvs_test_source, "RINGO")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("ringo_scaled.cir")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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device_scaling(2.0)
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.simplify
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compare
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+971
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#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12 '10/0')
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layer(l13 '11/0')
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layer(l7)
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layer(l1)
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layer(l9)
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layer(l5)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l1 l9 l5 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l7 l7)
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connect(l1 l8 l1)
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connect(l9 l3 l8 l9)
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connect(l5 l8 l5)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l1 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l1 (125 -750) (450 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(l1 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l1 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$2 PMOS
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terminal(S
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rect(l1 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l1 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l5 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l5 (125 -475) (450 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$1 NMOS
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terminal(S
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rect(l5 (-575 -475) (450 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l5 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$2 NMOS
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terminal(S
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rect(l5 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l5 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Circuit boundary
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rect((-100 400) (2600 7600))
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# Nets with their geometries
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net(1 name(VDD)
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rect(l8 (1110 5160) (180 180))
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rect(l8 (-180 920) (180 180))
|
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rect(l8 (-180 -730) (180 180))
|
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rect(l11 (-240 -790) (300 1700))
|
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rect(l11 (-1350 0) (2400 800))
|
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rect(l11 (-1151 -401) (2 2))
|
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rect(l1 (-276 -2151) (425 1500))
|
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rect(l1 (-400 -1500) (425 1500))
|
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)
|
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net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.5)
|
||||
param(W 3)
|
||||
param(AS 2.55)
|
||||
param(AD 1.35)
|
||||
param(PS 7.7)
|
||||
param(PD 3.9)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.5)
|
||||
param(W 3)
|
||||
param(AS 1.35)
|
||||
param(AD 2.55)
|
||||
param(PS 3.9)
|
||||
param(PD 7.7)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.5)
|
||||
param(W 1.9)
|
||||
param(AS 1.615)
|
||||
param(AD 0.855)
|
||||
param(PS 5.5)
|
||||
param(PD 2.8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.5)
|
||||
param(W 1.9)
|
||||
param(AS 0.855)
|
||||
param(AD 1.615)
|
||||
param(PS 2.8)
|
||||
param(PD 5.5)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.5)
|
||||
param(W 3)
|
||||
param(AS 2.55)
|
||||
param(AD 2.55)
|
||||
param(PS 7.7)
|
||||
param(PD 7.7)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.5)
|
||||
param(W 1.9)
|
||||
param(AS 1.615)
|
||||
param(AD 1.615)
|
||||
param(PS 5.5)
|
||||
param(PD 5.5)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-2550 1800) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.5)
|
||||
param(W 3)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.5)
|
||||
param(W 3)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.5)
|
||||
param(W 1.9)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.5)
|
||||
param(W 1.9)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.5)
|
||||
param(W 3)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.5)
|
||||
param(W 1.9)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
@@ -0,0 +1,102 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
* cell RINGO
|
||||
* pin FB
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin ENABLE
|
||||
* pin VSS
|
||||
.SUBCKT RINGO 5 6 7 8 9
|
||||
* net 5 FB
|
||||
* net 6 VDD
|
||||
* net 7 OUT
|
||||
* net 8 ENABLE
|
||||
* net 9 VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 6 1 9 6 5 8 9 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 6 2 9 6 1 9 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 6 10 9 6 2 9 INVX1
|
||||
* cell instance $4 r0 *1 16.8,0
|
||||
X$4 6 3 9 6 11 9 INVX1
|
||||
* cell instance $5 r0 *1 18.6,0
|
||||
X$5 6 4 9 6 3 9 INVX1
|
||||
* cell instance $6 r0 *1 20.4,0
|
||||
X$6 6 5 9 6 4 9 INVX1
|
||||
* cell instance $7 r0 *1 22.2,0
|
||||
X$7 5 6 7 9 6 9 INVX2
|
||||
* cell instance $17 r0 *1 7.8,0
|
||||
X$17 6 12 9 6 10 9 INVX1
|
||||
* cell instance $18 r0 *1 9.6,0
|
||||
X$18 6 13 9 6 12 9 INVX1
|
||||
* cell instance $19 r0 *1 11.4,0
|
||||
X$19 6 14 9 6 13 9 INVX1
|
||||
* cell instance $20 r0 *1 13.2,0
|
||||
X$20 6 15 9 6 14 9 INVX1
|
||||
* cell instance $21 r0 *1 15,0
|
||||
X$21 6 11 9 6 15 9 INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
* cell INVX2
|
||||
* pin IN
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT INVX2 1 2 3 4 5 6
|
||||
* net 1 IN
|
||||
* net 2 VDD
|
||||
* net 3 OUT
|
||||
* net 4 VSS
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
|
||||
.ENDS INVX2
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT INVX1 1 2 3 4 5 6
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
@@ -0,0 +1,76 @@
|
||||
|
||||
source($lvs_test_source, "RINGO")
|
||||
|
||||
report_lvs($lvs_test_target_lvsdb, true)
|
||||
|
||||
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
|
||||
|
||||
schematic("ringo_for_simplification.cir")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(8, 0)
|
||||
metal1 = input(9, 0)
|
||||
via1 = input(10, 0)
|
||||
metal2 = input(11, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Compare section
|
||||
|
||||
align
|
||||
|
||||
netlist.simplify
|
||||
|
||||
compare
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Vendored
+111
@@ -0,0 +1,111 @@
|
||||
|
||||
source($lvs_test_source)
|
||||
|
||||
# will get pretty big:
|
||||
# report_lvs($lvs_test_target_lvsdb, true)
|
||||
|
||||
target_netlist($lvs_test_target_cir, write_spice(true), "Extracted by KLayout")
|
||||
|
||||
schematic("vexriscv_schematic.cir.gz")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
pactive = input(4, 0)
|
||||
nactive = input(3, 0)
|
||||
ntie = input(5, 0)
|
||||
ptie = input(6, 0)
|
||||
|
||||
poly = input(7, 0)
|
||||
cont = input(10, 0)
|
||||
metal1 = input(11, 0)
|
||||
via1 = input(14, 0)
|
||||
metal2 = input(16, 0)
|
||||
via2 = input(18, 0)
|
||||
metal3 = input(19, 0)
|
||||
via3 = input(21, 0)
|
||||
metal4 = input(22, 0)
|
||||
via4 = input(25, 0)
|
||||
metal5 = input(26, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
poly_cont = cont & poly
|
||||
diff_cont = cont - poly
|
||||
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, diff_cont)
|
||||
connect(nsd, diff_cont)
|
||||
connect(poly, poly_cont)
|
||||
connect(poly_cont, metal1)
|
||||
connect(diff_cont, metal1)
|
||||
connect(diff_cont, ntie)
|
||||
connect(diff_cont, ptie)
|
||||
connect(nwell, ntie)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
connect(metal2, via2)
|
||||
connect(via2, metal3)
|
||||
connect(metal3, via3)
|
||||
connect(via3, metal4)
|
||||
connect(metal4, via4)
|
||||
connect(via4, metal5)
|
||||
|
||||
# Global
|
||||
connect_global(ptie, "BULK")
|
||||
connect_global(bulk, "BULK")
|
||||
|
||||
# Implicit
|
||||
connect_implicit("VDD")
|
||||
connect_implicit("VSS")
|
||||
|
||||
# Compare section
|
||||
|
||||
same_device_classes("PMOS", "TP")
|
||||
same_device_classes("NMOS", "TN")
|
||||
|
||||
# Ignore all caps from the schematic
|
||||
same_device_classes(nil, "CAP")
|
||||
|
||||
# Increase the default complexity from 100 to 200
|
||||
# This is required because the clock tree is incorrect and exhibits manifold ambiguities
|
||||
# (the netlists are just samples, not necessarily functional).
|
||||
# The algorithm needs enough freedom to follow all these branches and different variants.
|
||||
max_branch_complexity(200)
|
||||
|
||||
schematic.combine_devices
|
||||
|
||||
netlist.combine_devices
|
||||
|
||||
align
|
||||
|
||||
if ! compare
|
||||
raise "Netlists don't match"
|
||||
else
|
||||
puts "Congratulations! Netlists match."
|
||||
end
|
||||
|
||||
Reference in New Issue
Block a user