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Updating tests

This commit is contained in:
Matthias Koefferlein 2026-06-30 23:34:43 +02:00
parent 1c560caaa7
commit a9c4808d14
2 changed files with 13 additions and 16 deletions
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12
testdata/lvs/ringo_device_subcircuits_devcls.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
X$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
X$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
X$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
X$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
X$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
X$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

17
testdata/lvs/ringo_device_subcircuits_devcls.lvs vendored
View File

@ -8,21 +8,18 @@ target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
# Register device class with a "X" element based SPICE profile
# schematic only
xpmos = RBA::DeviceClassMOS4Transistor::new
xpmos.name = "XPMOS"
xpmos = mos4_class("XPMOS")
sp = xpmos.spice_profile
sp.element = "X"
xpmos.set_spice_profile(sp)
# layout only
pmos = RBA::DeviceClassMOS4Transistor::new
pmos.name = "PMOS"
pmos = mos4_class("PMOS")
sp = pmos.spice_profile
sp.element = "X"
pmos.set_spice_profile(sp)
nmos = RBA::DeviceClassMOS4Transistor::new
nmos.name = "NMOS"
nmos = mos4_class("NMOS")
sp = nmos.spice_profile
sp.element = "X"
nmos.set_spice_profile(sp)
@ -70,12 +67,12 @@ ptie = active_outside_nwell & pplus
# Device extraction
# PMOS transistor device extraction
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
extract_devices(mos4(pmos), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
# NMOS transistor device extraction
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
extract_devices(mos4(nmos), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
# Define connectivity for netlist extraction