WIP: enable multiple layout versions of one schematic circuit using 'same_circuit'

src/db/db/dbNetlistCompare.cc

@@ -492,10 +492,11 @@ public:
     if (ca && has_cat_for (ca)) {
       throw tl::Exception (tl::to_string (tr ("Circuit is already paired with other circuit: ")) + ca->name ());
     }
+#if 0 //  can pair multiple layout cells with one schematic circuit
     if (cb && has_cat_for (cb)) {
       throw tl::Exception (tl::to_string (tr ("Circuit is already paired with other circuit: ")) + cb->name ());
     }
-
+#endif
     generic_categorizer<db::Circuit>::same (ca, cb);
   }
 
@@ -2274,13 +2275,13 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
 
   bool good = true;
 
-  std::map<size_t, std::pair<const db::Circuit *, const db::Circuit *> > cat2circuits;
+  std::map<size_t, std::pair<std::vector<const db::Circuit *>, std::vector<const db::Circuit *> > > cat2circuits;
   std::set<const db::Circuit *> verified_circuits_a, verified_circuits_b;
 
   for (db::Netlist::const_circuit_iterator i = a->begin_circuits (); i != a->end_circuits (); ++i) {
     size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ());
     if (cat) {
-      cat2circuits[cat].first = i.operator-> ();
+      cat2circuits[cat].first.push_back (i.operator-> ());
     } else {
       //  skip circuit (but count it as verified)
       verified_circuits_a.insert (i.operator-> ());
@@ -2290,7 +2291,7 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
   for (db::Netlist::const_circuit_iterator i = b->begin_circuits (); i != b->end_circuits (); ++i) {
     size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ());
     if (cat) {
-      cat2circuits[cat].second = i.operator-> ();
+      cat2circuits[cat].second.push_back (i.operator-> ());
     } else {
       //  skip circuit (but count it as verified)
       verified_circuits_b.insert (i.operator-> ());
@@ -2342,11 +2343,21 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
 
   //  check for circuits that don't match
 
-  for (std::map<size_t, std::pair<const db::Circuit *, const db::Circuit *> >::const_iterator i = cat2circuits.begin (); i != cat2circuits.end (); ++i) {
+  for (std::map<size_t, std::pair<std::vector<const db::Circuit *>, std::vector<const db::Circuit *> > >::const_iterator i = cat2circuits.begin (); i != cat2circuits.end (); ++i) {
-    if (! i->second.first || ! i->second.second) {
+    if (i->second.first.empty ()) {
       good = false;
       if (mp_logger) {
-        mp_logger->circuit_mismatch (i->second.first, i->second.second);
+        for (std::vector<const db::Circuit *>::const_iterator j = i->second.second.begin (); j != i->second.second.end (); ++j) {
+          mp_logger->circuit_mismatch (0, *j);
+        }
+      }
+    }
+    if (i->second.second.empty ()) {
+      good = false;
+      if (mp_logger) {
+        for (std::vector<const db::Circuit *>::const_iterator j = i->second.first.begin (); j != i->second.first.end (); ++j) {
+          mp_logger->circuit_mismatch (*j, 0);
+        }
       }
     }
   }
@@ -2355,18 +2366,23 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
 
   for (db::Netlist::const_bottom_up_circuit_iterator c = a->begin_bottom_up (); c != a->end_bottom_up (); ++c) {
 
-    size_t ccat = circuit_categorizer.cat_for_circuit (c.operator-> ());
+    const db::Circuit *ca = c.operator-> ();
+
+    size_t ccat = circuit_categorizer.cat_for_circuit (ca);
     if (! ccat) {
       continue;
     }
 
-    std::map<size_t, std::pair<const db::Circuit *, const db::Circuit *> >::const_iterator i = cat2circuits.find (ccat);
+    std::map<size_t, std::pair<std::vector<const db::Circuit *>, std::vector<const db::Circuit *> > >::const_iterator i = cat2circuits.find (ccat);
     tl_assert (i != cat2circuits.end ());
+    tl_assert (! i->second.first.empty ());
+    if (i->second.second.empty ()) {
+      continue;
+    }
 
-    if (i->second.first && i->second.second) {
+    //  NOTE: there can only be one schematic circuit
-
+    tl_assert (i->second.second.size () == size_t (1));
-      const db::Circuit *ca = i->second.first;
+    const db::Circuit *cb = i->second.second.front ();
-      const db::Circuit *cb = i->second.second;
 
     std::vector<std::pair<const Net *, const Net *> > empty;
     const std::vector<std::pair<const Net *, const Net *> > *net_identity = &empty;
@@ -2412,8 +2428,6 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const
 
   }
 
-  }
-
   if (mp_logger) {
     mp_logger->end_netlist (a, b);
   }

src/lvs/unit_tests/lvsSimpleTests.cc

@@ -154,3 +154,9 @@ TEST(16_floating)
 {
   run_test (_this, "floating", "floating.gds", false, "TOP");
 }
+
+TEST(17_layout_variants)
+{
+  run_test (_this, "ringo_layout_var", "ringo_layout_var.gds");
+}
+

testdata/lvs/ringo_layout_var.cir

@@ -0,0 +1,102 @@
+* Extracted by KLayout
+
+* cell RINGO
+* pin FB
+* pin VDD
+* pin OUT
+* pin ENABLE
+* pin VSS
+.SUBCKT RINGO 11 12 13 14 15
+* net 11 FB
+* net 12 VDD
+* net 13 OUT
+* net 14 ENABLE
+* net 15 VSS
+* cell instance $1 r0 *1 1.8,0
+X$1 12 1 15 12 11 14 15 ND2X1
+* cell instance $2 r0 *1 4.2,0
+X$2 12 2 15 12 1 15 INVX1B
+* cell instance $3 r0 *1 6,0
+X$3 12 3 15 12 2 15 INVX1
+* cell instance $4 r0 *1 7.8,0
+X$4 12 4 15 12 3 15 INVX1B
+* cell instance $5 r0 *1 9.6,0
+X$5 12 5 15 12 4 15 INVX1
+* cell instance $6 r0 *1 11.4,0
+X$6 12 6 15 12 5 15 INVX1B
+* cell instance $7 r0 *1 13.2,0
+X$7 12 7 15 12 6 15 INVX1
+* cell instance $8 r0 *1 15,0
+X$8 12 8 15 12 7 15 INVX1
+* cell instance $9 r0 *1 16.8,0
+X$9 12 9 15 12 8 15 INVX1
+* cell instance $10 r0 *1 18.6,0
+X$10 12 10 15 12 9 15 INVX1
+* cell instance $11 r0 *1 20.4,0
+X$11 12 11 15 12 10 15 INVX1
+* cell instance $12 r0 *1 22.2,0
+X$12 12 13 15 12 11 15 INVX1
+.ENDS RINGO
+
+* cell INVX1B
+* pin VDD
+* pin OUT
+* pin VSS
+* pin 
+* pin IN
+* pin SUBSTRATE
+.SUBCKT INVX1B 1 2 3 4 5 6
+* net 1 VDD
+* net 2 OUT
+* net 3 VSS
+* net 5 IN
+* net 6 SUBSTRATE
+* device instance $1 r0 *1 0.85,5.8 PMOS
+M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
+* device instance $2 r0 *1 0.85,2.135 NMOS
+M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+.ENDS INVX1B
+
+* cell INVX1
+* pin VDD
+* pin OUT
+* pin VSS
+* pin 
+* pin IN
+* pin SUBSTRATE
+.SUBCKT INVX1 1 2 3 4 5 6
+* net 1 VDD
+* net 2 OUT
+* net 3 VSS
+* net 5 IN
+* net 6 SUBSTRATE
+* device instance $1 r0 *1 0.85,5.8 PMOS
+M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
+* device instance $2 r0 *1 0.85,2.135 NMOS
+M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+.ENDS INVX1
+
+* cell ND2X1
+* pin VDD
+* pin OUT
+* pin VSS
+* pin 
+* pin B
+* pin A
+* pin SUBSTRATE
+.SUBCKT ND2X1 1 2 3 4 5 6 7
+* net 1 VDD
+* net 2 OUT
+* net 3 VSS
+* net 5 B
+* net 6 A
+* net 7 SUBSTRATE
+* device instance $1 r0 *1 0.85,5.8 PMOS
+M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
+* device instance $2 r0 *1 1.55,5.8 PMOS
+M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
+* device instance $3 r0 *1 0.85,2.135 NMOS
+M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
+* device instance $4 r0 *1 1.55,2.135 NMOS
+M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
+.ENDS ND2X1

testdata/lvs/ringo_layout_var.lvs

@@ -0,0 +1,78 @@
+
+source($lvs_test_source, "RINGO")
+
+report_lvs($lvs_test_target_lvsdb, true)
+
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("ringo.cir")
+
+deep
+
+# Drawing layers
+
+nwell       = input(1, 0)
+active      = input(2, 0)
+pplus       = input(3, 0)
+nplus       = input(4, 0)
+poly        = input(5, 0)
+contact     = input(8, 0)
+metal1      = input(9, 0)
+via1        = input(10, 0)
+metal2      = input(11, 0)
+
+# Bulk layer for terminal provisioning
+
+bulk        = polygon_layer
+
+# Computed layers
+
+active_in_nwell       = active & nwell
+pactive               = active_in_nwell & pplus
+pgate                 = pactive & poly
+psd                   = pactive - pgate
+ntie                  = active_in_nwell & nplus
+
+active_outside_nwell  = active - nwell
+nactive               = active_outside_nwell & nplus
+ngate                 = nactive & poly
+nsd                   = nactive - ngate
+ptie                  = active_outside_nwell & pplus
+
+# Device extraction
+
+# PMOS transistor device extraction
+extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, 
+                                "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
+
+# NMOS transistor device extraction
+extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, 
+                                "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(psd,        contact)
+connect(nsd,        contact)
+connect(poly,       contact)
+connect(ntie,       contact)
+connect(nwell,      ntie)
+connect(ptie,       contact)
+connect(contact,    metal1)
+connect(metal1,     via1)
+connect(via1,       metal2)
+
+# Global
+connect_global(bulk, "SUBSTRATE")
+connect_global(ptie, "SUBSTRATE")
+
+# Compare section
+
+netlist.simplify
+
+# both INVX1 and INVX1B are the same schematic cell
+same_circuits("INVX1", "INVX1")
+same_circuits("INVX1B", "INVX1")
+
+compare
+