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Unique net names for Spice netlist writer

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This commit is contained in:
Matthias Koefferlein
2019-05-31 22:19:51 +02:00
parent c684633dd6
commit 985cffc099
11 changed files with 357 additions and 7 deletions
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testdata/algo/nwriter12_au.txt
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* written by unit test
* cell SUBCKT
* pin
* pin A
* pin V42
* pin Z
* pin gnd
* pin gnd
.SUBCKT SUBCKT 1 2 4 5 6 7
* net 2 A
* net 4 V42
* net 5 Z
* net 6 gnd
* net 7 gnd
* device instance $1 r0 *1 0,0 HVPMOS
XD_$1 4 3 5 1 HVPMOS PARAMS: L=0.2 W=1 AS=0.18 AD=0.18 PS=2.16 PD=2.16
* device instance $2 r0 *1 0,0 HVPMOS
XD_$2 4 2 3 1 HVPMOS PARAMS: L=0.2 W=1 AS=0.18 AD=0.18 PS=2.16 PD=2.16
* device instance $3 r0 *1 0,0 HVNMOS
XD_$3 6 3 6 7 HVNMOS PARAMS: L=1.13 W=2.12 PS=6 PD=6 AS=0 AD=0
* device instance $4 r0 *1 0,0 HVNMOS
XD_$4 6 3 5 7 HVNMOS PARAMS: L=0.4 W=0.4 PS=1.16 PD=1.16 AS=0.19 AD=0.19
* device instance $5 r0 *1 0,0 HVNMOS
XD_$5 6 2 3 7 HVNMOS PARAMS: L=0.4 W=0.4 PS=1.76 PD=1.76 AS=0.19 AD=0.19
.ENDS SUBCKT
testdata/algo/nwriter12b_au.txt
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* written by unit test
* cell SUBCKT
* pin
* pin A
* pin V42
* pin Z
* pin gnd
* pin gnd
.SUBCKT SUBCKT \$1 A V42 Z gnd gnd$1
* device instance $1 r0 *1 0,0 HVPMOS
XD_$1 V42 \$3 Z \$1 HVPMOS PARAMS: L=0.2 W=1 AS=0.18 AD=0.18 PS=2.16 PD=2.16
* device instance $2 r0 *1 0,0 HVPMOS
XD_$2 V42 A \$3 \$1 HVPMOS PARAMS: L=0.2 W=1 AS=0.18 AD=0.18 PS=2.16 PD=2.16
* device instance $3 r0 *1 0,0 HVNMOS
XD_$3 gnd \$3 gnd gnd$1 HVNMOS PARAMS: L=1.13 W=2.12 PS=6 PD=6 AS=0 AD=0
* device instance $4 r0 *1 0,0 HVNMOS
XD_$4 gnd \$3 Z gnd$1 HVNMOS PARAMS: L=0.4 W=0.4 PS=1.16 PD=1.16 AS=0.19 AD=0.19
* device instance $5 r0 *1 0,0 HVNMOS
XD_$5 gnd A \$3 gnd$1 HVNMOS PARAMS: L=0.4 W=0.4 PS=1.76 PD=1.76 AS=0.19 AD=0.19
.ENDS SUBCKT
testdata/algo/same_net_names.l2n
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#%l2n-klayout
W(CIRCUIT)
U(0.001)
D(D$HVPMOS HVPMOS
T(S
)
T(G
)
T(D
)
T(B
)
)
D(D$HVNMOS HVNMOS
T(S
)
T(G
)
T(D
)
T(B
)
)
X(SUBCKT
N(1
)
N(2 I(A)
)
N(3
)
N(4 I(V42)
)
N(5 I(Z)
)
N(6 I(gnd)
)
N(7 I(gnd)
)
P(1)
P(2 I(A))
P(4 I(V42))
P(5 I(Z))
P(6 I(gnd))
P(7 I(gnd))
D(1 D$HVPMOS
E(L 0.2)
E(W 1)
E(AS 0.18)
E(AD 0.18)
E(PS 2.16)
E(PD 2.16)
T(S 4)
T(G 3)
T(D 5)
T(B 1)
)
D(2 D$HVPMOS
E(L 0.2)
E(W 1)
E(AS 0.18)
E(AD 0.18)
E(PS 2.16)
E(PD 2.16)
T(S 4)
T(G 2)
T(D 3)
T(B 1)
)
D(3 D$HVNMOS
E(L 1.13)
E(W 2.12)
E(PS 6)
E(PD 6)
T(S 6)
T(G 3)
T(D 6)
T(B 7)
)
D(4 D$HVNMOS
E(L 0.4)
E(W 0.4)
E(AS 0.19)
E(AD 0.19)
E(PS 1.16)
E(PD 1.16)
T(S 6)
T(G 3)
T(D 5)
T(B 7)
)
D(5 D$HVNMOS
E(L 0.4)
E(W 0.4)
E(AS 0.19)
E(AD 0.19)
E(PS 1.76)
E(PD 1.76)
T(S 6)
T(G 2)
T(D 3)
T(B 7)
)
)