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Adapted test data to 0.26.

This commit is contained in:
Matthias Koefferlein 2021-01-31 20:04:06 +01:00
parent 47d9001ba6
commit 881479636f
1 changed files with 5 additions and 5 deletions
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10
testdata/lvs/empty_subcells.lvsdb vendored
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@ -18,7 +18,7 @@ layout(
connect(l1 l1 l2) connect(l1 l1 l2)
connect(l2 l1 l2 l3) connect(l2 l1 l2 l3)
connect(l3 l2 l3 l4) connect(l3 l2 l3 l4)
connect(l4 l3) connect(l4 l3 l4)
# Circuit section # Circuit section
# Circuits are the hierarchical building blocks of the netlist. # Circuits are the hierarchical building blocks of the netlist.
@ -30,11 +30,11 @@ layout(
# Nets with their geometries # Nets with their geometries
net(1 name(A) net(1 name(A)
rect(l3 (100 60) (30 30)) rect(l3 (100 60) (30 30))
text(l4 A (-10 -10)) rect(l4 (-11 -11) (2 2))
) )
net(2 name(B) net(2 name(B)
rect(l3 (100 10) (30 30)) rect(l3 (100 10) (30 30))
text(l4 B (-10 -10)) rect(l4 (-11 -11) (2 2))
) )
# Outgoing pins and their connections to nets # Outgoing pins and their connections to nets
@ -50,11 +50,11 @@ layout(
# Nets with their geometries # Nets with their geometries
net(1 name(V) net(1 name(V)
rect(l3 (100 60) (30 30)) rect(l3 (100 60) (30 30))
text(l4 V (-10 -10)) rect(l4 (-11 -11) (2 2))
) )
net(2 name(W) net(2 name(W)
rect(l3 (100 10) (30 30)) rect(l3 (100 10) (30 30))
text(l4 W (-10 -10)) rect(l4 (-11 -11) (2 2))
) )
# Outgoing pins and their connections to nets # Outgoing pins and their connections to nets