mirror of https://github.com/KLayout/klayout.git
LEF/DEF: Fixed placement of FOREIGN cell
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parent
9f17a819b2
commit
751340c963
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@ -827,17 +827,19 @@ LEFImporter::read_macro (Layout &layout)
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layout.cell (ci).set_ghost_cell (true);
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layout.cell (ci).set_ghost_cell (true);
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}
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}
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db::Point origin;
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db::Point vec;
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db::FTrans ft;
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db::FTrans ft;
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if (! peek (";")) {
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if (! peek (";")) {
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origin = get_point (1.0 / layout.dbu ());
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vec = get_point (1.0 / layout.dbu ());
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ft = get_orient (true);
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ft = get_orient (true);
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}
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}
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expect (";");
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expect (";");
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foreign_cell = &layout.cell (ci);
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foreign_cell = &layout.cell (ci);
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foreign_trans = (db::Trans (origin - db::Point ()) * db::Trans (ft)).inverted ();
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// What is the definition of the FOREIGN transformation?
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// Guessing: this transformation moves the lower-left origin to 0,0
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foreign_trans = db::Trans (db::Point () - vec) * db::Trans (ft);
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foreign_name = cn;
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foreign_name = cn;
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} else if (test ("OBS")) {
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} else if (test ("OBS")) {
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@ -899,7 +901,7 @@ LEFImporter::read_macro (Layout &layout)
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cell.clear_insts ();
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cell.clear_insts ();
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cell.insert (db::CellInstArray (db::CellInst (foreign_cell->cell_index ()), foreign_trans));
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cell.insert (db::CellInstArray (db::CellInst (foreign_cell->cell_index ()), db::Trans (db::Point () - origin) * foreign_trans));
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m_macros_by_name.insert (std::make_pair (mn, std::make_pair (&cell, db::Trans ())));
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m_macros_by_name.insert (std::make_pair (mn, std::make_pair (&cell, db::Trans ())));
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} else {
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} else {
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@ -907,7 +909,7 @@ LEFImporter::read_macro (Layout &layout)
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// use FOREIGN cell instead of new one
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// use FOREIGN cell instead of new one
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layout.delete_cell (cell.cell_index ());
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layout.delete_cell (cell.cell_index ());
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m_macros_by_name.insert (std::make_pair (mn, std::make_pair (foreign_cell, foreign_trans)));
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m_macros_by_name.insert (std::make_pair (mn, std::make_pair (foreign_cell, db::Trans (db::Point () - origin) * foreign_trans)));
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}
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}
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@ -9,7 +9,7 @@ DIEAREA ( 0 0 ) ( 1000 2000 ) ;
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COMPONENTS 3 ;
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COMPONENTS 3 ;
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- macro1 macro1 + PLACED ( 0 0 ) N ;
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- macro1 macro1 + PLACED ( 0 0 ) N ;
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- macro2 macro2 + PLACED ( 0 500 ) N ;
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- macro2 macro2 + PLACED ( 0 500 ) E ;
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- macro3 macro3 + PLACED ( 0 1000 ) N ;
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- macro3 macro3 + PLACED ( 0 1000 ) N ;
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END COMPONENTS
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END COMPONENTS
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@ -1,48 +1,21 @@
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MACRO macro1
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MACRO macro1
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CLASS CORE ;
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CLASS CORE ;
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FOREIGN foreign1 0.5 -0.2 W ;
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FOREIGN foreign1 0.13 0.5 W ;
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ORIGIN 0.000 0.000 ;
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ORIGIN 0.035 0.235 ;
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SIZE 0.384 BY 0.480 ;
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SIZE 0.07 BY 0.47 ;
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PIN Z
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PORT
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LAYER M1 ;
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RECT 0.306 0.357 0.318 0.403 ;
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RECT 0.318 0.115 0.352 0.403 ;
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VIA 0.336 0.167 square ;
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VIA 0.336 0.351 square ;
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END
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END Z
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END macro1
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END macro1
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MACRO macro2
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MACRO macro2
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CLASS CORE ;
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CLASS CORE ;
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FOREIGN foreign2 -0.15 0.25 ;
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FOREIGN foreign2 -0.15 0.25 ;
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ORIGIN 0.000 0.000 ;
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ORIGIN 0.235 0.035 ;
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SIZE 0.384 BY 0.480 ;
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SIZE 0.47 BY 0.07 ;
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PIN Z
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PORT
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LAYER M1 ;
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RECT 0.306 0.357 0.318 0.403 ;
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RECT 0.318 0.115 0.352 0.403 ;
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VIA 0.336 0.167 square ;
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VIA 0.336 0.351 square ;
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END
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END Z
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END macro2
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END macro2
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MACRO macro3
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MACRO macro3
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CLASS CORE ;
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CLASS CORE ;
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FOREIGN macro3 ;
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FOREIGN macro3 -1.0 1.0 ;
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ORIGIN 0.000 0.000 ;
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ORIGIN 0.0 0.0 ;
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SIZE 0.384 BY 0.480 ;
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SIZE 1.0 BY 0.4 ;
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PIN Z
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PORT
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LAYER M1 ;
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RECT 0.306 0.357 0.318 0.403 ;
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RECT 0.318 0.115 0.352 0.403 ;
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VIA 0.336 0.167 square ;
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VIA 0.336 0.351 square ;
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END
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END Z
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END macro3
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END macro3
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@ -1,46 +1,43 @@
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MACRO macro1
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MACRO macro1
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CLASS CORE ;
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CLASS CORE ;
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ORIGIN 0.000 0.000 ;
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ORIGIN 0.035 0.235 ;
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SIZE 0.384 BY 0.480 ;
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SIZE 0.07 BY 0.47 ;
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PIN Z
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PIN Z
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PORT
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PORT
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LAYER M1 ;
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LAYER M1 ;
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RECT 0.306 0.357 0.318 0.403 ;
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RECT -0.02 0 0.02 0.2 ;
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RECT 0.318 0.115 0.352 0.403 ;
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RECT -0.03 -0.2 0.01 -0.1 ;
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VIA 0.336 0.167 square ;
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VIA 0.0 0.2 square ;
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VIA 0.336 0.351 square ;
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VIA 0.01 -0.2 square ;
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END
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END
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END Z
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END Z
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END macro1
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END macro1
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MACRO macro2
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MACRO macro2
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CLASS CORE ;
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CLASS CORE ;
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FOREIGN foreign2 -0.15 0.25 ;
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FOREIGN foreign2 -0.15 0.25 ;
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ORIGIN 0.000 0.000 ;
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ORIGIN 0.235 0.035 ;
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SIZE 0.384 BY 0.480 ;
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SIZE 0.47 BY 0.07 ;
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PIN Z
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PIN Z
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PORT
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PORT
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LAYER M1 ;
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LAYER M1 ;
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RECT 0.306 0.357 0.318 0.403 ;
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RECT 0 -0.02 -0.2 0.02 ;
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RECT 0.318 0.115 0.352 0.403 ;
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RECT 0.2 -0.03 0.1 0.01 ;
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VIA 0.336 0.167 square ;
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VIA -0.2 0.0 square ;
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VIA 0.336 0.351 square ;
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VIA 0.2 0.01 square ;
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END
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END
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END Z
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END Z
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END macro2
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END macro2
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MACRO macro3
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MACRO macro3
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CLASS CORE ;
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CLASS CORE ;
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FOREIGN macro3 ;
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FOREIGN macro3 -1.0 1.0 ;
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ORIGIN 0.000 0.000 ;
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ORIGIN 0.0 0.0 ;
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SIZE 0.384 BY 0.480 ;
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SIZE 1.0 BY 1.0 ;
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PIN Z
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PIN Z
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PORT
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PORT
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LAYER M1 ;
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LAYER M1 ;
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RECT 0.306 0.357 0.318 0.403 ;
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RECT 0.2 0.2 0.3 0.5 ;
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RECT 0.318 0.115 0.352 0.403 ;
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VIA 0.336 0.167 square ;
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VIA 0.336 0.351 square ;
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END
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END
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END Z
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END Z
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END macro3
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END macro3
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