mirror of
https://github.com/KLayout/klayout.git
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Put more amphasis on net names to resolve ambiguities
The problem was that with the floating test case, the ambiguity resolution sometimes assigned the wrong pins and floating pins/connected pins were swapped. One option is to make the ambiguity resolver consider the pin connection state when tenatively evaluating nodes. Another option is to put more emphasis on net names and use them for ambiguity resolution. This has helped here.
This commit is contained in:
Matthias Koefferlein
Vendored
+50
@@ -0,0 +1,50 @@
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* Extracted by KLayout
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* cell TOP
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* pin A
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* pin C
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* pin SUBSTRATE
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.SUBCKT TOP 2 3 4
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* net 2 A
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* net 3 C
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* net 4 SUBSTRATE
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* cell instance $1 r0 *1 0,0
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X$1 2 3 1 6 4 DINV
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* cell instance $2 r0 *1 3.6,0
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X$2 5 6 1 4 INVX1
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.ENDS TOP
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* cell DINV
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* pin A<1>
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* pin A<2>
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* pin B<2>
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* pin VDD
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* pin VSS
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.SUBCKT DINV 1 2 3 5 6
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* net 1 A<1>
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* net 2 A<2>
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* net 3 B<2>
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* net 4 B<1>
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* net 5 VDD
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* net 6 VSS
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* cell instance $1 r0 *1 0,0
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X$1 4 5 1 6 INVX1
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* cell instance $2 r0 *1 1.8,0
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X$2 3 5 2 6 INVX1
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.ENDS DINV
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* cell INVX1
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* pin OUT
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* pin VDD
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* pin IN
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* pin VSS
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.SUBCKT INVX1 1 2 3 4
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* net 1 OUT
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* net 2 VDD
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* net 3 IN
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* net 4 VSS
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* device instance $1 r0 *1 0.85,2.135 NMOS
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M$1 4 3 1 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
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* device instance $2 r0 *1 0.85,5.8 PMOS
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M$2 2 3 1 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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.ENDS INVX1
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Vendored
BIN
Binary file not shown.
Vendored
+75
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source($lvs_test_source, $lvs_test_top)
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("floating_ref.cir")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.simplify
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align
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compare
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Vendored
+454
@@ -0,0 +1,454 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(TOP)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12 '5/0')
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layer(l13 '5/0')
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layer(l7)
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l7 l7)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l2 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l6 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INVX1
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# Circuit boundary
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rect((-100 400) (2000 7600))
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# Nets with their geometries
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net(1 name(OUT)
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rect(l8 (1110 5160) (180 180))
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rect(l8 (-180 920) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -4120) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -790) (300 4790))
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rect(l11 (-151 -2501) (2 2))
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rect(l2 (-226 1049) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(2 name(VDD)
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rect(l3 (-100 4500) (2000 3500))
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rect(l8 (-1090 -890) (180 180))
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rect(l8 (-580 -1030) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l11 (-590 1460) (1800 800))
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rect(l11 (-1050 -550) (300 300))
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rect(l11 (-700 -850) (300 300))
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rect(l11 (299 499) (2 2))
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rect(l11 (-601 -2201) (300 1400))
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rect(l2 (-350 -1450) (425 1500))
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rect(l9 (-75 450) (500 500))
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)
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net(3 name(IN)
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rect(l4 (725 2860) (250 1940))
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rect(l4 (-525 -1850) (300 300))
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rect(l4 (-25 -1840) (250 1450))
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rect(l4 (-250 1940) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l8 (-465 -3790) (180 180))
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rect(l11 (-91 -91) (2 2))
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rect(l11 (-151 -151) (300 300))
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)
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net(4 name(VSS)
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rect(l8 (810 710) (180 180))
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rect(l8 (-580 880) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-590 -2100) (1800 800))
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rect(l11 (-1050 -550) (300 300))
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rect(l11 (-101 -151) (2 2))
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rect(l11 (-601 399) (300 1360))
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rect(l6 (-350 -900) (425 950))
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rect(l10 (-75 -2010) (500 400))
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)
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# Outgoing pins and their connections to nets
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pin(1 name(OUT))
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pin(2 name(VDD))
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pin(3 name(IN))
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pin(4 name(VSS))
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# Devices and their connections
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device(1 D$NMOS
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location(850 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.40375)
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param(AD 0.40375)
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param(PS 2.75)
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param(PD 2.75)
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terminal(S 4)
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terminal(G 3)
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terminal(D 1)
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terminal(B 4)
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)
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device(2 D$PMOS
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location(850 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.6375)
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param(AD 0.6375)
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param(PS 3.85)
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param(PD 3.85)
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terminal(S 2)
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terminal(G 3)
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terminal(D 1)
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terminal(B 2)
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)
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)
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circuit(DINV
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# Circuit boundary
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rect((-100 400) (3800 7600))
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# Nets with their geometries
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net(1 name('A<1>')
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rect(l8 (510 3010) (180 180))
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rect(l11 (-91 -91) (2 2))
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)
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net(2 name('A<2>')
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rect(l8 (2310 3010) (180 180))
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rect(l11 (-91 -91) (2 2))
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)
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net(3 name('B<2>')
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rect(l11 (2999 3999) (2 2))
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rect(l2 (-226 1049) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(4 name('B<1>')
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rect(l11 (1199 3999) (2 2))
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rect(l2 (-226 1049) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(5 name(VDD)
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rect(l11 (1799 7199) (2 2))
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rect(l2 (299 -2151) (425 1500))
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rect(l2 (-2225 -1500) (425 1500))
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)
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net(6 name(VSS)
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rect(l11 (1799 799) (2 2))
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rect(l6 (299 859) (425 950))
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rect(l6 (-2225 -950) (425 950))
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)
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# Outgoing pins and their connections to nets
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pin(1 name('A<1>'))
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pin(2 name('A<2>'))
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pin(3 name('B<2>'))
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pin(5 name(VDD))
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pin(6 name(VSS))
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# Subcircuits and their connections
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circuit(1 INVX1 location(0 0)
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pin(0 4)
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pin(1 5)
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pin(2 1)
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pin(3 6)
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)
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circuit(2 INVX1 location(1800 0)
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pin(0 3)
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pin(1 5)
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pin(2 2)
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pin(3 6)
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)
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)
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circuit(TOP
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# Circuit boundary
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rect((-100 400) (5600 7600))
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# Nets with their geometries
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net(1
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rect(l8 (4110 3010) (180 180))
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rect(l11 (-1190 -240) (950 300))
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rect(l2 (-1275 1800) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(2 name(A)
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rect(l8 (510 3010) (180 180))
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rect(l11 (-91 -91) (2 2))
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)
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net(3 name(C)
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rect(l8 (2310 3010) (180 180))
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rect(l11 (-91 -91) (2 2))
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)
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net(4 name(SUBSTRATE)
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rect(l6 (3900 1660) (425 950))
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rect(l6 (-2225 -950) (425 950))
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rect(l6 (-2225 -950) (425 950))
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)
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net(5
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rect(l2 (4575 5050) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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||||
)
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net(6
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rect(l2 (3900 5050) (425 1500))
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||||
rect(l2 (-2225 -1500) (425 1500))
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||||
rect(l2 (-2225 -1500) (425 1500))
|
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)
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|
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# Outgoing pins and their connections to nets
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pin(2 name(A))
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pin(3 name(C))
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pin(4 name(SUBSTRATE))
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# Subcircuits and their connections
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circuit(1 DINV location(0 0)
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pin(0 2)
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pin(1 3)
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pin(2 1)
|
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pin(3 6)
|
||||
pin(4 4)
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||||
)
|
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circuit(2 INVX1 location(3600 0)
|
||||
pin(0 5)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 4)
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||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
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# Reference netlist
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||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(NMOS MOS4)
|
||||
class(PMOS MOS4)
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||||
|
||||
# Circuit section
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||||
# Circuits are the hierarchical building blocks of the netlist.
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circuit(INVX1
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||||
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||||
# Nets
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||||
net(1 name(A))
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||||
net(2 name(Z))
|
||||
net(3 name(VDD))
|
||||
net(4 name(VSS))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(A))
|
||||
pin(2 name(Z))
|
||||
pin(3 name(VDD))
|
||||
pin(4 name(VSS))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 NMOS
|
||||
name('0')
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 1)
|
||||
terminal(D 4)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name('1')
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 3)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(DINV
|
||||
|
||||
# Nets
|
||||
net(1 name('A<1>'))
|
||||
net(2 name('A<2>'))
|
||||
net(3 name('B<1>'))
|
||||
net(4 name('B<2>'))
|
||||
net(5 name(VDD))
|
||||
net(6 name(VSS))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('A<1>'))
|
||||
pin(2 name('A<2>'))
|
||||
pin(3 name('B<1>'))
|
||||
pin(4 name('B<2>'))
|
||||
pin(5 name(VDD))
|
||||
pin(6 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INVX1 name(A)
|
||||
pin(0 1)
|
||||
pin(1 3)
|
||||
pin(2 5)
|
||||
pin(3 6)
|
||||
)
|
||||
circuit(2 INVX1 name(B)
|
||||
pin(0 2)
|
||||
pin(1 4)
|
||||
pin(2 5)
|
||||
pin(3 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(TOP
|
||||
|
||||
# Nets
|
||||
net(1 name(A))
|
||||
net(2 name(C))
|
||||
net(3 name(D))
|
||||
net(4 name(VDD))
|
||||
net(5 name(VSS))
|
||||
net(6 name(B))
|
||||
net(7 name(E))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(A))
|
||||
pin(2 name(C))
|
||||
pin(3 name(D))
|
||||
pin(4 name(VDD))
|
||||
pin(5 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 DINV name('0')
|
||||
pin(0 1)
|
||||
pin(1 2)
|
||||
pin(2 6)
|
||||
pin(3 7)
|
||||
pin(4 4)
|
||||
pin(5 5)
|
||||
)
|
||||
circuit(2 INVX1 name('1')
|
||||
pin(0 7)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 5)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(DINV DINV match
|
||||
xref(
|
||||
net(1 1 match)
|
||||
net(2 2 match)
|
||||
net(4 3 warning)
|
||||
net(3 4 warning)
|
||||
net(5 5 match)
|
||||
net(6 6 match)
|
||||
pin(() 2 match)
|
||||
pin(0 0 match)
|
||||
pin(1 1 match)
|
||||
pin(2 3 match)
|
||||
pin(3 4 match)
|
||||
pin(4 5 match)
|
||||
circuit(1 1 match)
|
||||
circuit(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(3 1 match)
|
||||
net(1 2 match)
|
||||
net(2 3 match)
|
||||
net(4 4 match)
|
||||
pin(2 0 match)
|
||||
pin(0 1 match)
|
||||
pin(1 2 match)
|
||||
pin(3 3 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(TOP TOP match
|
||||
xref(
|
||||
net(5 3 match)
|
||||
net(1 7 match)
|
||||
net(6 4 match)
|
||||
net(2 1 match)
|
||||
net(3 2 match)
|
||||
net(4 5 match)
|
||||
pin(() 2 match)
|
||||
pin(() 3 match)
|
||||
pin(0 0 match)
|
||||
pin(1 1 match)
|
||||
pin(2 4 match)
|
||||
circuit(1 1 match)
|
||||
circuit(2 2 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Vendored
+16
@@ -0,0 +1,16 @@
|
||||
.global VDD VSS
|
||||
|
||||
.subckt TOP A C D
|
||||
X0 A C B E DINV
|
||||
X1 E D INVX1
|
||||
.ends
|
||||
|
||||
.subckt DINV A<1> A<2> B<1> B<2>
|
||||
XA A<1> B<1> INVX1
|
||||
XB A<2> B<2> INVX1
|
||||
.ends
|
||||
|
||||
.subckt INVX1 A Z
|
||||
M0 Z A VSS VSS NMOS W=0.95U L=0.25U
|
||||
M1 Z A VDD VDD PMOS W=1.5U L=0.25U
|
||||
.ends
|
||||
+4
-4
@@ -530,13 +530,13 @@ xref(
|
||||
net(8 4 match)
|
||||
net(5 3 match)
|
||||
net(7 5 match)
|
||||
net(6 1 warning)
|
||||
net(9 2 warning)
|
||||
net(6 2 warning)
|
||||
net(9 1 warning)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 0 match)
|
||||
pin(4 1 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(17 4 match)
|
||||
|
||||
Reference in New Issue
Block a user