mirror of https://github.com/KLayout/klayout.git
Test cases for DRC-based net extraction and flat extraction
Flat extraction requires that texts of subcells are not considered. Otherwise they pollute the net namespace of the top cell.
This commit is contained in:
Matthias Koefferlein
parent
ab8107de2d
commit
510c675d21
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@ -296,7 +296,7 @@ DeepShapeStore::~DeepShapeStore ()
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m_layouts.clear ();
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}
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DeepLayer DeepShapeStore::create_from_flat (const db::Region ®ion, double max_area_ratio, size_t max_vertex_count, const db::ICplxTrans &trans)
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DeepLayer DeepShapeStore::create_from_flat (const db::Region ®ion, bool for_netlist, double max_area_ratio, size_t max_vertex_count, const db::ICplxTrans &trans)
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{
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// reuse existing layer
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std::pair<bool, DeepLayer> lff = layer_for_flat (region);
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@ -322,12 +322,19 @@ DeepLayer DeepShapeStore::create_from_flat (const db::Region ®ion, double max
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db::PolygonReferenceHierarchyBuilderShapeReceiver refs (&layout (), m_text_enlargement, m_text_property_name);
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db::ReducingHierarchyBuilderShapeReceiver red (&refs, max_area_ratio, max_vertex_count);
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// try to maintain the texts - go through shape iterator
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// try to maintain the texts on top level - go through shape iterator
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std::pair<db::RecursiveShapeIterator, db::ICplxTrans> ii = region.begin_iter ();
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db::ICplxTrans ttop = trans * ii.second;
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while (! ii.first.at_end ()) {
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if (for_netlist && ii.first->is_text () && ii.first.layout () && ii.first.cell () != ii.first.top_cell ()) {
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// Skip texts on levels below top cell. For the reasoning see the description of this method.
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} else {
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red.push (*ii.first, ttop * ii.first.trans (), world, 0, shapes);
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}
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++ii.first;
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}
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DeepLayer dl (this, 0 /*singular layout index*/, layer);
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@ -267,8 +267,12 @@ public:
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*
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* After a flat layer has been created for a region, it can be retrieved
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* from the region later with layer_for_flat (region).
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*
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* If for_netlist is true, texts will be skipped except on top level. The
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* reasoning is that texts below top level may create name clashes if they
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* are used for net names.
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*/
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DeepLayer create_from_flat (const db::Region ®ion, double max_area_ratio = 0.0, size_t max_vertex_count = 0, const db::ICplxTrans &trans = db::ICplxTrans ());
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DeepLayer create_from_flat (const db::Region ®ion, bool for_netlist, double max_area_ratio = 0.0, size_t max_vertex_count = 0, const db::ICplxTrans &trans = db::ICplxTrans ());
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/**
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* @brief Gets the layer for a given flat region.
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@ -313,7 +313,7 @@ void LayoutToNetlist::register_layer (const db::Region ®ion, const std::strin
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if (m_is_flat) {
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dl = dss ().create_from_flat (region);
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dl = dss ().create_from_flat (region, true);
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} else {
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@ -200,9 +200,9 @@ TEST(4_FlatAndEmptyInput)
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db::Region r3;
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db::Region dr1 (new db::DeepRegion (dss.create_from_flat (r1)));
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db::Region dr2 (new db::DeepRegion (dss.create_from_flat (r2)));
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db::Region dr3 (new db::DeepRegion (dss.create_from_flat (r3)));
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db::Region dr1 (new db::DeepRegion (dss.create_from_flat (r1, true)));
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db::Region dr2 (new db::DeepRegion (dss.create_from_flat (r2, true)));
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db::Region dr3 (new db::DeepRegion (dss.create_from_flat (r3, true)));
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EXPECT_EQ ((dr1 - dr2).to_string (), "(0,0;0,900;100,900;100,100;900,100;900,900;0,900;0,1000;1000,1000;1000,0)");
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EXPECT_EQ ((dr1 - dr3).to_string (), "(0,0;0,1000;1000,1000;1000,0)");
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@ -24,6 +24,7 @@
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#include "dbReader.h"
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#include "dbTestSupport.h"
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#include "lymMacro.h"
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#include "tlFileUtils.h"
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TEST(1)
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{
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@ -342,3 +343,122 @@ TEST(8_TextsAndPolygons)
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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}
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TEST(9_NetlistExtraction)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/drc/drcSimpleTests_9.drc";
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std::string input = tl::testsrc ();
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input += "/testdata/drc/ringo.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/drc/drcSimpleTests_au9a.cir";
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std::string au_simplified = tl::testsrc ();
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au_simplified += "/testdata/drc/drcSimpleTests_au9b.cir";
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std::string output = this->tmp_file ("tmp.cir");
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std::string output_simplified = this->tmp_file ("tmp_simplified.cir");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$drc_test_source = '%s'\n"
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"$drc_test_target = '%s'\n"
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"$drc_test_target_simplified = '%s'\n"
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, input, output, output_simplified)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro drc;
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drc.load_from (rs);
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EXPECT_EQ (drc.run (), 0);
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// verify
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{
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tl::InputStream is (output);
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tl::InputStream is_au (au);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (output),
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tl::absolute_file_path (au)));
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}
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}
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{
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tl::InputStream is (output_simplified);
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tl::InputStream is_au (au_simplified);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed (simplified netlist) - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (output_simplified),
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tl::absolute_file_path (au_simplified)));
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}
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}
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}
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TEST(10_NetlistExtractionFlat)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/drc/drcSimpleTests_10.drc";
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std::string input = tl::testsrc ();
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input += "/testdata/drc/ringo.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/drc/drcSimpleTests_au10a.cir";
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std::string au_simplified = tl::testsrc ();
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au_simplified += "/testdata/drc/drcSimpleTests_au10b.cir";
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std::string output = this->tmp_file ("tmp.cir");
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std::string output_simplified = this->tmp_file ("tmp_simplified.cir");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$drc_test_source = '%s'\n"
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"$drc_test_target = '%s'\n"
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"$drc_test_target_simplified = '%s'\n"
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, input, output, output_simplified)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro drc;
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drc.load_from (rs);
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EXPECT_EQ (drc.run (), 0);
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// verify
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{
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tl::InputStream is (output);
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tl::InputStream is_au (au);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (output),
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tl::absolute_file_path (au)));
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}
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}
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{
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tl::InputStream is (output_simplified);
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tl::InputStream is_au (au_simplified);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed (simplified netlist) - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (output_simplified),
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tl::absolute_file_path (au_simplified)));
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}
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}
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}
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@ -0,0 +1,97 @@
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# Hierarchical extraction
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source($drc_test_source)
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# Drawing layers
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nwell = input(1, 0)
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diff = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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thickox = input(6, 0)
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polyres = input(7, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via = input(10, 0)
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metal2 = input(11, 0)
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# Special layer for bulk terminals
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bulk = make_layer
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# Computed layers
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diff_in_nwell = diff & nwell
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pdiff = diff_in_nwell - nplus
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ntie = diff_in_nwell & nplus
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pgate = pdiff & poly
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psd = pdiff - pgate
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hv_pgate = pgate & thickox
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lv_pgate = pgate - hv_pgate
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hv_psd = psd & thickox
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lv_psd = psd - thickox
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diff_outside_nwell = diff - nwell
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ndiff = diff_outside_nwell - pplus
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ptie = diff_outside_nwell & pplus
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ngate = ndiff & poly
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nsd = ndiff - ngate
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hv_ngate = ngate & thickox
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lv_ngate = ngate - hv_ngate
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hv_nsd = nsd & thickox
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lv_nsd = nsd - thickox
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# PMOS transistor device extraction
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hvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVPMOS")
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extract_devices(hvpmos_ex, { "SD" => psd, "G" => hv_pgate, "P" => poly, "W" => nwell })
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lvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVPMOS")
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extract_devices(lvpmos_ex, { "SD" => psd, "G" => lv_pgate, "P" => poly, "W" => nwell })
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# NMOS transistor device extraction
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lvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVNMOS")
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extract_devices(lvnmos_ex, { "SD" => nsd, "G" => lv_ngate, "P" => poly, "W" => bulk })
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hvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVNMOS")
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extract_devices(hvnmos_ex, { "SD" => nsd, "G" => hv_ngate, "P" => poly, "W" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(contact, ntie)
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connect(contact, ptie)
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connect(nwell, ntie)
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(contact, metal1)
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connect(metal1, via)
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connect(via, metal2)
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# Global connections
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connect_global(ptie, "BULK")
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connect_global(bulk, "BULK")
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# Actually performs the extraction
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netlist = l2n_data.netlist
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# Writes the netlist
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writer = RBA::NetlistSpiceWriter::new
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netlist.write($drc_test_target, writer, "RINGO netlist before simplification")
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# Netlist simplification
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netlist.combine_devices
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netlist.make_top_level_pins
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netlist.purge
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netlist.purge_nets
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netlist.write($drc_test_target_simplified, writer, "RINGO netlist after simplification")
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@ -0,0 +1,99 @@
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# Hierarchical extraction
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source($drc_test_source)
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deep
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# Drawing layers
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nwell = input(1, 0)
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diff = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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thickox = input(6, 0)
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polyres = input(7, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via = input(10, 0)
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metal2 = input(11, 0)
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# Special layer for bulk terminals
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bulk = make_layer
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# Computed layers
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diff_in_nwell = diff & nwell
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pdiff = diff_in_nwell - nplus
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ntie = diff_in_nwell & nplus
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pgate = pdiff & poly
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psd = pdiff - pgate
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hv_pgate = pgate & thickox
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lv_pgate = pgate - hv_pgate
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hv_psd = psd & thickox
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lv_psd = psd - thickox
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diff_outside_nwell = diff - nwell
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ndiff = diff_outside_nwell - pplus
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ptie = diff_outside_nwell & pplus
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ngate = ndiff & poly
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nsd = ndiff - ngate
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hv_ngate = ngate & thickox
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lv_ngate = ngate - hv_ngate
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hv_nsd = nsd & thickox
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lv_nsd = nsd - thickox
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# PMOS transistor device extraction
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hvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVPMOS")
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extract_devices(hvpmos_ex, { "SD" => psd, "G" => hv_pgate, "P" => poly, "W" => nwell })
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lvpmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVPMOS")
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extract_devices(lvpmos_ex, { "SD" => psd, "G" => lv_pgate, "P" => poly, "W" => nwell })
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# NMOS transistor device extraction
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lvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("LVNMOS")
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extract_devices(lvnmos_ex, { "SD" => nsd, "G" => lv_ngate, "P" => poly, "W" => bulk })
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hvnmos_ex = RBA::DeviceExtractorMOS4Transistor::new("HVNMOS")
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extract_devices(hvnmos_ex, { "SD" => nsd, "G" => hv_ngate, "P" => poly, "W" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(contact, ntie)
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connect(contact, ptie)
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connect(nwell, ntie)
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(contact, metal1)
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connect(metal1, via)
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connect(via, metal2)
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# Global connections
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connect_global(ptie, "BULK")
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connect_global(bulk, "BULK")
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# Actually performs the extraction
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netlist = l2n_data.netlist
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# Writes the netlist
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writer = RBA::NetlistSpiceWriter::new
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netlist.write($drc_test_target, writer, "RINGO netlist before simplification")
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# Netlist simplification
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netlist.combine_devices
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netlist.make_top_level_pins
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netlist.purge
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netlist.purge_nets
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netlist.write($drc_test_target_simplified, writer, "RINGO netlist after simplification")
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@ -0,0 +1,67 @@
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* RINGO netlist before simplification
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* cell RINGO
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.SUBCKT RINGO
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* net 12 OUT
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* net 27 ENABLE
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* net 28 VDD
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* net 29 FB
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* net 43 BULK,VSS
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* device instance $1 2.65,5.8 LVPMOS
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M$1 2 27 28 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
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* device instance $2 3.35,5.8 LVPMOS
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M$2 28 29 2 28 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
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* device instance $3 5.05,5.8 LVPMOS
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M$3 28 2 3 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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* device instance $4 6.85,5.8 LVPMOS
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M$4 28 3 4 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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* device instance $5 8.65,5.8 LVPMOS
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M$5 28 4 5 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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* device instance $6 10.45,5.8 LVPMOS
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M$6 28 5 6 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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* device instance $7 12.25,5.8 LVPMOS
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M$7 28 6 7 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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* device instance $8 14.05,5.8 LVPMOS
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M$8 28 7 8 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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* device instance $9 15.85,5.8 LVPMOS
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M$9 28 8 9 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $10 17.65,5.8 LVPMOS
|
||||
M$10 28 9 10 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $11 19.45,5.8 LVPMOS
|
||||
M$11 28 10 11 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $12 21.25,5.8 LVPMOS
|
||||
M$12 28 11 29 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $13 23.05,5.8 LVPMOS
|
||||
M$13 28 29 12 28 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $14 2.65,2.135 LVNMOS
|
||||
M$14 43 27 14 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
* device instance $15 3.35,2.135 LVNMOS
|
||||
M$15 14 29 2 43 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
* device instance $16 5.05,2.135 LVNMOS
|
||||
M$16 43 2 3 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $17 6.85,2.135 LVNMOS
|
||||
M$17 43 3 4 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $18 8.65,2.135 LVNMOS
|
||||
M$18 43 4 5 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $19 10.45,2.135 LVNMOS
|
||||
M$19 43 5 6 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $20 12.25,2.135 LVNMOS
|
||||
M$20 43 6 7 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $21 14.05,2.135 LVNMOS
|
||||
M$21 43 7 8 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $22 15.85,2.135 LVNMOS
|
||||
M$22 43 8 9 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $23 17.65,2.135 LVNMOS
|
||||
M$23 43 9 10 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
* device instance $24 19.45,2.135 LVNMOS
|
||||
M$24 43 10 11 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
* device instance $25 21.25,2.135 LVNMOS
|
||||
M$25 43 11 29 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
* device instance $26 23.05,2.135 LVNMOS
|
||||
M$26 43 29 12 43 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS RINGO
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
* RINGO netlist after simplification
|
||||
|
||||
* cell RINGO
|
||||
* pin OUT
|
||||
* pin ENABLE
|
||||
* pin VDD
|
||||
* pin FB
|
||||
* pin BULK,VSS
|
||||
.SUBCKT RINGO 11 13 14 15 16
|
||||
* net 11 OUT
|
||||
* net 13 ENABLE
|
||||
* net 14 VDD
|
||||
* net 15 FB
|
||||
* net 16 BULK,VSS
|
||||
* device instance $1 2.65,5.8 LVPMOS
|
||||
M$1 1 13 14 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 3.35,5.8 LVPMOS
|
||||
M$2 14 15 1 14 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 5.05,5.8 LVPMOS
|
||||
M$3 14 1 2 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $4 6.85,5.8 LVPMOS
|
||||
M$4 14 2 3 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $5 8.65,5.8 LVPMOS
|
||||
M$5 14 3 4 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $6 10.45,5.8 LVPMOS
|
||||
M$6 14 4 5 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $7 12.25,5.8 LVPMOS
|
||||
M$7 14 5 6 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $8 14.05,5.8 LVPMOS
|
||||
M$8 14 6 7 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $9 15.85,5.8 LVPMOS
|
||||
M$9 14 7 8 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $10 17.65,5.8 LVPMOS
|
||||
M$10 14 8 9 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $11 19.45,5.8 LVPMOS
|
||||
M$11 14 9 10 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $12 21.25,5.8 LVPMOS
|
||||
M$12 14 10 15 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $13 23.05,5.8 LVPMOS
|
||||
M$13 14 15 11 14 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $14 2.65,2.135 LVNMOS
|
||||
M$14 16 13 12 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
* device instance $15 3.35,2.135 LVNMOS
|
||||
M$15 12 15 1 16 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
* device instance $16 5.05,2.135 LVNMOS
|
||||
M$16 16 1 2 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $17 6.85,2.135 LVNMOS
|
||||
M$17 16 2 3 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $18 8.65,2.135 LVNMOS
|
||||
M$18 16 3 4 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $19 10.45,2.135 LVNMOS
|
||||
M$19 16 4 5 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $20 12.25,2.135 LVNMOS
|
||||
M$20 16 5 6 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $21 14.05,2.135 LVNMOS
|
||||
M$21 16 6 7 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $22 15.85,2.135 LVNMOS
|
||||
M$22 16 7 8 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $23 17.65,2.135 LVNMOS
|
||||
M$23 16 8 9 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
* device instance $24 19.45,2.135 LVNMOS
|
||||
M$24 16 9 10 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
* device instance $25 21.25,2.135 LVNMOS
|
||||
M$25 16 10 15 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
* device instance $26 23.05,2.135 LVNMOS
|
||||
M$26 16 15 11 16 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS RINGO
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
* RINGO netlist before simplification
|
||||
|
||||
* cell RINGO
|
||||
.SUBCKT RINGO
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 15 OUT
|
||||
* net 16 ENABLE
|
||||
* net 19 BULK,VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 19 12 11 16 19 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 12 2 19 12 1 19 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 12 3 19 12 2 19 INVX1
|
||||
* cell instance $4 r0 *1 7.8,0
|
||||
X$4 12 4 19 12 3 19 INVX1
|
||||
* cell instance $5 r0 *1 9.6,0
|
||||
X$5 12 5 19 12 4 19 INVX1
|
||||
* cell instance $6 r0 *1 11.4,0
|
||||
X$6 12 6 19 12 5 19 INVX1
|
||||
* cell instance $7 r0 *1 13.2,0
|
||||
X$7 12 7 19 12 6 19 INVX1
|
||||
* cell instance $8 r0 *1 15,0
|
||||
X$8 12 8 19 12 7 19 INVX1
|
||||
* cell instance $9 r0 *1 16.8,0
|
||||
X$9 12 9 19 12 8 19 INVX1
|
||||
* cell instance $10 r0 *1 18.6,0
|
||||
X$10 12 10 19 12 9 19 INVX1
|
||||
* cell instance $11 r0 *1 20.4,0
|
||||
X$11 12 11 19 12 10 19 INVX1
|
||||
* cell instance $12 r0 *1 22.2,0
|
||||
X$12 12 15 19 12 11 19 INVX1
|
||||
* cell instance $13 r0 *1 3.28,4
|
||||
X$13 11 M1M2
|
||||
* cell instance $14 r0 *1 21.42,4
|
||||
X$14 11 M1M2
|
||||
* cell instance $15 r0 *1 0.6,0
|
||||
X$15 12 19 TIE
|
||||
* cell instance $16 r0 *1 0,0
|
||||
X$16 12 19 12 EMPTY
|
||||
* cell instance $17 r0 *1 24,0
|
||||
X$17 12 19 TIE
|
||||
* cell instance $18 r0 *1 25.2,0
|
||||
X$18 12 19 12 EMPTY
|
||||
* cell instance $19 r0 *1 23.6,4
|
||||
X$19 15 M1M2
|
||||
* cell instance $20 r0 *1 2.6,3.1
|
||||
X$20 16 M1M2
|
||||
.ENDS RINGO
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin BULK
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 9
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 9 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 6 1 2 PMOS3
|
||||
* cell instance $2 r0 *1 1,5.05
|
||||
X$2 5 2 1 PMOS3
|
||||
* cell instance $3 r0 *1 1,1.66
|
||||
X$3 5 2 10 NMOS2
|
||||
* cell instance $4 r0 *1 0.3,1.66
|
||||
X$4 6 10 3 NMOS2
|
||||
* cell instance $5 r0 *1 1.48,4
|
||||
X$5 5 POLYM1
|
||||
* cell instance $6 r0 *1 0.8,3.1
|
||||
X$6 6 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 2 6 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 1.55,5.8 LVPMOS
|
||||
M$2 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 0.85,2.135 LVNMOS
|
||||
M$3 3 6 10 9 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 1.55,2.135 LVNMOS
|
||||
M$4 10 5 2 9 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin BULK
|
||||
.SUBCKT INVX1 1 2 3 4 5 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 7 BULK
|
||||
* cell instance $1 r0 *1 0.3,5.05
|
||||
X$1 5 2 1 PMOS3
|
||||
* cell instance $2 r0 *1 0.3,1.66
|
||||
X$2 5 2 3 NMOS2
|
||||
* cell instance $3 r0 *1 0.6,3.1
|
||||
X$3 5 POLYM1
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 0.85,2.135 LVNMOS
|
||||
M$2 3 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell M1M2
|
||||
* pin
|
||||
.SUBCKT M1M2 1
|
||||
.ENDS M1M2
|
||||
|
||||
* cell TIE
|
||||
* pin VDD
|
||||
* pin BULK,VSS
|
||||
.SUBCKT TIE 2 3
|
||||
* net 2 VDD
|
||||
* net 3 BULK,VSS
|
||||
.ENDS TIE
|
||||
|
||||
* cell EMPTY
|
||||
* pin
|
||||
* pin
|
||||
* pin
|
||||
.SUBCKT EMPTY 1 2 3
|
||||
.ENDS EMPTY
|
||||
|
||||
* cell POLYM1
|
||||
* pin
|
||||
.SUBCKT POLYM1 1
|
||||
.ENDS POLYM1
|
||||
|
||||
* cell NMOS2
|
||||
* pin
|
||||
* pin
|
||||
* pin
|
||||
.SUBCKT NMOS2 1 2 3
|
||||
.ENDS NMOS2
|
||||
|
||||
* cell PMOS3
|
||||
* pin
|
||||
* pin
|
||||
* pin
|
||||
.SUBCKT PMOS3 1 2 3
|
||||
.ENDS PMOS3
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
* RINGO netlist after simplification
|
||||
|
||||
* cell RINGO
|
||||
* pin FB
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin ENABLE
|
||||
* pin BULK,VSS
|
||||
.SUBCKT RINGO 11 12 13 14 15
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 13 OUT
|
||||
* net 14 ENABLE
|
||||
* net 15 BULK,VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 15 12 11 14 15 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 12 2 15 12 1 15 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 12 3 15 12 2 15 INVX1
|
||||
* cell instance $4 r0 *1 7.8,0
|
||||
X$4 12 4 15 12 3 15 INVX1
|
||||
* cell instance $5 r0 *1 9.6,0
|
||||
X$5 12 5 15 12 4 15 INVX1
|
||||
* cell instance $6 r0 *1 11.4,0
|
||||
X$6 12 6 15 12 5 15 INVX1
|
||||
* cell instance $7 r0 *1 13.2,0
|
||||
X$7 12 7 15 12 6 15 INVX1
|
||||
* cell instance $8 r0 *1 15,0
|
||||
X$8 12 8 15 12 7 15 INVX1
|
||||
* cell instance $9 r0 *1 16.8,0
|
||||
X$9 12 9 15 12 8 15 INVX1
|
||||
* cell instance $10 r0 *1 18.6,0
|
||||
X$10 12 10 15 12 9 15 INVX1
|
||||
* cell instance $11 r0 *1 20.4,0
|
||||
X$11 12 11 15 12 10 15 INVX1
|
||||
* cell instance $12 r0 *1 22.2,0
|
||||
X$12 12 13 15 12 11 15 INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin BULK
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 7 BULK
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 2 6 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 1.55,5.8 LVPMOS
|
||||
M$2 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 0.85,2.135 LVNMOS
|
||||
M$3 3 6 8 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 1.55,2.135 LVNMOS
|
||||
M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin BULK
|
||||
.SUBCKT INVX1 1 2 3 4 5 6
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 6 BULK
|
||||
* device instance $1 0.85,5.8 LVPMOS
|
||||
M$1 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 0.85,2.135 LVNMOS
|
||||
M$2 3 5 2 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
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Reference in New Issue