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Fixed tests. Note that now a net with two labels carries a combined net name and does not qualify for connect_implicit if one label matches

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This commit is contained in:
Matthias Koefferlein
2023-09-23 21:44:35 +02:00
parent c81388d830
commit 4d41ca6f5c
29 changed files with 300 additions and 85 deletions
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testdata/drc/drcSimpleTests_12.drc
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+2 -2
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@@ -21,8 +21,8 @@ metal2_lbl = input(8, 1)
# Computed layers
pactive = active & nwell
pgate = active & poly
psd = active - pgate
pgate = pactive & poly
psd = pactive - pgate
nactive = active - nwell
ngate = nactive & poly
testdata/drc/drcSimpleTests_au12a.cir
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+14 -18
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@@ -5,12 +5,12 @@
* net 1 FB
* net 2 OSC
* net 3 NEXT
* net 4 VSSZ,VSS
* net 5 VDDZ,VDD
* cell instance $1 r180 *1 -0.24,9.18
X$1 16 1 2 4 5 INV2
* cell instance $2 r0 *1 0,0
X$2 1 14 15 4 5 INV2
* net 4 VSSZ
* net 5 VDDZ
* cell instance $1 r0 *1 0,0
X$1 1 14 15 4 5 INV2
* cell instance $2 r180 *1 -0.24,9.18
X$2 16 1 2 4 5 INV2
* cell instance $3 r180 *1 10.32,9.18
X$3 3 9 19 4 5 INV2
* cell instance $4 r0 *1 10.56,0
@@ -46,18 +46,14 @@ X$2 2 5 1 TRANS
X$3 5 3 2 TRANS
* cell instance $4 m0 *1 0.4,0
X$4 4 3 2 TRANS
* device instance $1 -0.4,0 PMOS
M$1 2 1 4 2 PMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $2 0.4,0 PMOS
M$2 4 2 3 4 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $3 -0.4,2.8 PMOS
M$3 2 1 5 2 PMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $4 0.4,2.8 PMOS
M$4 5 2 3 5 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $5 -0.4,0 NMOS
M$5 2 1 4 2 NMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $6 0.4,0 NMOS
M$6 4 2 3 4 NMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $1 r0 *1 -0.4,2.8 PMOS
M$1 5 1 2 2 PMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $2 r0 *1 0.4,2.8 PMOS
M$2 3 2 5 5 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $3 r0 *1 -0.4,0 NMOS
M$3 4 1 2 2 NMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $4 r0 *1 0.4,0 NMOS
M$4 3 2 4 4 NMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
.ENDS INV2
* cell TRANS
testdata/drc/implicit_nets.gds
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BIN
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testdata/lvs/double_height2.lvs
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+2
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@@ -3,6 +3,8 @@ source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb)
ignore_extraction_errors(true)
writer = write_spice(true, false)
target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
testdata/lvs/double_height2.lvsdb
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+2
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@@ -27,6 +27,8 @@ J(
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets GND from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(W B('Must-connect nets R from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(E B('Must-connect nets R from circuit INV2 are not connected in INVCHAIN'))
K(PMOS MOS3)
K(NMOS MOS3)
testdata/lvs/double_height2_texts.lvs
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+2
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@@ -3,6 +3,8 @@ source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb)
ignore_extraction_errors(true)
writer = write_spice(true, false)
target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
testdata/lvs/double_height2_texts.lvsdb
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+2
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@@ -27,6 +27,8 @@ J(
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets GND from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(W B('Must-connect nets R from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(E B('Must-connect nets R from circuit INV2 are not connected in INVCHAIN'))
K(PMOS MOS3)
K(NMOS MOS3)
testdata/lvs/ringo_simple_implicit_connections.lvsdb.1
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+3
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@@ -38,6 +38,9 @@ layout(
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Log entries
message(warning description('Must-connect nets VDD from circuit RINGO must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
testdata/lvs/test_22a.lvsdb.1
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+3
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@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22a.lvsdb.2
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+3
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@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22b.lvsdb.1
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+3
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@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22b.lvsdb.2
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+3
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@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22c.lvsdb.1
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+3
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@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22c.lvsdb.2
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+3
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@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22c.lvsdb.3
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+3
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@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22d.lvsdb.1
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+3
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@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22d.lvsdb.2
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+3
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@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22d.lvsdb.3
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+3
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@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
# Device class section
class(active_res RES)
class(poly_res RES)