mirror of https://github.com/KLayout/klayout.git
Added a regression test for netlist extractor with soft connections
This commit is contained in:
Matthias Koefferlein
parent
417309acf1
commit
44edd8d26a
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@ -101,6 +101,11 @@ static void dump_nets_to_layout (const db::Netlist &nl, const db::hier_clusters<
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for (db::Net::const_terminal_iterator t = n->begin_terminals (); t != n->end_terminals (); ++t) {
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const db::NetTerminalRef &tref = *t;
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if (! tref.device ()->device_abstract ()) {
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continue;
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}
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db::cell_index_type dci = tref.device ()->device_abstract ()->cell_index ();
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db::DCplxTrans dtr = tref.device ()->trans ();
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@ -121,6 +126,10 @@ static void dump_nets_to_layout (const db::Netlist &nl, const db::hier_clusters<
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for (db::Circuit::const_device_iterator d = c->begin_devices (); d != c->end_devices (); ++d) {
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if (! d->device_abstract ()) {
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continue;
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}
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std::vector<db::cell_index_type> original_device_cells;
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db::cell_index_type dci = d->device_abstract ()->cell_index ();
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@ -3176,6 +3185,336 @@ TEST(14_JoinNets)
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db::compare_layouts (_this, ly, au);
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}
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static
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void annotate_soft_connections (db::Netlist &netlist, const db::hier_clusters<db::NetShape> &net_clusters)
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{
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db::DeviceClassDiode *soft_diode = new db::DeviceClassDiode ();
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soft_diode->set_name ("SOFT");
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netlist.add_device_class (soft_diode);
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for (auto c = netlist.begin_bottom_up (); c != netlist.end_bottom_up (); ++c) {
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auto clusters = net_clusters.clusters_per_cell (c->cell_index ());
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for (auto n = c->begin_nets (); n != c->end_nets (); ++n) {
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auto soft_connections = clusters.upward_soft_connections (n->cluster_id ());
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for (auto sc = soft_connections.begin (); sc != soft_connections.end (); ++sc) {
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db::Device *sc_device = new db::Device (soft_diode);
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c->add_device (sc_device);
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auto nn = c->net_by_cluster_id (*sc);
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if (nn) {
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sc_device->connect_terminal (db::DeviceClassDiode::terminal_id_C, n.operator-> ());
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sc_device->connect_terminal (db::DeviceClassDiode::terminal_id_A, nn);
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}
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}
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}
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}
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}
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TEST(15_SoftConnections)
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{
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db::Layout ly;
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db::LayerMap lmap;
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unsigned int nwell = define_layer (ly, lmap, 1);
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unsigned int diff = define_layer (ly, lmap, 2);
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unsigned int pplus = define_layer (ly, lmap, 3);
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unsigned int nplus = define_layer (ly, lmap, 4);
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unsigned int poly = define_layer (ly, lmap, 5);
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unsigned int contact = define_layer (ly, lmap, 8);
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unsigned int metal1 = define_layer (ly, lmap, 9);
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unsigned int via1 = define_layer (ly, lmap, 10);
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unsigned int metal2 = define_layer (ly, lmap, 11);
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{
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db::LoadLayoutOptions options;
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options.get_options<db::CommonReaderOptions> ().layer_map = lmap;
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options.get_options<db::CommonReaderOptions> ().create_other_layers = false;
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std::string fn (tl::testdata ());
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fn = tl::combine_path (fn, "algo");
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fn = tl::combine_path (fn, "soft_connections.gds");
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tl::InputStream stream (fn);
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db::Reader reader (stream);
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reader.read (ly, options);
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}
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db::Cell &tc = ly.cell (*ly.begin_top_down ());
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db::DeepShapeStore dss;
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dss.set_text_enlargement (1);
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dss.set_text_property_name (tl::Variant ("LABEL"));
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// original layers
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db::Region rnwell (db::RecursiveShapeIterator (ly, tc, nwell), dss);
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db::Region rdiff (db::RecursiveShapeIterator (ly, tc, diff), dss);
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db::Region rpplus (db::RecursiveShapeIterator (ly, tc, pplus), dss);
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db::Region rnplus (db::RecursiveShapeIterator (ly, tc, nplus), dss);
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db::Region rpoly (db::RecursiveShapeIterator (ly, tc, poly), dss);
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db::Region rcontact (db::RecursiveShapeIterator (ly, tc, contact), dss);
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db::Region rmetal1 (db::RecursiveShapeIterator (ly, tc, metal1), dss);
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db::Region rvia1 (db::RecursiveShapeIterator (ly, tc, via1), dss);
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db::Region rmetal2 (db::RecursiveShapeIterator (ly, tc, metal2), dss);
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// derived regions
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db::Region rdiff_in_nwell = rdiff & rnwell;
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db::Region rpdiff = rdiff_in_nwell - rnplus;
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db::Region rntie = rdiff_in_nwell & rnplus;
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db::Region rpgate = rpdiff & rpoly;
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db::Region rpsd = rpdiff - rpgate;
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db::Region rdiff_outside_nwell = rdiff - rnwell;
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db::Region rndiff = rdiff_outside_nwell - rpplus;
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db::Region rptie = rdiff_outside_nwell & rpplus;
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db::Region rngate = rndiff & rpoly;
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db::Region rnsd = rndiff - rngate;
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// Global
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db::Region bulk (dss);
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// return the computed layers into the original layout and write it for debugging purposes
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unsigned int lpgate = ly.insert_layer (db::LayerProperties (10, 0)); // 10/0 -> Gate (p)
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unsigned int lngate = ly.insert_layer (db::LayerProperties (11, 0)); // 11/0 -> Gate (n)
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unsigned int lpsd = ly.insert_layer (db::LayerProperties (12, 0)); // 12/0 -> Source/Drain (p)
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unsigned int lnsd = ly.insert_layer (db::LayerProperties (13, 0)); // 13/0 -> Source/Drain (n)
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unsigned int lpdiff = ly.insert_layer (db::LayerProperties (14, 0)); // 14/0 -> P Diffusion
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unsigned int lndiff = ly.insert_layer (db::LayerProperties (15, 0)); // 15/0 -> N Diffusion
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unsigned int lptie = ly.insert_layer (db::LayerProperties (16, 0)); // 16/0 -> P Tie
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unsigned int lntie = ly.insert_layer (db::LayerProperties (17, 0)); // 17/0 -> N Tie
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rpgate.insert_into (&ly, tc.cell_index (), lpgate);
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rngate.insert_into (&ly, tc.cell_index (), lngate);
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rpsd.insert_into (&ly, tc.cell_index (), lpsd);
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rnsd.insert_into (&ly, tc.cell_index (), lnsd);
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rpdiff.insert_into (&ly, tc.cell_index (), lpdiff);
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rndiff.insert_into (&ly, tc.cell_index (), lndiff);
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rptie.insert_into (&ly, tc.cell_index (), lptie);
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rntie.insert_into (&ly, tc.cell_index (), lntie);
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// perform the extraction
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db::Netlist nl;
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db::hier_clusters<db::NetShape> cl;
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db::NetlistDeviceExtractorMOS4Transistor pmos_ex ("PMOS");
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db::NetlistDeviceExtractorMOS4Transistor nmos_ex ("NMOS");
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db::NetlistDeviceExtractor::input_layers dl;
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dl["SD"] = &rpsd;
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dl["G"] = &rpgate;
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dl["W"] = &rnwell;
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dl["P"] = &rpoly; // not needed for extraction but to return terminal shapes
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pmos_ex.extract (dss, 0, dl, nl, cl);
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dl["SD"] = &rnsd;
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dl["G"] = &rngate;
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dl["W"] = &bulk;
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dl["P"] = &rpoly; // not needed for extraction but to return terminal shapes
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nmos_ex.extract (dss, 0, dl, nl, cl);
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// perform the net extraction
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db::NetlistExtractor net_ex;
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db::Connectivity conn;
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// Global nets
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conn.connect_global (bulk, "BULK");
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conn.soft_connect_global (rptie, "BULK");
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// Intra-layer
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conn.connect (rpsd);
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conn.connect (rnsd);
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conn.connect (rptie);
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conn.connect (rntie);
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conn.connect (rnwell);
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conn.connect (rpoly);
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conn.connect (rcontact);
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conn.connect (rmetal1);
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conn.connect (rvia1);
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conn.connect (rmetal2);
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// Inter-layer
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conn.soft_connect (rcontact, rpsd);
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conn.soft_connect (rcontact, rnsd);
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conn.soft_connect (rntie, rnwell);
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conn.soft_connect (rcontact, rptie);
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conn.soft_connect (rcontact, rntie);
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conn.soft_connect (rcontact, rpoly);
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conn.connect (rcontact, rmetal1);
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conn.connect (rvia1, rmetal1);
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conn.connect (rvia1, rmetal2);
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// extract the nets
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#if 0 // @@@
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std::list<std::set<std::string> > jn;
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jn.push_back (std::set<std::string> ());
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jn.back ().insert ("BULK");
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jn.back ().insert ("VSS");
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jn.push_back (std::set<std::string> ());
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jn.back ().insert ("NWELL");
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jn.back ().insert ("VDD");
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net_ex.set_joined_nets ("INV2", jn);
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std::list<tl::GlobPattern> gp;
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gp.push_back (tl::GlobPattern ("NEXT"));
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gp.push_back (tl::GlobPattern ("FB"));
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net_ex.set_joined_net_names (gp);
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#endif
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net_ex.extract_nets (dss, 0, conn, nl, cl);
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annotate_soft_connections (nl, cl);
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EXPECT_EQ (all_net_names_unique (nl), true);
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// debug layers produced for nets
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std::map<unsigned int, unsigned int> dump_map;
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dump_map [layer_of (bulk) ] = ly.insert_layer (db::LayerProperties (200, 0));
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dump_map [layer_of (rnwell) ] = ly.insert_layer (db::LayerProperties (201, 0));
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dump_map [layer_of (rpsd) ] = ly.insert_layer (db::LayerProperties (202, 0));
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dump_map [layer_of (rnsd) ] = ly.insert_layer (db::LayerProperties (203, 0));
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dump_map [layer_of (rpoly) ] = ly.insert_layer (db::LayerProperties (204, 0));
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dump_map [layer_of (rcontact) ] = ly.insert_layer (db::LayerProperties (205, 0));
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dump_map [layer_of (rmetal1) ] = ly.insert_layer (db::LayerProperties (206, 0));
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dump_map [layer_of (rvia1) ] = ly.insert_layer (db::LayerProperties (207, 0));
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dump_map [layer_of (rmetal2) ] = ly.insert_layer (db::LayerProperties (208, 0));
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// write nets to layout
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db::CellMapping cm = dss.cell_mapping_to_original (0, &ly, tc.cell_index ());
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dump_nets_to_layout (nl, cl, ly, dump_map, cm, true);
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// compare netlist as string
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CHECKPOINT ();
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db::compare_netlist (_this, nl,
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"circuit RINGO ();\n"
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" subcircuit ND2X1 $1 (NWELL=$4,B=FB,A=ENABLE,VDD=VDD,OUT=$5,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $2 (NWELL=$4,IN=$14,VDD=VDD,OUT=FB,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $3 (NWELL=$4,IN=FB,VDD=$I17,OUT=OUT,VSS=$I27,BULK=BULK);\n"
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" subcircuit TIE $4 (NWELL=$4,VSS=$I27,VDD=$I17,BULK=BULK);\n"
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" subcircuit EMPTY $5 ($1=$4,$2=$I27,$3=$I17);\n"
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" subcircuit TIE $6 (NWELL=$4,VSS=VSS,VDD=VDD,BULK=BULK);\n"
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" subcircuit INVX1 $7 (NWELL=$4,IN=$5,VDD=VDD,OUT=$6,VSS=VSS,BULK=BULK);\n"
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" subcircuit EMPTY $8 ($1=$4,$2=VSS,$3=VDD);\n"
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" subcircuit INVX1 $9 (NWELL=$4,IN=$6,VDD=VDD,OUT=$7,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $10 (NWELL=$4,IN=$7,VDD=VDD,OUT=$8,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $11 (NWELL=$4,IN=$8,VDD=VDD,OUT=$9,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $12 (NWELL=$4,IN=$9,VDD=VDD,OUT=$10,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $13 (NWELL=$4,IN=$10,VDD=VDD,OUT=$11,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $14 (NWELL=$4,IN=$11,VDD=VDD,OUT=$12,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $15 (NWELL=$4,IN=$12,VDD=VDD,OUT=$15,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $16 (NWELL=$4,IN=$15,VDD=VDD,OUT=$14,VSS=VSS,BULK=BULK);\n"
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"end;\n"
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"circuit ND2X1 (NWELL=NWELL,B=B,A=A,VDD=VDD,OUT=OUT,VSS=VSS,BULK=BULK);\n"
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" device PMOS $1 (S=$7,G=$4,D=$9,B=NWELL) (L=0.25,W=1.5,AS=0.6375,AD=0.3375,PS=3.85,PD=1.95);\n"
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" device PMOS $2 (S=$9,G=$2,D=$6,B=NWELL) (L=0.25,W=1.5,AS=0.3375,AD=0.6375,PS=1.95,PD=3.85);\n"
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" device NMOS $3 (S=$13,G=$4,D=$14,B=BULK) (L=0.25,W=0.95,AS=0.40375,AD=0.21375,PS=2.75,PD=1.4);\n"
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" device NMOS $4 (S=$14,G=$2,D=$11,B=BULK) (L=0.25,W=0.95,AS=0.21375,AD=0.40375,PS=1.4,PD=2.75);\n"
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" device SOFT $5 (A=B,C=$2) (A=0,P=0);\n"
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" device SOFT $6 (A=A,C=$4) (A=0,P=0);\n"
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" device SOFT $7 (A=OUT,C=$6) (A=0,P=0);\n"
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" device SOFT $8 (A=OUT,C=$7) (A=0,P=0);\n"
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" device SOFT $9 (A=VDD,C=$9) (A=0,P=0);\n"
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" device SOFT $10 (A=OUT,C=$11) (A=0,P=0);\n"
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" device SOFT $11 (A=VSS,C=$13) (A=0,P=0);\n"
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"end;\n"
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"circuit TIE (NWELL=NWELL,VSS=VSS,VDD=VDD,BULK=BULK);\n"
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" device SOFT $1 (A=$2,C=NWELL) (A=0,P=0);\n"
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" device SOFT $2 (A=VDD,C=$2) (A=0,P=0);\n"
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" device SOFT $3 (A=VSS,C=$3) (A=0,P=0);\n"
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" device SOFT $4 (A=$3,C=BULK) (A=0,P=0);\n"
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"end;\n"
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"circuit EMPTY ($1=$1,$2=$2,$3=$3);\n"
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"end;\n"
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"circuit INVX1 (NWELL=NWELL,IN=IN,VDD=VDD,OUT=OUT,VSS=VSS,BULK=BULK);\n"
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" device PMOS $1 (S=$5,G=$2,D=$7,B=NWELL) (L=0.25,W=1.5,AS=0.6375,AD=0.6375,PS=3.85,PD=3.85);\n"
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" device NMOS $2 (S=$10,G=$2,D=$8,B=BULK) (L=0.25,W=0.95,AS=0.40375,AD=0.40375,PS=2.75,PD=2.75);\n"
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" device SOFT $3 (A=IN,C=$2) (A=0,P=0);\n"
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" device SOFT $4 (A=VDD,C=$5) (A=0,P=0);\n"
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" device SOFT $5 (A=OUT,C=$7) (A=0,P=0);\n"
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" device SOFT $6 (A=OUT,C=$8) (A=0,P=0);\n"
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" device SOFT $7 (A=VSS,C=$10) (A=0,P=0);\n"
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"end;\n"
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);
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// doesn't do anything here, but we test that this does not destroy anything:
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nl.combine_devices ();
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// make pins for named nets of top-level circuits - this way they are not purged
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nl.make_top_level_pins ();
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nl.purge ();
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// compare netlist as string
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CHECKPOINT ();
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db::compare_netlist (_this, nl,
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"circuit RINGO (FB=FB,ENABLE=ENABLE,OUT=OUT,VDD=VDD,VSS=VSS,BULK=BULK);\n"
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" subcircuit ND2X1 $1 (NWELL=$4,B=FB,A=ENABLE,VDD=VDD,OUT=$5,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $2 (NWELL=$4,IN=$14,VDD=VDD,OUT=FB,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $3 (NWELL=$4,IN=FB,VDD=$I17,OUT=OUT,VSS=$I27,BULK=BULK);\n"
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" subcircuit TIE $4 (NWELL=$4,VSS=$I27,VDD=$I17,BULK=BULK);\n"
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" subcircuit TIE $5 (NWELL=$4,VSS=VSS,VDD=VDD,BULK=BULK);\n"
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" subcircuit INVX1 $6 (NWELL=$4,IN=$5,VDD=VDD,OUT=$6,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $7 (NWELL=$4,IN=$6,VDD=VDD,OUT=$7,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $8 (NWELL=$4,IN=$7,VDD=VDD,OUT=$8,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $9 (NWELL=$4,IN=$8,VDD=VDD,OUT=$9,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $10 (NWELL=$4,IN=$9,VDD=VDD,OUT=$10,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $11 (NWELL=$4,IN=$10,VDD=VDD,OUT=$11,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $12 (NWELL=$4,IN=$11,VDD=VDD,OUT=$12,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $13 (NWELL=$4,IN=$12,VDD=VDD,OUT=$15,VSS=VSS,BULK=BULK);\n"
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" subcircuit INVX1 $14 (NWELL=$4,IN=$15,VDD=VDD,OUT=$14,VSS=VSS,BULK=BULK);\n"
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"end;\n"
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"circuit ND2X1 (NWELL=NWELL,B=B,A=A,VDD=VDD,OUT=OUT,VSS=VSS,BULK=BULK);\n"
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" device PMOS $1 (S=$7,G=$4,D=$9,B=NWELL) (L=0.25,W=1.5,AS=0.6375,AD=0.3375,PS=3.85,PD=1.95);\n"
|
||||
" device PMOS $2 (S=$9,G=$2,D=$6,B=NWELL) (L=0.25,W=1.5,AS=0.3375,AD=0.6375,PS=1.95,PD=3.85);\n"
|
||||
" device NMOS $3 (S=$13,G=$4,D=$14,B=BULK) (L=0.25,W=0.95,AS=0.40375,AD=0.21375,PS=2.75,PD=1.4);\n"
|
||||
" device NMOS $4 (S=$14,G=$2,D=$11,B=BULK) (L=0.25,W=0.95,AS=0.21375,AD=0.40375,PS=1.4,PD=2.75);\n"
|
||||
" device SOFT $5 (A=B,C=$2) (A=0,P=0);\n"
|
||||
" device SOFT $6 (A=A,C=$4) (A=0,P=0);\n"
|
||||
" device SOFT $7 (A=OUT,C=$6) (A=0,P=0);\n"
|
||||
" device SOFT $8 (A=OUT,C=$7) (A=0,P=0);\n"
|
||||
" device SOFT $9 (A=VDD,C=$9) (A=0,P=0);\n"
|
||||
" device SOFT $10 (A=OUT,C=$11) (A=0,P=0);\n"
|
||||
" device SOFT $11 (A=VSS,C=$13) (A=0,P=0);\n"
|
||||
"end;\n"
|
||||
"circuit TIE (NWELL=NWELL,VSS=VSS,VDD=VDD,BULK=BULK);\n"
|
||||
" device SOFT $1 (A=$2,C=NWELL) (A=0,P=0);\n"
|
||||
" device SOFT $2 (A=VDD,C=$2) (A=0,P=0);\n"
|
||||
" device SOFT $3 (A=VSS,C=$3) (A=0,P=0);\n"
|
||||
" device SOFT $4 (A=$3,C=BULK) (A=0,P=0);\n"
|
||||
"end;\n"
|
||||
"circuit INVX1 (NWELL=NWELL,IN=IN,VDD=VDD,OUT=OUT,VSS=VSS,BULK=BULK);\n"
|
||||
" device PMOS $1 (S=$5,G=$2,D=$7,B=NWELL) (L=0.25,W=1.5,AS=0.6375,AD=0.6375,PS=3.85,PD=3.85);\n"
|
||||
" device NMOS $2 (S=$10,G=$2,D=$8,B=BULK) (L=0.25,W=0.95,AS=0.40375,AD=0.40375,PS=2.75,PD=2.75);\n"
|
||||
" device SOFT $3 (A=IN,C=$2) (A=0,P=0);\n"
|
||||
" device SOFT $4 (A=VDD,C=$5) (A=0,P=0);\n"
|
||||
" device SOFT $5 (A=OUT,C=$7) (A=0,P=0);\n"
|
||||
" device SOFT $6 (A=OUT,C=$8) (A=0,P=0);\n"
|
||||
" device SOFT $7 (A=VSS,C=$10) (A=0,P=0);\n"
|
||||
"end;\n"
|
||||
);
|
||||
|
||||
// compare the collected test data
|
||||
|
||||
std::string au = tl::testdata ();
|
||||
au = tl::combine_path (au, "algo");
|
||||
au = tl::combine_path (au, "soft_connections_au.gds");
|
||||
|
||||
db::compare_layouts (_this, ly, au);
|
||||
}
|
||||
|
||||
|
||||
TEST(100_issue954)
|
||||
{
|
||||
|
|
|
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Reference in New Issue