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Updated test cases

This commit is contained in:
Matthias Koefferlein 2020-06-22 21:07:16 +02:00
parent b742542286
commit 408a0b571d
2 changed files with 15 additions and 15 deletions
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28
src/db/unit_tests/dbNetlistCompareTests.cc
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@ -2657,10 +2657,10 @@ TEST(17_InherentlyAmbiguousDecoder)
"match_nets B B\n"
"match_nets NB NB\n"
"match_nets NA NA\n"
"match_nets NQ0 NQ0\n"
"match_nets NQ2 NQ2\n"
"match_nets NQ1 NQ1\n"
"match_nets NQ3 NQ3\n"
"match_nets NQ2 NQ2\n"
"match_nets NQ0 NQ0\n"
"match_pins $0 $1\n"
"match_pins $1 $0\n"
"match_pins $2 $2\n"
@ -2922,24 +2922,24 @@ TEST(19_SymmetricCircuit)
"match_nets g1 G1\n"
"match_nets $44 YI\n"
"match_nets $14 WELL\n"
"match_nets $8 NET215\n"
"match_nets $9 NET175\n"
"match_nets $6 NET181\n"
"match_nets $4 NET200\n"
"match_nets nn1 NN1\n"
"match_nets $11 CS0\n"
"match_nets $13 CS1\n"
"match_nets nn2 NN2\n"
"match_nets nn2_ NN2_\n"
"match_nets q0 Q0\n"
"match_nets q1 Q1\n"
"match_nets $11 CS0\n"
"match_nets q0_ Q0_\n"
"match_nets $6 NET181\n"
"match_nets nn1 NN1\n"
"match_nets $8 NET215\n"
"match_nets $13 CS1\n"
"match_nets q1_ Q1_\n"
"match_nets a0_ A0_\n"
"match_nets $34 HNET48\n"
"match_nets nn1_ NN1_\n"
"match_nets a0 A0\n"
"match_nets $35 HNET44\n"
"match_nets nn1_ NN1_\n"
"match_nets $9 NET175\n"
"match_nets $4 NET200\n"
"match_nets a0_ A0_\n"
"match_nets $34 HNET48\n"
"match_pins VDD VDD\n"
"match_pins nn1_ NN1_\n"
"match_pins nn1 NN1\n"
@ -3805,11 +3805,11 @@ TEST(25c_JoinSymmetricNetsMultipleMessedUp)
// NOTE $1 and $2 are joined because they are symmetric
EXPECT_EQ (nl.to_string (),
"circuit NOR3 (A=A,C=C,B=B,OUT=OUT,VSS=VSS,VDD=VDD);\n"
" device PMOS $1 (S=$5,G=B,D=$3) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $1 (S=$6,G=B,D=$3) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $2 (S=OUT,G=A,D=VSS) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $3 (S=$3,G=A,D=OUT) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $4 (S=OUT,G=B,D=VSS) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $8 (S=VDD,G=C,D=$5) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $8 (S=VDD,G=C,D=$6) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $12 (S=VSS,G=C,D=OUT) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
)

2
testdata/lvs/double_height2.lvsdb vendored
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@ -314,8 +314,8 @@ Z(
N(5 2 1)
N(4 1 1)
N(2 4 1)
P(2 () 1)
P(0 () 1)
P(2 () 1)
P(4 () 1)
P(3 () 1)
P(1 () 1)