mirror of https://github.com/KLayout/klayout.git
Co-authored-by: Matthias Koefferlein <matthias@klayout.de>
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8d4da8b374
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@ -702,7 +702,8 @@ module DRC
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@l2n = RBA::LayoutToNetlist::new(@engine._dss)
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else
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layout = @engine.source.layout
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@l2n = RBA::LayoutToNetlist::new(layout.top_cell.name, layout.dbu)
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cell_name = @engine.source.cell_name
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@l2n = RBA::LayoutToNetlist::new(cell_name, layout.dbu)
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end
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@l2n.name = "DRC"
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@ -1617,3 +1617,39 @@ TEST(89_deep_with_mag_cop_size_aniso)
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run_test (_this, "89", true);
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}
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TEST(90_issue1594_dual_top)
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{
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std::string rs = tl::testdata ();
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rs += "/drc/issue_1594.drc";
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std::string input = tl::testdata ();
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input += "/drc/issue_1594.gds";
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std::string au = tl::testdata ();
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au += "/drc/issue_1594_au.cir";
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std::string output = this->tmp_file ("tmp.cir");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$drc_force_gc = true\n"
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"$drc_test_source = '%s'\n"
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"$drc_test_target = '%s'\n"
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, input, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro drc;
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drc.load_from (rs);
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EXPECT_EQ (drc.run (), 0);
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// verify
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CHECKPOINT ();
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compare_netlists (_this, output, au);
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}
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@ -0,0 +1,15 @@
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source($drc_test_source, "TOP1")
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# This is just a smoke test without actual devices
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l1 = input(1, 0)
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l2 = input(2, 0)
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l3 = input(3, 0)
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connect(l1, l2)
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connect(l2, l3)
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writer = RBA::NetlistSpiceWriter::new
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netlist.write($drc_test_target, writer, "netlist")
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Binary file not shown.
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@ -0,0 +1,5 @@
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* netlist
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* cell TOP1
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.SUBCKT TOP1
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.ENDS TOP1
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