WIP: refactoring, added first tests for LVS

testdata/lvs/inv.lvsdb

@@ -0,0 +1,239 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(INVERTER)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 'NWELL (1/0)')
+ layer(l8 'POLY (5/0)')
+ layer(l9 'CONTACT (6/0)')
+ layer(l10 'METAL1 (7/0)')
+ layer(l11 'METAL1_LABEL (7/1)')
+ layer(l12 'VIA1 (8/0)')
+ layer(l13 'METAL2 (9/0)')
+ layer(l14 'METAL2_LABEL (9/1)')
+ layer(l15)
+ layer(l23)
+ layer(l31)
+
+ # Mask layer connectivity
+ connect(l3 l3)
+ connect(l8 l8 l9)
+ connect(l9 l8 l9 l10 l23 l31)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14)
+ connect(l15 l15)
+ connect(l23 l9 l23)
+ connect(l31 l9 l31)
+
+ # Global nets and connectivity
+ global(l3 NWELL)
+ global(l15 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l23 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l8 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l23 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l31 (-575 -450) (450 900))
+  )
+  terminal(G
+   rect(l8 (-125 -450) (250 900))
+  )
+  terminal(D
+   rect(l31 (125 -450) (450 900))
+  )
+  terminal(B
+   rect(l15 (-125 -450) (250 900))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INVERTER
+
+  # Nets with their geometries
+  net(1 name(IN)
+   rect(l8 (900 50) (250 1050))
+   rect(l8 (-250 0) (250 3100))
+   rect(l8 (-250 0) (250 1650))
+   rect(l8 (-800 -3100) (550 400))
+   rect(l9 (-450 -300) (200 200))
+   rect(l10 (-300 -300) (400 400))
+   rect(l11 (-201 -201) (2 2))
+  )
+  net(2 name(VSS)
+   rect(l9 (550 300) (200 200))
+   rect(l9 (-200 300) (200 200))
+   rect(l10 (-250 -950) (300 1050))
+   rect(l12 (-250 -950) (200 200))
+   rect(l12 (-200 300) (200 200))
+   rect(l13 (-750 -850) (2000 1000))
+   rect(l14 (-101 -851) (2 2))
+   rect(l31 (-1451 49) (450 900))
+  )
+  net(3 name(VDD)
+   rect(l9 (550 4350) (200 200))
+   rect(l9 (-200 300) (200 200))
+   rect(l9 (-200 300) (200 200))
+   rect(l10 (-250 -1300) (300 1600))
+   rect(l12 (-250 -800) (200 200))
+   rect(l12 (-200 300) (200 200))
+   rect(l13 (-750 -850) (2000 1000))
+   rect(l14 (-151 -851) (2 2))
+   rect(l23 (-1401 -851) (450 1500))
+  )
+  net(4 name(OUT)
+   rect(l9 (1300 4350) (200 200))
+   rect(l9 (-200 300) (200 200))
+   rect(l9 (-200 300) (200 200))
+   rect(l9 (-200 -5250) (200 200))
+   rect(l9 (-200 300) (200 200))
+   rect(l10 (-250 3250) (300 1400))
+   rect(l10 (-300 -4600) (300 3200))
+   rect(l10 (-300 -2900) (450 400))
+   rect(l10 (-450 -1550) (300 850))
+   rect(l11 (-51 499) (2 2))
+   rect(l23 (-351 2649) (450 1500))
+   rect(l31 (-450 -5500) (450 900))
+  )
+  net(5 name(NWELL)
+   rect(l3 (0 2950) (2000 3200))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(1025 4950)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.675)
+   param(AD 0.675)
+   param(PS 3.9)
+   param(PD 3.9)
+   terminal(S 3)
+   terminal(G 1)
+   terminal(D 4)
+   terminal(B 5)
+  )
+  device(2 D$NMOS
+   location(1025 650)
+   param(L 0.25)
+   param(W 0.9)
+   param(AS 0.405)
+   param(AD 0.405)
+   param(PS 2.7)
+   param(PD 2.7)
+   terminal(S 2)
+   terminal(G 1)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INVERTER
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(IN))
+  net(3 name(OUT))
+  net(4 name(NWELL))
+  net(5 name(SUBSTRATE))
+  net(6 name(VDD))
+
+  # Outgoing pins and their connections to nets
+  pin(1)
+  pin(2)
+  pin(3)
+  pin(4)
+  pin(5)
+  pin(6)
+
+  # Devices and their connections
+  device(1 PMOS
+   name(P)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 6)
+   terminal(G 2)
+   terminal(D 3)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name(N)
+   param(L 0.25)
+   param(W 0.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 1)
+   terminal(B 5)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVERTER INVERTER match
+  xref(
+   net(1 2 match)
+   net(5 4 match)
+   net(4 3 match)
+   net(6 5 match)
+   net(3 6 match)
+   net(2 1 match)
+   pin(() 0 match)
+   pin(() 1 match)
+   pin(() 2 match)
+   pin(() 3 match)
+   pin(() 4 match)
+   pin(() 5 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+)

testdata/lvs/inv_layout.cir

@@ -0,0 +1,15 @@
+* Extracted by KLayout
+
+* cell INVERTER
+.SUBCKT INVERTER
+* net 1 IN
+* net 2 VSS
+* net 3 VDD
+* net 4 OUT
+* net 5 NWELL
+* net 6 SUBSTRATE
+* device instance $1 r0 *1 1.025,4.95 PMOS
+M$1 3 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
+* device instance $2 r0 *1 1.025,0.65 NMOS
+M$2 2 1 4 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
+.ENDS INVERTER