mirror of https://github.com/KLayout/klayout.git
Merge remote-tracking branch 'origin/netlist-compare-hardening' into macos-fixes
This commit is contained in:
Matthias
commit
29e8e148c9
File diff suppressed because it is too large
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@ -38,6 +38,8 @@ class DeviceCategorizer;
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class CircuitCategorizer;
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class CircuitMapper;
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class NetGraph;
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class SubCircuitEquivalenceTracker;
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class DeviceEquivalenceTracker;
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/**
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* @brief A receiver for netlist compare events
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@ -326,8 +328,8 @@ protected:
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bool all_subcircuits_verified (const db::Circuit *c, const std::set<const db::Circuit *> &verified_circuits) const;
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static void derive_pin_equivalence (const db::Circuit *ca, const db::Circuit *cb, CircuitPinMapper *circuit_pin_mapper);
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void do_pin_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, std::map<const db::Circuit *, CircuitMapper> &c12_circuit_and_pin_mapping, std::map<const db::Circuit *, CircuitMapper> &c22_circuit_and_pin_mapping, bool &pin_mismatch, bool &good) const;
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void do_device_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, const db::DeviceFilter &device_filter, DeviceCategorizer &device_categorizer, bool &good) const;
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void do_subcircuit_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, CircuitCategorizer &circuit_categorizer, const db::CircuitPinMapper &circuit_pin_mapper, std::map<const db::Circuit *, CircuitMapper> &c12_circuit_and_pin_mapping, std::map<const db::Circuit *, CircuitMapper> &c22_circuit_and_pin_mapping, bool &good) const;
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void do_device_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, const db::DeviceFilter &device_filter, DeviceCategorizer &device_categorizer, db::DeviceEquivalenceTracker &device_eq, bool &good) const;
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void do_subcircuit_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, CircuitCategorizer &circuit_categorizer, const db::CircuitPinMapper &circuit_pin_mapper, std::map<const db::Circuit *, CircuitMapper> &c12_circuit_and_pin_mapping, std::map<const db::Circuit *, CircuitMapper> &c22_circuit_and_pin_mapping, db::SubCircuitEquivalenceTracker &subcircuit_eq, bool &good) const;
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bool handle_pin_mismatch (const NetGraph &g1, const db::Circuit *c1, const db::Pin *pin1, const NetGraph &g2, const db::Circuit *c2, const db::Pin *p2) const;
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mutable NetlistCompareLogger *mp_logger;
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@ -2552,8 +2552,8 @@ TEST(17_InherentlyAmbiguousDecoder)
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"match_ambiguous_nets NQ1 NQ1\n"
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"match_ambiguous_nets NQ2 NQ2\n"
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"match_nets NQ3 NQ3\n"
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"match_ambiguous_nets NA NA\n"
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"match_ambiguous_nets NB NB\n"
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"match_nets NA NA\n"
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"match_nets NB NB\n"
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"match_nets B B\n"
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"match_nets A A\n"
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"match_pins $0 $1\n"
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@ -2657,10 +2657,10 @@ TEST(17_InherentlyAmbiguousDecoder)
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"match_nets B B\n"
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"match_nets NB NB\n"
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"match_nets NA NA\n"
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"match_nets NQ0 NQ0\n"
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"match_nets NQ2 NQ2\n"
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"match_nets NQ1 NQ1\n"
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"match_nets NQ3 NQ3\n"
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"match_nets NQ2 NQ2\n"
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"match_nets NQ0 NQ0\n"
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"match_pins $0 $1\n"
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"match_pins $1 $0\n"
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"match_pins $2 $2\n"
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@ -2922,24 +2922,24 @@ TEST(19_SymmetricCircuit)
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"match_nets g1 G1\n"
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"match_nets $44 YI\n"
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"match_nets $14 WELL\n"
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"match_nets $8 NET215\n"
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"match_nets $9 NET175\n"
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"match_nets $6 NET181\n"
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"match_nets $4 NET200\n"
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"match_nets nn1 NN1\n"
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"match_nets $11 CS0\n"
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"match_nets $13 CS1\n"
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"match_nets nn2 NN2\n"
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"match_nets nn2_ NN2_\n"
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"match_nets q0 Q0\n"
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"match_nets q1 Q1\n"
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"match_nets $11 CS0\n"
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"match_nets q0_ Q0_\n"
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"match_nets $6 NET181\n"
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"match_nets nn1 NN1\n"
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"match_nets $8 NET215\n"
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"match_nets $13 CS1\n"
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"match_nets q1_ Q1_\n"
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"match_nets a0_ A0_\n"
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"match_nets $34 HNET48\n"
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"match_nets nn1_ NN1_\n"
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"match_nets a0 A0\n"
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"match_nets $35 HNET44\n"
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"match_nets nn1_ NN1_\n"
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"match_nets $9 NET175\n"
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"match_nets $4 NET200\n"
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"match_nets a0_ A0_\n"
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"match_nets $34 HNET48\n"
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"match_pins VDD VDD\n"
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"match_pins nn1_ NN1_\n"
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"match_pins nn1 NN1\n"
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@ -3576,7 +3576,7 @@ TEST(23_NodesRemovedWithError)
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"pin_mismatch (null) BULK\n"
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"pin_mismatch (null) $6\n"
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"match_subcircuits $1 $1\n"
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"subcircuit_mismatch $2 $2\n"
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"match_subcircuits $2 $2\n"
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"end_circuit INV2PAIR INV2PAIR NOMATCH\n"
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"circuit_skipped RINGO RINGO"
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);
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@ -3805,11 +3805,11 @@ TEST(25c_JoinSymmetricNetsMultipleMessedUp)
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// NOTE $1 and $2 are joined because they are symmetric
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EXPECT_EQ (nl.to_string (),
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"circuit NOR3 (A=A,C=C,B=B,OUT=OUT,VSS=VSS,VDD=VDD);\n"
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" device PMOS $1 (S=$5,G=B,D=$3) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
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" device PMOS $1 (S=$6,G=B,D=$3) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
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" device NMOS $2 (S=OUT,G=A,D=VSS) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
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" device PMOS $3 (S=$3,G=A,D=OUT) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
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" device NMOS $4 (S=OUT,G=B,D=VSS) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
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" device PMOS $8 (S=VDD,G=C,D=$5) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
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" device PMOS $8 (S=VDD,G=C,D=$6) (L=0.27,W=3.3,AS=0,AD=0,PS=0,PD=0);\n"
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" device NMOS $12 (S=VSS,G=C,D=OUT) (L=0.23,W=2.05,AS=0,AD=0,PS=0,PD=0);\n"
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"end;\n"
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)
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@ -314,8 +314,8 @@ Z(
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N(5 2 1)
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N(4 1 1)
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N(2 4 1)
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P(2 () 1)
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P(0 () 1)
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P(2 () 1)
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P(4 () 1)
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P(3 () 1)
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P(1 () 1)
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@ -850,7 +850,7 @@ xref(
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device(1 1 match)
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)
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)
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circuit(ND2X1 ND2X1 nomatch
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circuit(ND2X1 ND2X1 match
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xref(
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net(4 8 mismatch)
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net(5 4 mismatch)
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@ -867,10 +867,10 @@ xref(
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pin(6 6 match)
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pin(0 0 match)
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pin(2 2 match)
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device(3 3 match)
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device(4 4 match)
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device(3 3 mismatch)
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device(1 1 match)
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device(2 2 match)
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device(1 1 mismatch)
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)
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)
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circuit(RINGO RINGO match
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@ -1,912 +0,0 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l4 '1/0')
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layer(l5 '5/0')
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layer(l10 '8/0')
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layer(l13 '9/0')
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layer(l14 '10/0')
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layer(l15 '11/0')
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layer(l9)
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layer(l3)
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layer(l1)
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layer(l11)
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layer(l8)
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layer(l6)
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layer(l12)
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# Mask layer connectivity
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connect(l4 l4 l11)
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connect(l5 l5 l10)
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connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
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connect(l13 l10 l13 l14)
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connect(l14 l13 l14 l15)
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connect(l15 l14 l15)
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connect(l9 l9)
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connect(l3 l10 l3)
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connect(l1 l10 l1)
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connect(l11 l4 l10 l11)
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connect(l8 l10 l8)
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connect(l6 l10 l6)
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connect(l12 l10 l12)
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# Global nets and connectivity
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global(l9 SUBSTRATE)
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global(l12 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l3 (125 -750) (450 1500))
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)
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terminal(G
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rect(l5 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l1 (-550 -750) (425 1500))
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)
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terminal(B
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rect(l4 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(l3 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l5 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l1 (125 -750) (425 1500))
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)
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terminal(B
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rect(l4 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$2 PMOS
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terminal(S
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rect(l3 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l5 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l1 (125 -750) (425 1500))
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)
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terminal(B
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rect(l4 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l8 (125 -475) (450 950))
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)
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terminal(G
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rect(l5 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (-550 -475) (425 950))
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)
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terminal(B
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rect(l9 (-125 -475) (250 950))
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)
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)
|
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device(D$NMOS$1 NMOS
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terminal(S
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||||
rect(l8 (-575 -475) (450 950))
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)
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terminal(G
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rect(l5 (-125 -475) (250 950))
|
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)
|
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
|
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terminal(B
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rect(l9 (-125 -475) (250 950))
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)
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)
|
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device(D$NMOS$2 NMOS
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terminal(S
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rect(l8 (-550 -475) (425 950))
|
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)
|
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terminal(G
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||||
rect(l5 (-125 -475) (250 950))
|
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)
|
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terminal(D
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||||
rect(l6 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
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||||
rect(l9 (-125 -475) (250 950))
|
||||
)
|
||||
)
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|
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# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
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||||
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# Circuit boundary
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rect((-100 400) (2600 7600))
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||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
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||||
rect(l10 (1110 5160) (180 180))
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||||
rect(l10 (-180 920) (180 180))
|
||||
rect(l10 (-180 -730) (180 180))
|
||||
rect(l13 (-240 -790) (300 1700))
|
||||
rect(l13 (-1350 0) (2400 800))
|
||||
rect(l13 (-1151 -401) (2 2))
|
||||
rect(l3 (-251 -2151) (425 1500))
|
||||
rect(l3 (-450 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l10 (1810 1770) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l10 (-1580 3760) (180 180))
|
||||
rect(l10 (-180 -730) (180 180))
|
||||
rect(l10 (-180 -730) (180 180))
|
||||
rect(l10 (1220 920) (180 180))
|
||||
rect(l10 (-180 -1280) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l13 (-110 1390) (300 1400))
|
||||
polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l13 (-141 -501) (2 2))
|
||||
rect(l13 (-1751 1099) (300 1400))
|
||||
rect(l13 (1100 -1700) (300 300))
|
||||
rect(l13 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l10 (410 1770) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l13 (-240 -1300) (300 1360))
|
||||
rect(l13 (-650 -2160) (2400 800))
|
||||
rect(l13 (-1151 -401) (2 2))
|
||||
rect(l6 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (1000 1660) (425 950))
|
||||
rect(l8 (-450 -950) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l4 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(6 name(B)
|
||||
rect(l5 (1425 2860) (250 1940))
|
||||
rect(l5 (-345 -950) (300 300))
|
||||
rect(l5 (-205 650) (250 2000))
|
||||
rect(l5 (-250 -2000) (250 2000))
|
||||
rect(l5 (-250 -5390) (250 1450))
|
||||
rect(l10 (-285 1050) (180 180))
|
||||
rect(l13 (-71 -91) (2 2))
|
||||
rect(l13 (-171 -151) (300 300))
|
||||
)
|
||||
net(7 name(A)
|
||||
rect(l5 (725 2860) (250 1940))
|
||||
rect(l5 (-325 -1850) (300 300))
|
||||
rect(l5 (-225 1550) (250 2000))
|
||||
rect(l5 (-250 -2000) (250 2000))
|
||||
rect(l5 (-250 -5390) (250 1450))
|
||||
rect(l10 (-265 150) (180 180))
|
||||
rect(l13 (-91 -91) (2 2))
|
||||
rect(l13 (-151 -151) (300 300))
|
||||
)
|
||||
net(8 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(5)
|
||||
pin(6 name(B))
|
||||
pin(7 name(A))
|
||||
pin(8 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 7)
|
||||
terminal(D 2)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 6)
|
||||
terminal(D 2)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 4)
|
||||
terminal(G 7)
|
||||
terminal(D 3)
|
||||
terminal(B 8)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 4)
|
||||
terminal(G 6)
|
||||
terminal(D 2)
|
||||
terminal(B 8)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l10 (410 6260) (180 180))
|
||||
rect(l10 (-180 -730) (180 180))
|
||||
rect(l10 (-180 -730) (180 180))
|
||||
rect(l13 (-240 -240) (300 1400))
|
||||
rect(l13 (-650 300) (1800 800))
|
||||
rect(l13 (-1450 -1100) (300 300))
|
||||
rect(l13 (299 399) (2 2))
|
||||
rect(l3 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l10 (1110 5160) (180 180))
|
||||
rect(l10 (-180 920) (180 180))
|
||||
rect(l10 (-180 -730) (180 180))
|
||||
rect(l10 (-180 -4120) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l13 (-240 -790) (300 4790))
|
||||
rect(l13 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l10 (410 1770) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l13 (-240 -1300) (300 1360))
|
||||
rect(l13 (-650 -2160) (1800 800))
|
||||
rect(l13 (-851 -401) (2 2))
|
||||
rect(l8 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l4 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l5 (725 2860) (250 1940))
|
||||
rect(l5 (-525 -1850) (300 300))
|
||||
rect(l5 (-25 1550) (250 2000))
|
||||
rect(l5 (-250 -2000) (250 2000))
|
||||
rect(l5 (-250 -5390) (250 1450))
|
||||
rect(l10 (-465 150) (180 180))
|
||||
rect(l13 (-91 -91) (2 2))
|
||||
rect(l13 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l13 (4040 2950) (610 300))
|
||||
)
|
||||
net(2
|
||||
rect(l13 (5550 2950) (900 300))
|
||||
)
|
||||
net(3
|
||||
rect(l13 (7350 2950) (900 300))
|
||||
)
|
||||
net(4
|
||||
rect(l13 (9150 2950) (900 300))
|
||||
)
|
||||
net(5
|
||||
rect(l13 (10950 2950) (900 300))
|
||||
)
|
||||
net(6
|
||||
rect(l13 (12750 2950) (900 300))
|
||||
)
|
||||
net(7
|
||||
rect(l13 (14550 2950) (900 300))
|
||||
)
|
||||
net(8
|
||||
rect(l13 (16350 2950) (900 300))
|
||||
)
|
||||
net(9
|
||||
rect(l13 (18150 2950) (900 300))
|
||||
)
|
||||
net(10
|
||||
rect(l13 (19950 2950) (900 300))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l13 (21750 2950) (900 300))
|
||||
rect(l13 (-19530 590) (320 320))
|
||||
rect(l13 (17820 -320) (320 320))
|
||||
rect(l14 (-18400 -260) (200 200))
|
||||
rect(l14 (17940 -200) (200 200))
|
||||
rect(l15 (-18040 -300) (17740 400))
|
||||
rect(l15 (-17921 -201) (2 2))
|
||||
rect(l15 (-221 -201) (400 400))
|
||||
rect(l15 (17740 -400) (400 400))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l4 (500 4500) (1400 3500))
|
||||
rect(l4 (-1900 -3500) (600 3500))
|
||||
rect(l4 (23300 -3500) (1400 3500))
|
||||
rect(l4 (-100 -3500) (600 3500))
|
||||
rect(l10 (-24690 -1240) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l10 (-180 -1280) (180 180))
|
||||
rect(l10 (23220 370) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l10 (-180 -1280) (180 180))
|
||||
rect(l13 (-21741 859) (2 2))
|
||||
rect(l13 (-2351 -451) (1200 800))
|
||||
rect(l13 (-750 -1450) (300 1400))
|
||||
rect(l13 (-101 -351) (2 2))
|
||||
rect(l13 (-1251 -401) (600 800))
|
||||
rect(l13 (23400 -800) (1200 800))
|
||||
rect(l13 (-750 -1450) (300 1400))
|
||||
rect(l13 (-101 -351) (2 2))
|
||||
rect(l13 (549 -401) (600 800))
|
||||
rect(l11 (-24850 -1500) (500 1500))
|
||||
rect(l11 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l13 (23440 3840) (320 320))
|
||||
rect(l14 (-260 -260) (200 200))
|
||||
rect(l15 (-101 -101) (2 2))
|
||||
rect(l15 (-201 -201) (400 400))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l13 (2440 2940) (320 320))
|
||||
rect(l14 (-260 -260) (200 200))
|
||||
rect(l15 (-101 -101) (2 2))
|
||||
rect(l15 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l10 (1110 1610) (180 180))
|
||||
rect(l10 (-180 -1280) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l10 (23220 370) (180 180))
|
||||
rect(l10 (-180 -1280) (180 180))
|
||||
rect(l10 (-180 370) (180 180))
|
||||
rect(l13 (-21741 -391) (2 2))
|
||||
rect(l13 (-1901 -401) (300 1400))
|
||||
rect(l13 (-750 -1450) (1200 800))
|
||||
rect(l13 (-551 -401) (2 2))
|
||||
rect(l13 (-1251 -401) (600 800))
|
||||
rect(l13 (23850 -750) (300 1400))
|
||||
rect(l13 (-750 -1450) (1200 800))
|
||||
rect(l13 (-551 -401) (2 2))
|
||||
rect(l13 (549 -401) (600 800))
|
||||
rect(l12 (-24850 -800) (500 1500))
|
||||
rect(l12 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(2 2 match)
|
||||
device(1 1 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 nomatch
|
||||
xref(
|
||||
net(4 8 mismatch)
|
||||
net(5 4 mismatch)
|
||||
net(7 6 match)
|
||||
net(6 5 match)
|
||||
net(2 2 mismatch)
|
||||
net(8 7 mismatch)
|
||||
net(1 1 mismatch)
|
||||
net(3 3 mismatch)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(4 4 match)
|
||||
device(3 3 mismatch)
|
||||
device(2 2 match)
|
||||
device(1 1 mismatch)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(1 1 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Loading…
Reference in New Issue