mirror of https://github.com/KLayout/klayout.git
Added soft-connect test for valid layout
This commit is contained in:
Matthias Koefferlein
parent
962e212e19
commit
265b5680de
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@ -307,3 +307,9 @@ TEST(50_SoftConnection)
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run_test (_this, "soft_connect1", "soft_connect1.gds", true, false /*no LVS*/);
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}
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// No errors
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TEST(51_SoftConnection)
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{
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run_test (_this, "soft_connect2", "soft_connect2.gds", true, false /*no LVS*/);
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}
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@ -0,0 +1,13 @@
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* Extracted by KLayout
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.SUBCKT TOP A Q VDD SUBSTRATE|VSS
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X$1 SUBSTRATE|VSS VDD VDD \$1 Q SUBSTRATE|VSS INV
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X$2 SUBSTRATE|VSS VDD VDD A \$1 SUBSTRATE|VSS INV
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.ENDS TOP
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.SUBCKT INV \$1 \$2 \$3 \$4 \$5 SUBSTRATE
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M$1 \$2 \$4 \$5 \$3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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M$2 \$1 \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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.ENDS INV
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Binary file not shown.
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@ -0,0 +1,213 @@
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#%l2n-klayout
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W(TOP)
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U(0.001)
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L(l3 '1/0')
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L(l4 '3/0')
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L(l15 '3/1')
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L(l8 '4/0')
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L(l11 '5/0')
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L(l12 '6/0')
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L(l16 '6/1')
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L(l13 '7/0')
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L(l14 '8/0')
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L(l17 '8/1')
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L(l7)
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L(l10)
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L(l2)
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L(l9)
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L(l6)
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C(l3 l3 l10)
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C(l4 l4 l15 l11)
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C(l15 l4 l15)
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C(l8 l8 l12 l10 l2 l9 l6)
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CS(l8 l10 l2 l9 l6)
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C(l11 l4 l11 l12)
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CS(l11 l4)
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C(l12 l8 l11 l12 l16 l13)
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C(l16 l12 l16)
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C(l13 l12 l13 l14)
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C(l14 l13 l14 l17)
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C(l17 l14 l17)
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C(l7 l7)
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C(l10 l3 l8 l10)
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CS(l10 l3)
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C(l2 l8 l2)
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C(l9 l8 l9)
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C(l6 l8 l6)
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G(l7 SUBSTRATE)
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G(l9 SUBSTRATE)
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GS(l9 SUBSTRATE)
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K(PMOS MOS4)
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K(NMOS MOS4)
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D(D$PMOS PMOS
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T(S
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R(l2 (-900 -475) (775 950))
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)
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T(G
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R(l4 (-125 -475) (250 950))
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)
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T(D
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R(l2 (125 -475) (775 950))
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)
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T(B
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R(l3 (-125 -475) (250 950))
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)
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)
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D(D$NMOS NMOS
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T(S
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R(l6 (-900 -475) (775 950))
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)
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T(G
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R(l4 (-125 -475) (250 950))
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)
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T(D
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R(l6 (125 -475) (775 950))
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)
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T(B
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R(l7 (-125 -475) (250 950))
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)
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)
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X(INV
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R((-1500 -800) (3000 4600))
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N(1
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R(l8 (290 -310) (220 220))
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R(l8 (-220 180) (220 220))
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R(l12 (-290 -690) (360 760))
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R(l13 (-305 -705) (250 250))
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R(l13 (-250 150) (250 250))
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R(l14 (-2025 -775) (3000 900))
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R(l6 (-1375 -925) (775 950))
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)
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N(2
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R(l8 (290 2490) (220 220))
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R(l8 (-220 180) (220 220))
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R(l12 (-290 -690) (360 760))
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R(l13 (-305 -705) (250 250))
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R(l13 (-250 150) (250 250))
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R(l14 (-2025 -775) (3000 900))
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R(l2 (-1375 -925) (775 950))
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)
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N(3
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R(l3 (-1500 1800) (3000 2000))
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)
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N(4
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R(l4 (-125 -250) (250 2500))
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R(l4 (-250 -3050) (250 1600))
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R(l4 (-250 1200) (250 1600))
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)
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N(5
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R(l8 (-510 -310) (220 220))
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R(l8 (-220 180) (220 220))
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R(l8 (-220 2180) (220 220))
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R(l8 (-220 180) (220 220))
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R(l12 (-290 -3530) (360 2840))
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R(l12 (-360 -2800) (360 760))
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R(l12 (-360 2040) (360 760))
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R(l2 (-680 -855) (775 950))
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R(l6 (-775 -3750) (775 950))
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)
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N(6 I(SUBSTRATE))
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P(1)
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P(2)
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P(3)
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P(4)
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P(5)
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P(6 I(SUBSTRATE))
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D(1 D$PMOS
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Y(0 2800)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 5)
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T(G 4)
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T(D 2)
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T(B 3)
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)
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D(2 D$NMOS
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Y(0 0)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 5)
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T(G 4)
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T(D 1)
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T(B 6)
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)
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)
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X(TOP
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R((600 800) (8880 4600))
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N(1
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R(l4 (2920 2600) (2880 400))
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R(l11 (-300 -300) (200 200))
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R(l12 (-300 -300) (690 400))
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)
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N(2 I(A)
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R(l4 (6600 2600) (2880 400))
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R(l15 (-2380 -200) (0 0))
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)
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N(3 I(Q)
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R(l12 (1810 2600) (690 400))
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R(l16 (-400 -200) (0 0))
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)
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N(4 I(VDD)
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R(l3 (4000 3400) (1600 2000))
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R(l3 (-5000 -2000) (1000 2000))
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R(l3 (6400 -2000) (1000 2000))
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R(l8 (-8000 -900) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l8 (7200 200) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l12 (-7900 -350) (800 900))
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R(l12 (6600 -900) (800 900))
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R(l13 (-7900 -350) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l13 (7200 200) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l14 (-4400 -350) (1200 900))
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R(l14 (-4800 -900) (1000 900))
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R(l14 (6400 -900) (1000 900))
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R(l17 (-4800 -450) (0 0))
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)
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N(5 I('SUBSTRATE,VSS')
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R(l8 (1000 1700) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l8 (7200 200) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l12 (-7900 -350) (800 900))
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R(l12 (6600 -900) (800 900))
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R(l13 (-7900 -350) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l13 (7200 200) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l14 (-4400 -350) (1200 900))
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R(l14 (-4800 -900) (1000 900))
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R(l14 (6400 -900) (1000 900))
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R(l17 (-4800 -550) (0 0))
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)
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P(2 I(A))
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P(3 I(Q))
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P(4 I(VDD))
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P(5 I('SUBSTRATE,VSS'))
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X(1 INV Y(3000 1600)
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P(0 5)
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P(1 4)
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P(2 4)
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P(3 1)
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P(4 3)
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P(5 5)
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)
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X(2 INV Y(6600 1600)
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P(0 5)
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P(1 4)
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P(2 4)
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P(3 2)
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P(4 1)
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P(5 5)
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)
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)
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@ -0,0 +1,92 @@
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$lvs_test_source && source($lvs_test_source)
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if $lvs_test_target_l2n
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report_netlist($lvs_test_target_l2n)
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else
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report_netlist
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end
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writer = write_spice(true, false)
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$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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nplus = input(2, 1)
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pplus = input(2, 2)
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poly = input(3, 0)
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poly_lbl = input(3, 1)
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diff_cont = input(4, 0)
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poly_cont = input(5, 0)
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metal1 = input(6, 0)
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metal1_lbl = input(6, 1)
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via1 = input(7, 0)
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metal2 = input(8, 0)
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metal2_lbl = input(8, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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psd = nil
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nsd = nil
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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ntie = active_in_nwell & nplus
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ptie = active_outside_nwell & pplus
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly })
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# Define connectivity for netlist extraction
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# Inter-layer
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soft_connect(diff_cont, psd)
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soft_connect(diff_cont, nsd)
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soft_connect(diff_cont, ptie)
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soft_connect(diff_cont, ntie)
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soft_connect(ntie, nwell)
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soft_connect(poly_cont, poly)
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connect(diff_cont, metal1)
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connect(poly_cont, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# attach labels
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connect(poly, poly_lbl)
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connect(metal1, metal1_lbl)
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connect(metal2, metal2_lbl)
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# Global
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connect_global(bulk, "SUBSTRATE")
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soft_connect_global(ptie, "SUBSTRATE")
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# Netlist section (NOTE: we only check log here)
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netlist
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netlist.simplify
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