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Added new tests

This commit is contained in:
Matthias Koefferlein 2021-07-19 08:32:55 +02:00
parent 2e21498422
commit 23d0fcae8d
44 changed files with 6605 additions and 0 deletions
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20
src/lvs/unit_tests/lvsSimpleTests.cc
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@ -241,3 +241,23 @@ TEST(26_enableWandL)
run_test (_this, "enable_wl2", "resistor.gds");
run_test (_this, "enable_wl3", "resistor.gds");
}
TEST(27_BlackBoxDevicesWithAlign)
{
run_test (_this, "bbdevices1", "bbdevices1.gds");
run_test (_this, "bbdevices2", "bbdevices2.gds");
run_test (_this, "bbdevices3", "bbdevices3.gds");
run_test (_this, "bbdevices4", "bbdevices4.gds");
run_test (_this, "bbdevices5", "bbdevices5.gds");
run_test (_this, "bbdevices6", "bbdevices6.gds");
}
TEST(28_BlackBoxDevicesWithBlank)
{
run_test (_this, "bbdevices1b", "bbdevices1.gds");
run_test (_this, "bbdevices2b", "bbdevices2.gds");
run_test (_this, "bbdevices3b", "bbdevices3.gds");
run_test (_this, "bbdevices4b", "bbdevices4.gds");
run_test (_this, "bbdevices5b", "bbdevices5.gds");
run_test (_this, "bbdevices6b", "bbdevices6.gds");
}

32
testdata/lvs/bbdevices.net vendored Normal file
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@ -0,0 +1,32 @@
.SUBCKT TESTALL
XUFBGA A1 B1 FBGATEST
XUFWB C1 G1 FWBTEST
XUFDP B1 C1 FDPTEST
XUDP C1 D1 DPTEST
XUBDP D1 E1 BDPTEST
XUBWB D1 H1 BWBTEST
XUBBGA E1 F1 BBGATEST
.SUBCKT FBGATEST A B
.ENDS
.SUBCKT FWBTEST A B
.ENDS
.SUBCKT FDPTEST A B
.ENDS
.SUBCKT DPTEST A B
.ENDS
.SUBCKT BDPTEST A B
.ENDS
.SUBCKT BWBTEST A B
.ENDS
.SUBCKT BBGATEST A B
.ENDS
.ENDS

75
testdata/lvs/bbdevices1.cir vendored Normal file
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@ -0,0 +1,75 @@
* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $10 r0 *1 0,0
X$10 3 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 4 BBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
* net 1 B
* net 2 A
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
* net 1 B
* net 2 A
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
* net 1 A
* net 2 B
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 2
* net 1 B
* net 2 A
* net 3 BBGATEST
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
* net 1 B
* net 2 A
* net 3 FBGATEST
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 2
* net 1 B
* net 2 A
* net 3 FWBTEST
.ENDS FWBTEST
* cell BWBTEST
* pin A
.SUBCKT BWBTEST 2
* net 1 B
* net 2 A
* net 3 BWBTEST
.ENDS BWBTEST

BIN
testdata/lvs/bbdevices1.gds vendored Normal file
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74
testdata/lvs/bbdevices1.lvs vendored Normal file
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@ -0,0 +1,74 @@
source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
align
compare

464
testdata/lvs/bbdevices1.lvsdb vendored Normal file
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@ -0,0 +1,464 @@
#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Nets with their geometries
net(1 name(B)
rect(l15 (832000 -242000) (93500 75500))
rect(l15 (-46751 -37751) (2 2))
)
net(2 name(A)
rect(l15 (576500 -249000) (105500 81500))
rect(l15 (-52751 -40751) (2 2))
)
net(3 name(BWBTEST)
rect(l15 (754499 -114001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Nets with their geometries
net(1 name(B)
rect(l3 (793500 427000) (120500 82000))
rect(l3 (-60251 -41001) (2 2))
)
net(2 name(A)
rect(l3 (572500 432500) (74500 73500))
rect(l3 (-37251 -36751) (2 2))
)
net(3 name(FWBTEST)
rect(l3 (797999 565499) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Nets with their geometries
net(1 name(B)
rect(l3 (-221000 412500) (162000 152500))
rect(l3 (-81001 -76251) (2 2))
)
net(2 name(A)
rect(l3 (-449500 422500) (146000 144500))
rect(l3 (-71001 -71251) (2 2))
)
net(3 name(FBGATEST)
rect(l3 (-417001 610499) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Nets with their geometries
net(1 name(B)
rect(l15 (-468000 -280000) (177000 189000))
rect(l15 (-88501 -94501) (2 2))
)
net(2 name(A)
rect(l15 (-218500 -290000) (193000 203000))
rect(l15 (-94001 -101501) (2 2))
)
net(3 name(BBGATEST)
rect(l15 (-422001 -313001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Nets with their geometries
net(1 name(A)
rect(l16 (317000 -232000) (92000 92000))
rect(l16 (-46001 -46001) (2 2))
)
net(2 name(B)
rect(l16 (95500 -231000) (116000 97000))
rect(l16 (-58001 -48501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Nets with their geometries
net(1 name(B)
rect(l11 (323000 151500) (76000 83000))
rect(l11 (-38001 -41501) (2 2))
)
net(2 name(A)
rect(l11 (96500 159500) (90000 73000))
rect(l11 (-45001 -36501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Nets with their geometries
net(1 name(B)
rect(l1 (327000 436500) (72000 93000))
rect(l1 (-36001 -46501) (2 2))
)
net(2 name(A)
rect(l1 (101500 443500) (82000 84000))
rect(l1 (-41001 -42001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-270500 7500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(10 BWBTEST location(0 0) pin(0 3))
circuit(14 BBGATEST location(0 0) pin(0 4))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
net(1 1 match)
net(2 2 match)
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(DPTEST DPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
net(() 1 match)
net(1 2 match)
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL match
xref(
net(2 2 match)
net(1 3 match)
net(3 5 match)
net(4 6 match)
circuit(14 7 match)
circuit(9 5 match)
circuit(10 6 match)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

57
testdata/lvs/bbdevices1b.cir vendored Normal file
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@ -0,0 +1,57 @@
* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $10 r0 *1 0,0
X$10 3 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 4 BBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 1
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 1
.ENDS FWBTEST
* cell BWBTEST
* pin A
.SUBCKT BWBTEST 1
.ENDS BWBTEST

75
testdata/lvs/bbdevices1b.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.simplify
compare

340
testdata/lvs/bbdevices1b.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Outgoing pins and their connections to nets
pin(name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-270500 7500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(10 BWBTEST location(0 0) pin(0 3))
circuit(14 BBGATEST location(0 0) pin(0 4))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(DPTEST DPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL match
xref(
net(2 2 match)
net(1 3 match)
net(3 5 match)
net(4 6 match)
circuit(14 7 match)
circuit(9 5 match)
circuit(10 6 match)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

79
testdata/lvs/bbdevices2.cir vendored Normal file
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@ -0,0 +1,79 @@
* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 4 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 5 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 3 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 5 6 BDPTEST
* cell instance $10 r0 *1 0,0
X$10 8 5 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 7 6 BBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
* net 1 B
* net 2 A
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
* net 1 B
* net 2 A
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
* net 1 A
* net 2 B
.ENDS BDPTEST
* cell BBGATEST
* pin B
* pin A
.SUBCKT BBGATEST 1 2
* net 1 B
* net 2 A
* net 3 BBGATEST
.ENDS BBGATEST
* cell FBGATEST
* pin B
* pin A
.SUBCKT FBGATEST 1 2
* net 1 B
* net 2 A
* net 3 FBGATEST
.ENDS FBGATEST
* cell FWBTEST
* pin B
* pin A
.SUBCKT FWBTEST 1 2
* net 1 B
* net 2 A
* net 3 FWBTEST
.ENDS FWBTEST
* cell BWBTEST
* pin B
* pin A
.SUBCKT BWBTEST 1 2
* net 1 B
* net 2 A
* net 3 BWBTEST
.ENDS BWBTEST

BIN
testdata/lvs/bbdevices2.gds vendored Normal file
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Binary file not shown.

74
testdata/lvs/bbdevices2.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
align
compare

496
testdata/lvs/bbdevices2.lvsdb vendored Normal file
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@ -0,0 +1,496 @@
#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Nets with their geometries
net(1 name(B)
rect(l15 (832000 -242000) (93500 75500))
rect(l15 (-46751 -37751) (2 2))
)
net(2 name(A)
rect(l15 (576500 -249000) (105500 81500))
rect(l15 (-52751 -40751) (2 2))
)
net(3 name(BWBTEST)
rect(l15 (754499 -114001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Nets with their geometries
net(1 name(B)
rect(l3 (793500 427000) (120500 82000))
rect(l3 (-60251 -41001) (2 2))
)
net(2 name(A)
rect(l3 (572500 432500) (74500 73500))
rect(l3 (-37251 -36751) (2 2))
)
net(3 name(FWBTEST)
rect(l3 (797999 565499) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Nets with their geometries
net(1 name(B)
rect(l3 (-221000 412500) (162000 152500))
rect(l3 (-81001 -76251) (2 2))
)
net(2 name(A)
rect(l3 (-449500 422500) (146000 144500))
rect(l3 (-71001 -71251) (2 2))
)
net(3 name(FBGATEST)
rect(l3 (-417001 610499) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Nets with their geometries
net(1 name(B)
rect(l15 (-468000 -280000) (177000 189000))
rect(l15 (-88501 -94501) (2 2))
)
net(2 name(A)
rect(l15 (-218500 -290000) (193000 203000))
rect(l15 (-94001 -101501) (2 2))
)
net(3 name(BBGATEST)
rect(l15 (-422001 -313001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Nets with their geometries
net(1 name(A)
rect(l16 (317000 -232000) (92000 92000))
rect(l16 (-46001 -46001) (2 2))
)
net(2 name(B)
rect(l16 (95500 -231000) (116000 97000))
rect(l16 (-58001 -48501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Nets with their geometries
net(1 name(B)
rect(l11 (323000 151500) (76000 83000))
rect(l11 (-38001 -41501) (2 2))
)
net(2 name(A)
rect(l11 (96500 159500) (90000 73000))
rect(l11 (-45001 -36501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Nets with their geometries
net(1 name(B)
rect(l1 (327000 436500) (72000 93000))
rect(l1 (-36001 -46501) (2 2))
)
net(2 name(A)
rect(l1 (101500 443500) (82000 84000))
rect(l1 (-41001 -42001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l2 (-401420 456500) (50730 78500))
)
net(4
rect(l2 (822690 427000) (63970 82000))
)
net(5
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-270500 7500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(6
rect(l14 (-126000 -195000) (292000 25000))
)
net(7
rect(l14 (-410240 -216150) (83240 87150))
)
net(8
rect(l14 (846960 -242000) (77190 75500))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0)
pin(0 4)
pin(1 1)
)
circuit(7 DPTEST location(0 0)
pin(0 5)
pin(1 1)
)
circuit(8 FBGATEST location(0 0)
pin(0 2)
pin(1 3)
)
circuit(9 BDPTEST location(0 0)
pin(0 5)
pin(1 6)
)
circuit(10 BWBTEST location(0 0)
pin(0 8)
pin(1 5)
)
circuit(14 BBGATEST location(0 0)
pin(0 7)
pin(1 6)
)
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
net(1 1 match)
net(2 2 match)
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(DPTEST DPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(testall TESTALL match
xref(
net(3 1 match)
net(2 2 match)
net(1 3 match)
net(5 5 match)
net(6 6 match)
net(7 8 match)
net(4 4 match)
net(8 7 match)
circuit(14 7 match)
circuit(9 5 match)
circuit(10 6 match)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

61
testdata/lvs/bbdevices2b.cir vendored Normal file
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 4 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 5 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 3 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 5 6 BDPTEST
* cell instance $10 r0 *1 0,0
X$10 8 5 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 7 6 BBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
.ENDS BDPTEST
* cell BBGATEST
* pin B
* pin A
.SUBCKT BBGATEST 1 2
.ENDS BBGATEST
* cell FBGATEST
* pin B
* pin A
.SUBCKT FBGATEST 1 2
.ENDS FBGATEST
* cell FWBTEST
* pin B
* pin A
.SUBCKT FWBTEST 1 2
.ENDS FWBTEST
* cell BWBTEST
* pin B
* pin A
.SUBCKT BWBTEST 1 2
.ENDS BWBTEST

75
testdata/lvs/bbdevices2b.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.simplify
compare

372
testdata/lvs/bbdevices2b.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l2 (-401420 456500) (50730 78500))
)
net(4
rect(l2 (822690 427000) (63970 82000))
)
net(5
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-270500 7500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(6
rect(l14 (-126000 -195000) (292000 25000))
)
net(7
rect(l14 (-410240 -216150) (83240 87150))
)
net(8
rect(l14 (846960 -242000) (77190 75500))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0)
pin(0 4)
pin(1 1)
)
circuit(7 DPTEST location(0 0)
pin(0 5)
pin(1 1)
)
circuit(8 FBGATEST location(0 0)
pin(0 2)
pin(1 3)
)
circuit(9 BDPTEST location(0 0)
pin(0 5)
pin(1 6)
)
circuit(10 BWBTEST location(0 0)
pin(0 8)
pin(1 5)
)
circuit(14 BBGATEST location(0 0)
pin(0 7)
pin(1 6)
)
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(DPTEST DPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(testall TESTALL match
xref(
net(3 1 match)
net(2 2 match)
net(1 3 match)
net(5 5 match)
net(6 6 match)
net(7 8 match)
net(4 4 match)
net(8 7 match)
circuit(14 7 match)
circuit(9 5 match)
circuit(10 6 match)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

75
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $10 r0 *1 0,0
X$10 3 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 4 BBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
* net 1 B
* net 2 A
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
* net 1 B
* net 2 A
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
* net 1 A
* net 2 B
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 2
* net 1 B
* net 2 A
* net 3 BBGATEST
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
* net 1 B
* net 2 A
* net 3 FBGATEST
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 2
* net 1 B
* net 2 A
* net 3 FWBTEST
.ENDS FWBTEST
* cell BWBTEST
* pin B
.SUBCKT BWBTEST 1
* net 1 B
* net 2 A
* net 3 BWBTEST
.ENDS BWBTEST

BIN
testdata/lvs/bbdevices3.gds vendored Normal file
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74
testdata/lvs/bbdevices3.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
align
compare

465
testdata/lvs/bbdevices3.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Nets with their geometries
net(1 name(B)
rect(l15 (586500 -242000) (93500 75500))
rect(l15 (-46751 -37751) (2 2))
)
net(2 name(A)
rect(l15 (830000 -249000) (105500 81500))
rect(l15 (-52751 -40751) (2 2))
)
net(3 name(BWBTEST)
rect(l15 (757499 -114001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Nets with their geometries
net(1 name(B)
rect(l3 (793500 427000) (120500 82000))
rect(l3 (-60251 -41001) (2 2))
)
net(2 name(A)
rect(l3 (572500 432500) (74500 73500))
rect(l3 (-37251 -36751) (2 2))
)
net(3 name(FWBTEST)
rect(l3 (797999 565499) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Nets with their geometries
net(1 name(B)
rect(l3 (-221000 412500) (162000 152500))
rect(l3 (-81001 -76251) (2 2))
)
net(2 name(A)
rect(l3 (-449500 422500) (146000 144500))
rect(l3 (-71001 -71251) (2 2))
)
net(3 name(FBGATEST)
rect(l3 (-417001 610499) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Nets with their geometries
net(1 name(B)
rect(l15 (-468000 -280000) (177000 189000))
rect(l15 (-88501 -94501) (2 2))
)
net(2 name(A)
rect(l15 (-218500 -290000) (193000 203000))
rect(l15 (-94001 -101501) (2 2))
)
net(3 name(BBGATEST)
rect(l15 (-422001 -313001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Nets with their geometries
net(1 name(A)
rect(l16 (317000 -232000) (92000 92000))
rect(l16 (-46001 -46001) (2 2))
)
net(2 name(B)
rect(l16 (95500 -231000) (116000 97000))
rect(l16 (-58001 -48501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Nets with their geometries
net(1 name(B)
rect(l11 (323000 151500) (76000 83000))
rect(l11 (-38001 -41501) (2 2))
)
net(2 name(A)
rect(l11 (96500 159500) (90000 73000))
rect(l11 (-45001 -36501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Nets with their geometries
net(1 name(B)
rect(l1 (327000 436500) (72000 93000))
rect(l1 (-36001 -46501) (2 2))
)
net(2 name(A)
rect(l1 (101500 443500) (82000 84000))
rect(l1 (-41001 -42001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-270500 7500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(10 BWBTEST location(0 0) pin(0 3))
circuit(14 BBGATEST location(0 0) pin(0 4))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
net(1 1 match)
net(2 2 match)
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
net(() 1 match)
net(1 2 match)
pin(() 0 match)
pin(0 1 match)
)
)
circuit(DPTEST DPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
net(() 1 match)
net(1 2 match)
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL nomatch
xref(
net(() 7 mismatch)
net(2 2 match)
net(1 3 match)
net(3 5 mismatch)
net(4 6 match)
circuit(14 7 match)
circuit(9 5 match)
circuit(10 6 mismatch)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

57
testdata/lvs/bbdevices3b.cir vendored Normal file
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $10 r0 *1 0,0
X$10 3 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 4 BBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 1
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 1
.ENDS FWBTEST
* cell BWBTEST
* pin B
.SUBCKT BWBTEST 1
.ENDS BWBTEST

75
testdata/lvs/bbdevices3b.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.simplify
compare

329
testdata/lvs/bbdevices3b.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Outgoing pins and their connections to nets
pin(name(B))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Outgoing pins and their connections to nets
pin(name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-270500 7500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(10 BWBTEST location(0 0) pin(0 3))
circuit(14 BBGATEST location(0 0) pin(0 4))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST nomatch
xref(
pin(() 0 mismatch)
pin(0 1 match)
)
)
circuit(DPTEST DPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL skipped description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n B: BWBTEST')
xref(
)
)
)

72
testdata/lvs/bbdevices4.cir vendored Normal file
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $13 r0 *1 0,0
X$13 4 BBGATEST
.ENDS testall
* cell BWBTEST
.SUBCKT BWBTEST
* net 1 B
* net 2 A
* net 3 BWBTEST
.ENDS BWBTEST
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
* net 1 B
* net 2 A
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
* net 1 B
* net 2 A
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
* net 1 A
* net 2 B
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 2
* net 1 B
* net 2 A
* net 3 BBGATEST
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
* net 1 B
* net 2 A
* net 3 FBGATEST
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 2
* net 1 B
* net 2 A
* net 3 FWBTEST
.ENDS FWBTEST

BIN
testdata/lvs/bbdevices4.gds vendored Normal file
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Binary file not shown.

74
testdata/lvs/bbdevices4.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
align
compare

459
testdata/lvs/bbdevices4.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Nets with their geometries
net(1 name(B)
rect(l3 (793500 427000) (120500 82000))
rect(l3 (-60251 -41001) (2 2))
)
net(2 name(A)
rect(l3 (572500 432500) (74500 73500))
rect(l3 (-37251 -36751) (2 2))
)
net(3 name(FWBTEST)
rect(l3 (797999 565499) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Nets with their geometries
net(1 name(B)
rect(l3 (-221000 412500) (162000 152500))
rect(l3 (-81001 -76251) (2 2))
)
net(2 name(A)
rect(l3 (-449500 422500) (146000 144500))
rect(l3 (-71001 -71251) (2 2))
)
net(3 name(FBGATEST)
rect(l3 (-417001 610499) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Nets with their geometries
net(1 name(B)
rect(l15 (-468000 -280000) (177000 189000))
rect(l15 (-88501 -94501) (2 2))
)
net(2 name(A)
rect(l15 (-218500 -290000) (193000 203000))
rect(l15 (-94001 -101501) (2 2))
)
net(3 name(BBGATEST)
rect(l15 (-422001 -313001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Nets with their geometries
net(1 name(A)
rect(l16 (317000 -232000) (92000 92000))
rect(l16 (-46001 -46001) (2 2))
)
net(2 name(B)
rect(l16 (95500 -231000) (116000 97000))
rect(l16 (-58001 -48501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Nets with their geometries
net(1 name(B)
rect(l11 (323000 151500) (76000 83000))
rect(l11 (-38001 -41501) (2 2))
)
net(2 name(A)
rect(l11 (96500 159500) (90000 73000))
rect(l11 (-45001 -36501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Nets with their geometries
net(1 name(B)
rect(l1 (327000 436500) (72000 93000))
rect(l1 (-36001 -46501) (2 2))
)
net(2 name(A)
rect(l1 (101500 443500) (82000 84000))
rect(l1 (-41001 -42001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Nets with their geometries
net(1 name(B)
rect(l15 (832000 -242000) (93500 75500))
rect(l15 (-46751 -37751) (2 2))
)
net(2 name(A)
rect(l15 (576500 -249000) (105500 81500))
rect(l15 (-52751 -40751) (2 2))
)
net(3 name(BWBTEST)
rect(l15 (754499 -114001) (2 2))
)
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-25000 -193000) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(13 BBGATEST location(0 0) pin(0 4))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
net(1 1 match)
net(2 2 match)
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
net(() 1 match)
net(() 2 match)
pin(() 0 match)
pin(() 1 match)
)
)
circuit(DPTEST DPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
net(() 1 match)
net(1 2 match)
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL nomatch
xref(
net(2 2 match)
net(1 3 match)
net(3 5 mismatch)
net(4 6 match)
circuit(() 6 mismatch)
circuit(13 7 match)
circuit(9 5 match)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

54
testdata/lvs/bbdevices4b.cir vendored Normal file
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@ -0,0 +1,54 @@
* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $13 r0 *1 0,0
X$13 4 BBGATEST
.ENDS testall
* cell BWBTEST
.SUBCKT BWBTEST
.ENDS BWBTEST
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 1
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 1
.ENDS FWBTEST

75
testdata/lvs/bbdevices4b.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.simplify
compare

324
testdata/lvs/bbdevices4b.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Outgoing pins and their connections to nets
pin(name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-25000 -193000) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(13 BBGATEST location(0 0) pin(0 4))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST nomatch
xref(
pin(() 0 mismatch)
pin(() 1 match)
)
)
circuit(DPTEST DPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL skipped description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n B: BWBTEST')
xref(
)
)
)

75
testdata/lvs/bbdevices5.cir vendored Normal file
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $13 r0 *1 0,0
X$13 4 BBGATEST
* cell instance $14 r0 *1 0,0
X$14 5 BWBTEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
* net 1 B
* net 2 A
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
* net 1 B
* net 2 A
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
* net 1 A
* net 2 B
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 2
* net 1 B
* net 2 A
* net 3 BBGATEST
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
* net 1 B
* net 2 A
* net 3 FBGATEST
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 2
* net 1 B
* net 2 A
* net 3 FWBTEST
.ENDS FWBTEST
* cell BWBTEST
* pin A
.SUBCKT BWBTEST 2
* net 1 B
* net 2 A
* net 3 BWBTEST
.ENDS BWBTEST

BIN
testdata/lvs/bbdevices5.gds vendored Normal file
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74
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
align
compare

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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Nets with their geometries
net(1 name(B)
rect(l15 (832000 -242000) (93500 75500))
rect(l15 (-46751 -37751) (2 2))
)
net(2 name(A)
rect(l15 (576500 -249000) (105500 81500))
rect(l15 (-52751 -40751) (2 2))
)
net(3 name(BWBTEST)
rect(l15 (754499 -114001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Nets with their geometries
net(1 name(B)
rect(l3 (793500 427000) (120500 82000))
rect(l3 (-60251 -41001) (2 2))
)
net(2 name(A)
rect(l3 (572500 432500) (74500 73500))
rect(l3 (-37251 -36751) (2 2))
)
net(3 name(FWBTEST)
rect(l3 (797999 565499) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Nets with their geometries
net(1 name(B)
rect(l3 (-221000 412500) (162000 152500))
rect(l3 (-81001 -76251) (2 2))
)
net(2 name(A)
rect(l3 (-449500 422500) (146000 144500))
rect(l3 (-71001 -71251) (2 2))
)
net(3 name(FBGATEST)
rect(l3 (-417001 610499) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Nets with their geometries
net(1 name(B)
rect(l15 (-468000 -280000) (177000 189000))
rect(l15 (-88501 -94501) (2 2))
)
net(2 name(A)
rect(l15 (-218500 -290000) (193000 203000))
rect(l15 (-94001 -101501) (2 2))
)
net(3 name(BBGATEST)
rect(l15 (-422001 -313001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Nets with their geometries
net(1 name(A)
rect(l16 (317000 -232000) (92000 92000))
rect(l16 (-46001 -46001) (2 2))
)
net(2 name(B)
rect(l16 (95500 -231000) (116000 97000))
rect(l16 (-58001 -48501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Nets with their geometries
net(1 name(B)
rect(l11 (323000 151500) (76000 83000))
rect(l11 (-38001 -41501) (2 2))
)
net(2 name(A)
rect(l11 (96500 159500) (90000 73000))
rect(l11 (-45001 -36501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Nets with their geometries
net(1 name(B)
rect(l1 (327000 436500) (72000 93000))
rect(l1 (-36001 -46501) (2 2))
)
net(2 name(A)
rect(l1 (101500 443500) (82000 84000))
rect(l1 (-41001 -42001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-25000 -193000) (25000 193000))
rect(l14 (-24000 -225500) (118960 25000))
rect(l14 (-182460 113000) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
net(5
rect(l14 (509690 -219000) (113310 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(13 BBGATEST location(0 0) pin(0 4))
circuit(14 BWBTEST location(0 0) pin(0 5))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
net(1 1 match)
net(2 2 match)
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(DPTEST DPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
net(() 1 match)
net(1 2 match)
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL nomatch
xref(
net(5 () mismatch)
net(2 2 match)
net(1 3 match)
net(3 5 mismatch)
net(4 6 match)
circuit(() 6 mismatch)
circuit(13 7 match)
circuit(9 5 match)
circuit(14 () mismatch)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

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testdata/lvs/bbdevices5b.cir vendored Normal file
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 2 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 3 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 FBGATEST
* cell instance $9 r0 *1 0,0
X$9 3 4 BDPTEST
* cell instance $13 r0 *1 0,0
X$13 4 BBGATEST
* cell instance $14 r0 *1 0,0
X$14 5 BWBTEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 1
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 1
.ENDS FWBTEST
* cell BWBTEST
* pin A
.SUBCKT BWBTEST 1
.ENDS BWBTEST

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testdata/lvs/bbdevices5b.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.simplify
compare

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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Outgoing pins and their connections to nets
pin(name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l2 (-148000 463000) (300000 25000))
)
net(3
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-25000 -193000) (25000 193000))
rect(l14 (-24000 -225500) (118960 25000))
rect(l14 (-182460 113000) (150000 150000))
)
net(4
rect(l14 (-126000 -195000) (292000 25000))
)
net(5
rect(l14 (509690 -219000) (113310 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 2)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 3)
pin(1 1)
)
circuit(8 FBGATEST location(0 0) pin(0 2))
circuit(9 BDPTEST location(0 0)
pin(0 3)
pin(1 4)
)
circuit(13 BBGATEST location(0 0) pin(0 4))
circuit(14 BWBTEST location(0 0) pin(0 5))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(DPTEST DPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL nomatch
xref(
net(5 () mismatch)
net(2 2 match)
net(1 3 match)
net(3 5 mismatch)
net(4 6 match)
circuit(() 6 mismatch)
circuit(13 7 match)
circuit(9 5 match)
circuit(14 () mismatch)
circuit(7 4 match)
circuit(8 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

75
testdata/lvs/bbdevices6.cir vendored Normal file
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 3 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 2 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 2 BDPTEST
* cell instance $9 r0 *1 0,0
X$9 2 BBGATEST
* cell instance $10 r0 *1 0,0
X$10 2 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 3 FBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
* net 1 B
* net 2 A
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
* net 1 B
* net 2 A
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
* net 1 A
* net 2 B
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 2
* net 1 B
* net 2 A
* net 3 BBGATEST
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
* net 1 B
* net 2 A
* net 3 FBGATEST
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 2
* net 1 B
* net 2 A
* net 3 FWBTEST
.ENDS FWBTEST
* cell BWBTEST
* pin A
.SUBCKT BWBTEST 2
* net 1 B
* net 2 A
* net 3 BWBTEST
.ENDS BWBTEST

BIN
testdata/lvs/bbdevices6.gds vendored Normal file
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74
testdata/lvs/bbdevices6.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
align
compare

463
testdata/lvs/bbdevices6.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Nets with their geometries
net(1 name(B)
rect(l15 (832000 -242000) (93500 75500))
rect(l15 (-46751 -37751) (2 2))
)
net(2 name(A)
rect(l15 (576500 -249000) (105500 81500))
rect(l15 (-52751 -40751) (2 2))
)
net(3 name(BWBTEST)
rect(l15 (754499 -114001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Nets with their geometries
net(1 name(B)
rect(l3 (793500 427000) (120500 82000))
rect(l3 (-60251 -41001) (2 2))
)
net(2 name(A)
rect(l3 (572500 432500) (74500 73500))
rect(l3 (-37251 -36751) (2 2))
)
net(3 name(FWBTEST)
rect(l3 (797999 565499) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Nets with their geometries
net(1 name(B)
rect(l3 (-221000 412500) (162000 152500))
rect(l3 (-81001 -76251) (2 2))
)
net(2 name(A)
rect(l3 (-449500 422500) (146000 144500))
rect(l3 (-71001 -71251) (2 2))
)
net(3 name(FBGATEST)
rect(l3 (-417001 610499) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Nets with their geometries
net(1 name(B)
rect(l15 (-468000 -280000) (177000 189000))
rect(l15 (-88501 -94501) (2 2))
)
net(2 name(A)
rect(l15 (-218500 -290000) (193000 203000))
rect(l15 (-94001 -101501) (2 2))
)
net(3 name(BBGATEST)
rect(l15 (-422001 -313001) (2 2))
)
# Outgoing pins and their connections to nets
pin(2 name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Nets with their geometries
net(1 name(A)
rect(l16 (317000 -232000) (92000 92000))
rect(l16 (-46001 -46001) (2 2))
)
net(2 name(B)
rect(l16 (95500 -231000) (116000 97000))
rect(l16 (-58001 -48501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Nets with their geometries
net(1 name(B)
rect(l11 (323000 151500) (76000 83000))
rect(l11 (-38001 -41501) (2 2))
)
net(2 name(A)
rect(l11 (96500 159500) (90000 73000))
rect(l11 (-45001 -36501) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Nets with their geometries
net(1 name(B)
rect(l1 (327000 436500) (72000 93000))
rect(l1 (-36001 -46501) (2 2))
)
net(2 name(A)
rect(l1 (101500 443500) (82000 84000))
rect(l1 (-41001 -42001) (2 2))
)
# Outgoing pins and their connections to nets
pin(1 name(B))
pin(2 name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-457140 -10680) (187640 34680))
rect(l14 (-479500 -25000) (292000 25000))
rect(l14 (186500 -16500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(3
rect(l2 (-148000 463000) (300000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 3)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 2)
pin(1 1)
)
circuit(8 BDPTEST location(0 0)
pin(0 2)
pin(1 2)
)
circuit(9 BBGATEST location(0 0) pin(0 2))
circuit(10 BWBTEST location(0 0) pin(0 2))
circuit(14 FBGATEST location(0 0) pin(0 3))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(FDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(DPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BDPTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BWBTEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(BBGATEST
# Nets
net(1 name(A))
net(2 name(B))
# Outgoing pins and their connections to nets
pin(1 name(A))
pin(2 name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
net(1 1 match)
net(2 2 match)
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(DPTEST DPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
net(() 1 match)
net(1 2 match)
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
net(2 1 match)
net(1 2 match)
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
net(() 2 match)
net(2 1 match)
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL nomatch
xref(
net(() 6 mismatch)
net(3 2 match)
net(1 3 match)
net(2 5 mismatch)
circuit(9 7 mismatch)
circuit(8 5 mismatch)
circuit(10 6 match)
circuit(7 4 match)
circuit(14 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)

57
testdata/lvs/bbdevices6b.cir vendored Normal file
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* Extracted by KLayout
* cell testall
.SUBCKT testall
* cell instance $2 r0 *1 0,0
X$2 1 3 FDPTEST
* cell instance $3 r0 *1 0,0
X$3 1 FWBTEST
* cell instance $7 r0 *1 0,0
X$7 2 1 DPTEST
* cell instance $8 r0 *1 0,0
X$8 2 2 BDPTEST
* cell instance $9 r0 *1 0,0
X$9 2 BBGATEST
* cell instance $10 r0 *1 0,0
X$10 2 BWBTEST
* cell instance $14 r0 *1 0,0
X$14 3 FBGATEST
.ENDS testall
* cell FDPTEST
* pin B
* pin A
.SUBCKT FDPTEST 1 2
.ENDS FDPTEST
* cell DPTEST
* pin B
* pin A
.SUBCKT DPTEST 1 2
.ENDS DPTEST
* cell BDPTEST
* pin A
* pin B
.SUBCKT BDPTEST 1 2
.ENDS BDPTEST
* cell BBGATEST
* pin A
.SUBCKT BBGATEST 1
.ENDS BBGATEST
* cell FBGATEST
* pin B
.SUBCKT FBGATEST 1
.ENDS FBGATEST
* cell FWBTEST
* pin A
.SUBCKT FWBTEST 1
.ENDS FWBTEST
* cell BWBTEST
* pin A
.SUBCKT BWBTEST 1
.ENDS BWBTEST

75
testdata/lvs/bbdevices6b.lvs vendored Normal file
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source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("bbdevices.net")
deep
class Layers
attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
end
layer = Layers.new
layer.package = input(20,0)
layer.fdp = input(70,0)
layer.fdpPad = input(73,0)
layer.fsm = input(45,0)
layer.ftp = input(44,0)
layer.fm7 = input(43,0)
layer.fv7 = input(42,0)
layer.fm6 = input(41,0)
layer.fv6 = input(40,0)
layer.fm5 = input(39,0)
layer.fv5 = input(38,0)
layer.fm4 = input(37,0)
layer.fv4 = input(36,0)
layer.fm3 = input(35,0)
layer.fv3 = input(34,0)
layer.fm2 = input(33,0)
layer.fv2 = input(32,0)
layer.fm1 = input(31,0)
layer.fv1 = input(30,0)
layer.dpPad = input(75,0)
layer.dp = input(21,0)
layer.tsv = input(19,0)
layer.bv1 = input(50,0)
layer.bm1 = input(51,0)
layer.bv2 = input(52,0)
layer.bm2 = input(53,0)
layer.bv3 = input(54,0)
layer.bm3 = input(55,0)
layer.bv4 = input(56,0)
layer.bm4 = input(57,0)
layer.bv5 = input(58,0)
layer.bm5 = input(59,0)
layer.bv6 = input(60,0)
layer.bm6 = input(61,0)
layer.bv7 = input(62,0)
layer.bm7 = input(63,0)
layer.btp = input(64,0)
layer.bsm = input(65,0)
layer.bdpPad = input(78,0)
layer.bdp = input(71,0)
layer.text = input(230,0)
connect(layer.fdpPad, layer.fm4)
connect(layer.ftp, layer.fm4)
connect(layer.fm4, layer.fv4)
connect(layer.fv4, layer.fm3)
connect(layer.fm3, layer.fv3)
connect(layer.fv3, layer.fm2)
connect(layer.fm2, layer.fv2)
connect(layer.fv2, layer.fm1)
connect(layer.fm1, layer.fv1)
connect(layer.dpPad, layer.fv1)
connect(layer.fv1, layer.tsv)
connect(layer.tsv, layer.bv1)
connect(layer.bv1, layer.bm1)
connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.simplify
compare

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testdata/lvs/bbdevices6b.lvsdb vendored Normal file
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#%lvsdb-klayout
# Layout
layout(
top(testall)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l1 '73/0')
layer(l3 '44/0')
layer(l2 '37/0')
layer(l4 '36/0')
layer(l5 '35/0')
layer(l6 '34/0')
layer(l7 '33/0')
layer(l8 '32/0')
layer(l9 '31/0')
layer(l10 '30/0')
layer(l11 '75/0')
layer(l12 '19/0')
layer(l13 '50/0')
layer(l14 '51/0')
layer(l15 '64/0')
layer(l16 '78/0')
# Mask layer connectivity
connect(l1 l1 l2)
connect(l3 l3 l2)
connect(l2 l1 l3 l2 l4)
connect(l4 l2 l4 l5)
connect(l5 l4 l5 l6)
connect(l6 l5 l6 l7)
connect(l7 l6 l7 l8)
connect(l8 l7 l8 l9)
connect(l9 l8 l9 l10)
connect(l10 l9 l10 l11 l12)
connect(l11 l10 l11)
connect(l12 l10 l12 l13)
connect(l13 l12 l13 l14)
connect(l14 l13 l14 l15 l16)
connect(l15 l14 l15)
connect(l16 l14 l16)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(BWBTEST
# Circuit boundary
rect((554500 -276000) (403000 162001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FWBTEST
# Circuit boundary
rect((536500 386500) (404000 179001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(FBGATEST
# Circuit boundary
rect((-449500 412500) (390500 198001))
# Outgoing pins and their connections to nets
pin(name(B))
)
circuit(BBGATEST
# Circuit boundary
rect((-468000 -313001) (442500 226001))
# Outgoing pins and their connections to nets
pin(name(A))
)
circuit(BDPTEST
# Circuit boundary
rect((71500 -290000) (371500 194000))
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Circuit boundary
rect((64500 86000) (371500 214500))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(FDPTEST
# Circuit boundary
rect((59500 359500) (375500 241000))
# Outgoing pins and their connections to nets
pin(name(B))
pin(name(A))
)
circuit(testall
# Circuit boundary
rect((-577500 -1123000) (1868000 1796000))
# Nets with their geometries
net(1
rect(l2 (345500 455000) (256500 25000))
rect(l2 (-256500 -146000) (25000 146000))
rect(l2 (-47000 -183500) (75000 75000))
rect(l4 (-50000 -50000) (25000 25000))
rect(l5 (-134000 -25000) (134000 25000))
rect(l5 (-50000 -50000) (75000 75000))
rect(l5 (-184000 -78500) (75000 75000))
rect(l6 (-50000 -50000) (25000 25000))
rect(l7 (-133500 -21500) (134500 25000))
rect(l7 (-51000 -53500) (75000 75000))
rect(l7 (-183500 -73000) (75000 75000))
rect(l8 (-50000 -50000) (25000 25000))
rect(l9 (-25000 -152000) (25000 152000))
rect(l9 (-50000 -50000) (75000 75000))
rect(l9 (-80500 -217500) (90000 90000))
rect(l10 (-57500 -57500) (25000 25000))
rect(l11 (-25000 -25000) (25000 25000))
)
net(2
rect(l9 (348500 26500) (25000 179000))
rect(l9 (-57500 -58000) (90000 90000))
rect(l9 (-86000 -288500) (90000 90000))
rect(l10 (-61500 141000) (25000 25000))
rect(l10 (-21000 -223500) (25000 25000))
rect(l11 (-29000 173500) (25000 25000))
rect(l12 (-58500 -261000) (100000 100000))
rect(l12 (-100000 -100000) (100000 100000))
rect(l13 (-62500 -62500) (25000 25000))
rect(l14 (-24000 -225500) (269500 25000))
rect(l14 (-457140 -10680) (187640 34680))
rect(l14 (-479500 -25000) (292000 25000))
rect(l14 (186500 -16500) (25000 193000))
rect(l14 (-87500 -87500) (150000 150000))
)
net(3
rect(l2 (-148000 463000) (300000 25000))
)
# Subcircuits and their connections
circuit(2 FDPTEST location(0 0)
pin(0 1)
pin(1 3)
)
circuit(3 FWBTEST location(0 0) pin(0 1))
circuit(7 DPTEST location(0 0)
pin(0 2)
pin(1 1)
)
circuit(8 BDPTEST location(0 0)
pin(0 2)
pin(1 2)
)
circuit(9 BBGATEST location(0 0) pin(0 2))
circuit(10 BWBTEST location(0 0) pin(0 2))
circuit(14 FBGATEST location(0 0) pin(0 3))
)
)
# Reference netlist
reference(
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(FBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(FDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(DPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BDPTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BWBTEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(BBGATEST
# Outgoing pins and their connections to nets
pin(name(A))
pin(name(B))
)
circuit(TESTALL
# Nets
net(1 name(A1))
net(2 name(B1))
net(3 name(C1))
net(4 name(G1))
net(5 name(D1))
net(6 name(E1))
net(7 name(H1))
net(8 name(F1))
# Subcircuits and their connections
circuit(1 FBGATEST name(UFBGA)
pin(0 1)
pin(1 2)
)
circuit(2 FWBTEST name(UFWB)
pin(0 3)
pin(1 4)
)
circuit(3 FDPTEST name(UFDP)
pin(0 2)
pin(1 3)
)
circuit(4 DPTEST name(UDP)
pin(0 3)
pin(1 5)
)
circuit(5 BDPTEST name(UBDP)
pin(0 5)
pin(1 6)
)
circuit(6 BWBTEST name(UBWB)
pin(0 5)
pin(1 7)
)
circuit(7 BBGATEST name(UBBGA)
pin(0 6)
pin(1 8)
)
)
)
# Cross reference
xref(
circuit(BBGATEST BBGATEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(BDPTEST BDPTEST match
xref(
pin(0 0 match)
pin(1 1 match)
)
)
circuit(BWBTEST BWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(DPTEST DPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FBGATEST FBGATEST match
xref(
pin(() 0 match)
pin(0 1 match)
)
)
circuit(FDPTEST FDPTEST match
xref(
pin(1 0 match)
pin(0 1 match)
)
)
circuit(FWBTEST FWBTEST match
xref(
pin(() 1 match)
pin(0 0 match)
)
)
circuit(testall TESTALL nomatch
xref(
net(() 6 mismatch)
net(3 2 match)
net(1 3 match)
net(2 5 mismatch)
circuit(9 7 mismatch)
circuit(8 5 mismatch)
circuit(10 6 match)
circuit(7 4 match)
circuit(14 1 match)
circuit(2 3 match)
circuit(3 2 match)
)
)
)