Bug fixes and tests for fill DRC feature.

This commit is contained in:
Matthias Koefferlein 2021-03-29 15:00:31 +02:00
parent d862970d47
commit 1608fa7d0e
4 changed files with 53 additions and 22 deletions

View File

@ -2100,6 +2100,31 @@ CODE
def _ty
@ty
end
def _output_layout
if @output_layout
output = @output_layout
else
output = @def_layout
output || raise("No output layout specified")
end
output
end
def _output_cell
if @output_layout
if @output_cell
output_cell = @output_cell
elsif @def_cell
output_cell = @output_layout.cell(@def_cell.name) || @output_layout.create_cell(@def_cell.name)
end
output_cell || raise("No output cell specified (see 'target' instruction)")
else
output_cell = @output_cell || @def_cell
output_cell || raise("No output cell specified")
end
output_cell
end
def _start
@ -2399,6 +2424,13 @@ CODE
v
end
def _use_output_layer(li)
if !@used_output_layers[li]
@output_layers.push(li)
@used_output_layers[li] = true
end
end
private
def _make_string(v)
@ -2489,20 +2521,8 @@ CODE
else
if @output_layout
output = @output_layout
if @output_cell
output_cell = @output_cell
elsif @def_cell
output_cell = @output_layout.cell(@def_cell.name) || @output_layout.create_cell(@def_cell.name)
end
output_cell || raise("No output cell specified (see 'target' instruction)")
else
output = @def_layout
output || raise("No output layout specified")
output_cell = @output_cell || @def_cell
output_cell || raise("No output cell specified")
end
output = self._output_layout
output_cell = self._output_cell
info = nil
if args.size == 1
@ -2563,7 +2583,7 @@ CODE
end
end
def make_source(layout, cell = nil, path = nil)
name = "layout" + @lnum.to_s
@lnum += 1

View File

@ -4021,8 +4021,8 @@ CODE
dbu_trans = RBA::VCplxTrans::new(1.0 / @engine.dbu)
fill_cell = pattern.create_cell(source.layout)
top_cell = source.cell_obj
fill_cell = pattern.create_cell(@engine._output_layout, @engine)
top_cell = @engine._output_cell
ko = dbu_trans * pattern.cell_origin
rs = dbu_trans * row_step
cs = dbu_trans * column_step
@ -4033,6 +4033,7 @@ CODE
tp = RBA::TilingProcessor::new
tp.dbu = @engine.dbu
tp.frame = RBA::CplxTrans::new(@engine.dbu) * self.data.bbox
tp.scale_to_dbu = false
tp.tile_size(@engine._tx, @engine._ty)
bx = [ @engine._bx || 0.0, row_step.x ].max
@ -4049,8 +4050,8 @@ CODE
tp.var("fc_index", fc_index)
tp.queue(<<"END")
var tc_box = top_cell.bbox;
var tile_box = _tile ? (tc_box & _tile.bbox) : top_cell.bbox;
var tc_box = _frame.bbox;
var tile_box = _tile ? (tc_box & _tile.bbox) : tc_box;
!tile_box.empty && (
tile_box.right = tile_box.right + rs.x - 1;
tile_box.top = tile_box.top + cs.y - 1;
@ -4060,12 +4061,12 @@ var tile_box = _tile ? (tc_box & _tile.bbox) : top_cell.bbox;
END
begin
source.layout.start_changes
@engine._output_layout.start_changes
@engine.run_timed("\"#{m}\" in: #{@engine.src_line}", self.data) do
tp.execute("Tiled \"#{m}\" in: #{@engine.src_line}")
end
ensure
source.layout.end_changes
@engine._output_layout.end_changes
end
else

View File

@ -190,10 +190,11 @@ module DRC
@origin = RBA::DVector::new
end
def create_cell(layout)
def create_cell(layout, engine)
cell = layout.create_cell(@cell_name)
@shapes.each do |s|
li = layout.layer(s[0])
engine._use_output_layer(li)
s[1].each { |t| cell.shapes(li).insert(t) }
end
cell

View File

@ -1163,3 +1163,12 @@ TEST(29d_holes)
run_test (_this, "29", true);
}
TEST(30_fill)
{
run_test (_this, "30", false);
}
TEST(31_fillTiled)
{
run_test (_this, "31", false);
}