mirror of https://github.com/KLayout/klayout.git
Bug fixes and tests for fill DRC feature.
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d862970d47
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@ -2100,6 +2100,31 @@ CODE
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def _ty
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@ty
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end
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def _output_layout
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if @output_layout
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output = @output_layout
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else
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output = @def_layout
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output || raise("No output layout specified")
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end
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output
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end
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def _output_cell
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if @output_layout
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if @output_cell
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output_cell = @output_cell
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elsif @def_cell
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output_cell = @output_layout.cell(@def_cell.name) || @output_layout.create_cell(@def_cell.name)
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end
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output_cell || raise("No output cell specified (see 'target' instruction)")
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else
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output_cell = @output_cell || @def_cell
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output_cell || raise("No output cell specified")
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end
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output_cell
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end
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def _start
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@ -2399,6 +2424,13 @@ CODE
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v
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end
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def _use_output_layer(li)
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if !@used_output_layers[li]
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@output_layers.push(li)
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@used_output_layers[li] = true
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end
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end
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private
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def _make_string(v)
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@ -2489,20 +2521,8 @@ CODE
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else
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if @output_layout
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output = @output_layout
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if @output_cell
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output_cell = @output_cell
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elsif @def_cell
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output_cell = @output_layout.cell(@def_cell.name) || @output_layout.create_cell(@def_cell.name)
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end
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output_cell || raise("No output cell specified (see 'target' instruction)")
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else
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output = @def_layout
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output || raise("No output layout specified")
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output_cell = @output_cell || @def_cell
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output_cell || raise("No output cell specified")
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end
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output = self._output_layout
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output_cell = self._output_cell
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info = nil
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if args.size == 1
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@ -2563,7 +2583,7 @@ CODE
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end
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end
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def make_source(layout, cell = nil, path = nil)
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name = "layout" + @lnum.to_s
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@lnum += 1
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@ -4021,8 +4021,8 @@ CODE
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dbu_trans = RBA::VCplxTrans::new(1.0 / @engine.dbu)
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fill_cell = pattern.create_cell(source.layout)
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top_cell = source.cell_obj
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fill_cell = pattern.create_cell(@engine._output_layout, @engine)
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top_cell = @engine._output_cell
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ko = dbu_trans * pattern.cell_origin
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rs = dbu_trans * row_step
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cs = dbu_trans * column_step
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@ -4033,6 +4033,7 @@ CODE
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tp = RBA::TilingProcessor::new
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tp.dbu = @engine.dbu
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tp.frame = RBA::CplxTrans::new(@engine.dbu) * self.data.bbox
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tp.scale_to_dbu = false
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tp.tile_size(@engine._tx, @engine._ty)
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bx = [ @engine._bx || 0.0, row_step.x ].max
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@ -4049,8 +4050,8 @@ CODE
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tp.var("fc_index", fc_index)
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tp.queue(<<"END")
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var tc_box = top_cell.bbox;
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var tile_box = _tile ? (tc_box & _tile.bbox) : top_cell.bbox;
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var tc_box = _frame.bbox;
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var tile_box = _tile ? (tc_box & _tile.bbox) : tc_box;
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!tile_box.empty && (
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tile_box.right = tile_box.right + rs.x - 1;
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tile_box.top = tile_box.top + cs.y - 1;
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@ -4060,12 +4061,12 @@ var tile_box = _tile ? (tc_box & _tile.bbox) : top_cell.bbox;
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END
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begin
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source.layout.start_changes
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@engine._output_layout.start_changes
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@engine.run_timed("\"#{m}\" in: #{@engine.src_line}", self.data) do
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tp.execute("Tiled \"#{m}\" in: #{@engine.src_line}")
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end
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ensure
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source.layout.end_changes
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@engine._output_layout.end_changes
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end
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else
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@ -190,10 +190,11 @@ module DRC
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@origin = RBA::DVector::new
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end
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def create_cell(layout)
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def create_cell(layout, engine)
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cell = layout.create_cell(@cell_name)
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@shapes.each do |s|
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li = layout.layer(s[0])
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engine._use_output_layer(li)
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s[1].each { |t| cell.shapes(li).insert(t) }
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end
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cell
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@ -1163,3 +1163,12 @@ TEST(29d_holes)
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run_test (_this, "29", true);
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}
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TEST(30_fill)
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{
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run_test (_this, "30", false);
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}
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TEST(31_fillTiled)
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{
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run_test (_this, "31", false);
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}
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