luke
/
klayout
mirror of https://github.com/KLayout/klayout.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Updated test data for windows.

This commit is contained in:
Matthias Koefferlein 2019-12-15 10:17:10 +01:00
parent a05345945d
commit 06a68b77d2
16 changed files with 14520 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

646
testdata/algo/lvs_test1_au.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,646 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(bulk '1/0')
layer(nwell '1/0')
layer(poly '3/0')
layer(poly_lbl '3/1')
layer(diff_cont '4/0')
layer(poly_cont '5/0')
layer(metal1 '6/0')
layer(metal1_lbl '6/1')
layer(via1 '7/0')
layer(metal2 '8/0')
layer(metal2_lbl '8/1')
layer(ntie)
layer(psd)
layer(ptie)
layer(nsd)
# Mask layer connectivity
connect(nwell nwell ntie)
connect(poly poly poly_lbl poly_cont)
connect(poly_lbl poly)
connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
connect(poly_cont poly poly_cont metal1)
connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
connect(metal1_lbl metal1)
connect(via1 metal1 via1 metal2)
connect(metal2 via1 metal2 metal2_lbl)
connect(metal2_lbl metal2)
connect(ntie nwell diff_cont ntie)
connect(psd diff_cont psd)
connect(ptie diff_cont ptie)
connect(nsd diff_cont nsd)
# Global nets and connectivity
global(bulk BULK)
global(ptie BULK)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(psd (-650 -875) (525 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(psd (125 -875) (550 1750))
)
terminal(B
rect(nwell (-125 -875) (250 1750))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(psd (-675 -875) (550 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(psd (125 -875) (525 1750))
)
terminal(B
rect(nwell (-125 -875) (250 1750))
)
)
device(D$NMOS NMOS
terminal(S
rect(nsd (-650 -875) (525 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(nsd (125 -875) (550 1750))
)
terminal(B
rect(bulk (-125 -875) (250 1750))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(nsd (-675 -875) (550 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(nsd (125 -875) (525 1750))
)
terminal(B
rect(bulk (-125 -875) (250 1750))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INV2
# Circuit boundary
rect((-1700 -2440) (3100 7820))
# Nets with their geometries
net(1
rect(nwell (-1400 1800) (2800 3580))
rect(diff_cont (-1510 -650) (220 220))
rect(ntie (-510 -450) (800 680))
)
net(2 name(IN)
rect(poly (-525 -250) (250 2500))
rect(poly (-1425 -630) (2100 360))
rect(poly (-125 -2230) (250 2500))
rect(poly (-1050 -3850) (250 2400))
rect(poly (550 1200) (250 2400))
rect(poly (-250 -6000) (250 2400))
rect(poly (-1050 1200) (250 2400))
rect(poly_lbl (-526 -2601) (2 2))
rect(poly_cont (-831 -111) (220 220))
)
net(3 name(OUT)
rect(diff_cont (-910 90) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (1380 3380) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 -3820) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-1820 3380) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(metal1 (1310 -3710) (360 2220))
rect(metal1 (-1900 -800) (2220 360))
rect(metal1 (-2280 -2400) (360 2840))
rect(metal1 (-360 -3600) (360 1560))
rect(metal1 (1240 2040) (360 1560))
rect(metal1 (-360 -5160) (360 1560))
rect(metal1 (-1960 2040) (360 1560))
rect(metal1_lbl (1419 -2181) (2 2))
rect(psd (-1851 524) (525 1750))
rect(psd (1050 -1750) (525 1750))
rect(nsd (-2100 -5350) (525 1750))
rect(nsd (1050 -1750) (525 1750))
)
net(4 name(VSS)
rect(diff_cont (-110 90) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 980) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(metal1 (-290 -290) (360 1560))
rect(metal1 (-360 -1560) (360 1560))
rect(via1 (-305 -705) (250 250))
rect(via1 (-250 150) (250 250))
rect(via1 (-250 -1450) (250 250))
rect(via1 (-250 150) (250 250))
rect(metal2 (-1525 -775) (2800 1700))
rect(metal2_lbl (-161 -541) (2 2))
rect(nsd (-1516 -1186) (550 1750))
)
net(5 name(VDD)
rect(diff_cont (-110 2490) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 -1420) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(metal1 (-290 -1490) (360 1560))
rect(metal1 (-360 -1560) (360 1560))
rect(via1 (-305 -1505) (250 250))
rect(via1 (-250 150) (250 250))
rect(via1 (-250 150) (250 250))
rect(via1 (-250 150) (250 250))
rect(metal2 (-1525 -1575) (2800 1700))
rect(metal2_lbl (-151 -1251) (2 2))
rect(psd (-1526 -476) (550 1750))
)
net(6 name(BULK)
rect(diff_cont (-110 -2160) (220 220))
rect(ptie (-510 -450) (800 680))
)
# Outgoing pins and their connections to nets
pin(1)
pin(2 name(IN))
pin(3 name(OUT))
pin(4 name(VSS))
pin(5 name(VDD))
pin(6 name(BULK))
# Devices and their connections
device(1 D$PMOS
device(D$PMOS$1 location(800 0))
connect(0 S S)
connect(1 S D)
connect(0 G G)
connect(1 G G)
connect(0 D D)
connect(1 D S)
connect(0 B B)
connect(1 B B)
location(-400 3200)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 5)
terminal(B 1)
)
device(3 D$NMOS
device(D$NMOS$1 location(800 0))
connect(0 S S)
connect(1 S D)
connect(0 G G)
connect(1 G G)
connect(0 D D)
connect(1 D S)
connect(0 B B)
connect(1 B B)
location(-400 -400)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 4)
terminal(B 6)
)
)
circuit(INV2PAIR
# Circuit boundary
rect((0 -1640) (5740 7820))
# Nets with their geometries
net(1 name(BULK))
net(2)
net(3)
net(4)
net(5)
net(6)
net(7)
# Outgoing pins and their connections to nets
pin(1 name(BULK))
pin(2)
pin(3)
pin(4)
pin(5)
pin(6)
pin(7)
# Subcircuits and their connections
circuit(1 INV2 location(1700 800)
pin(0 7)
pin(1 5)
pin(2 4)
pin(3 3)
pin(4 2)
pin(5 1)
)
circuit(2 INV2 location(4340 800)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
# Circuit boundary
rect((-1720 -2440) (26880 7820))
# Nets with their geometries
net(1 name(FB)
rect(metal1 (-1700 1620) (360 360))
rect(via1 (-305 -305) (250 250))
rect(via1 (23190 -250) (250 250))
rect(metal2 (-23765 -325) (23840 400))
rect(metal2_lbl (-22121 -201) (2 2))
)
net(2 name(OSC)
rect(via1 (24435 1675) (250 250))
rect(metal2 (-325 -325) (400 400))
rect(metal2_lbl (-201 -201) (2 2))
)
net(3 name(VDD)
rect(metal1 (-180 3900) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal2_lbl (-23941 -2221) (2 2))
)
net(4 name(VSS)
rect(metal1 (-180 -2220) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal2_lbl (-23941 1099) (2 2))
)
net(5)
net(6)
net(7)
net(8)
net(9)
net(10)
net(11)
net(12)
# Outgoing pins and their connections to nets
pin(1 name(FB))
pin(2 name(OSC))
pin(3 name(VDD))
pin(4 name(VSS))
# Subcircuits and their connections
circuit(1 INV2PAIR location(19420 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 1)
pin(4 10)
pin(5 2)
pin(6 3)
)
circuit(2 INV2PAIR location(-1700 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 8)
pin(4 1)
pin(5 9)
pin(6 3)
)
circuit(3 INV2PAIR location(3580 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 7)
pin(4 9)
pin(5 12)
pin(6 3)
)
circuit(4 INV2PAIR location(8860 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 6)
pin(4 12)
pin(5 11)
pin(6 3)
)
circuit(5 INV2PAIR location(14140 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 5)
pin(4 11)
pin(5 10)
pin(6 3)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INV2
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 5)
terminal(B 1)
)
device(2 NMOS
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 4)
terminal(B 6)
)
)
circuit(INV2PAIR
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($1)
pin(0 7)
pin(1 5)
pin(2 4)
pin(3 3)
pin(4 2)
pin(5 1)
)
circuit(2 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('6'))
net(6 name('100'))
net(7 name('5'))
net(8 name('101'))
net(9 name('8'))
net(10 name('102'))
net(11 name('7'))
net(12 name('103'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
# Subcircuits and their connections
circuit(1 INV2PAIR name($1)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 1)
pin(4 5)
pin(5 2)
pin(6 3)
)
circuit(2 INV2PAIR name($2)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 6)
pin(4 1)
pin(5 7)
pin(6 3)
)
circuit(3 INV2PAIR name($3)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 8)
pin(4 7)
pin(5 9)
pin(6 3)
)
circuit(4 INV2PAIR name($4)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 10)
pin(4 9)
pin(5 11)
pin(6 3)
)
circuit(5 INV2PAIR name($5)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 12)
pin(4 11)
pin(5 5)
pin(6 3)
)
)
)
# Cross reference
xref(
circuit(INV2 INV2 match
xref(
net(1 1 match)
net(6 6 match)
net(2 2 match)
net(3 3 match)
net(5 5 match)
net(4 4 match)
pin(0 0 match)
pin(5 5 match)
pin(1 1 match)
pin(2 2 match)
pin(4 4 match)
pin(3 3 match)
device(3 2 match)
device(1 1 match)
)
)
circuit(INV2PAIR INV2PAIR match
xref(
net(2 2 match)
net(3 3 match)
net(4 4 match)
net(5 5 match)
net(6 6 match)
net(7 7 match)
net(1 1 match)
pin(1 1 match)
pin(2 2 match)
pin(3 3 match)
pin(4 4 match)
pin(5 5 match)
pin(6 6 match)
pin(0 0 match)
circuit(1 1 match)
circuit(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(8 6 match)
net(7 8 match)
net(6 10 match)
net(5 12 match)
net(9 7 match)
net(10 5 match)
net(11 11 match)
net(12 9 match)
net(1 1 match)
net(2 2 match)
net(3 3 match)
net(4 4 match)
pin(0 0 match)
pin(1 1 match)
pin(2 2 match)
pin(3 3 match)
circuit(1 1 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
)
)
)

682
testdata/algo/lvs_test2_au.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,682 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(bulk '1/0')
layer(nwell '1/0')
layer(poly '3/0')
layer(poly_lbl '3/1')
layer(diff_cont '4/0')
layer(poly_cont '5/0')
layer(metal1 '6/0')
layer(metal1_lbl '6/1')
layer(via1 '7/0')
layer(metal2 '8/0')
layer(metal2_lbl '8/1')
layer(ntie)
layer(psd)
layer(ptie)
layer(nsd)
# Mask layer connectivity
connect(nwell nwell ntie)
connect(poly poly poly_lbl poly_cont)
connect(poly_lbl poly)
connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
connect(poly_cont poly poly_cont metal1)
connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
connect(metal1_lbl metal1)
connect(via1 metal1 via1 metal2)
connect(metal2 via1 metal2 metal2_lbl)
connect(metal2_lbl metal2)
connect(ntie nwell diff_cont ntie)
connect(psd diff_cont psd)
connect(ptie diff_cont ptie)
connect(nsd diff_cont nsd)
# Global nets and connectivity
global(bulk BULK)
global(ptie BULK)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(psd (-650 -875) (525 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(psd (125 -875) (550 1750))
)
terminal(B
rect(nwell (-125 -875) (250 1750))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(psd (-675 -875) (550 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(psd (125 -875) (525 1750))
)
terminal(B
rect(nwell (-125 -875) (250 1750))
)
)
device(D$NMOS NMOS
terminal(S
rect(nsd (-650 -875) (525 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(nsd (125 -875) (550 1750))
)
terminal(B
rect(bulk (-125 -875) (250 1750))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(nsd (-675 -875) (550 1750))
)
terminal(G
rect(poly (-125 -875) (250 1750))
)
terminal(D
rect(nsd (125 -875) (525 1750))
)
terminal(B
rect(bulk (-125 -875) (250 1750))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INV2
# Circuit boundary
rect((-1700 -2440) (3100 7820))
# Nets with their geometries
net(1
rect(nwell (-1400 1800) (2800 3580))
rect(diff_cont (-1510 -650) (220 220))
rect(ntie (-510 -450) (800 680))
)
net(2 name(IN)
rect(poly (-525 -250) (250 2500))
rect(poly (-1425 -630) (2100 360))
rect(poly (-125 -2230) (250 2500))
rect(poly (-1050 -3850) (250 2400))
rect(poly (550 1200) (250 2400))
rect(poly (-250 -6000) (250 2400))
rect(poly (-1050 1200) (250 2400))
rect(poly_lbl (-526 -2601) (2 2))
rect(poly_cont (-831 -111) (220 220))
)
net(3 name(OUT)
rect(diff_cont (-910 90) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (1380 3380) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 -3820) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-1820 3380) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(metal1 (1310 -3710) (360 2220))
rect(metal1 (-1900 -800) (2220 360))
rect(metal1 (-2280 -2400) (360 2840))
rect(metal1 (-360 -3600) (360 1560))
rect(metal1 (1240 2040) (360 1560))
rect(metal1 (-360 -5160) (360 1560))
rect(metal1 (-1960 2040) (360 1560))
rect(metal1_lbl (1419 -2181) (2 2))
rect(psd (-1851 524) (525 1750))
rect(psd (1050 -1750) (525 1750))
rect(nsd (-2100 -5350) (525 1750))
rect(nsd (1050 -1750) (525 1750))
)
net(4 name(VSS)
rect(diff_cont (-110 90) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 980) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(diff_cont (-220 -620) (220 220))
rect(metal1 (-290 -290) (360 1560))
rect(metal1 (-360 -1560) (360 1560))
rect(via1 (-305 -705) (250 250))
rect(via1 (-250 150) (250 250))
rect(via1 (-250 -1450) (250 250))
rect(via1 (-250 150) (250 250))
rect(metal2 (-1525 -775) (2800 1700))
rect(metal2_lbl (-161 -541) (2 2))
rect(nsd (-1516 -1186) (550 1750))
)
net(5 name(VDD)
rect(diff_cont (-110 2490) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 -1420) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(diff_cont (-220 180) (220 220))
rect(metal1 (-290 -1490) (360 1560))
rect(metal1 (-360 -1560) (360 1560))
rect(via1 (-305 -1505) (250 250))
rect(via1 (-250 150) (250 250))
rect(via1 (-250 150) (250 250))
rect(via1 (-250 150) (250 250))
rect(metal2 (-1525 -1575) (2800 1700))
rect(metal2_lbl (-151 -1251) (2 2))
rect(psd (-1526 -476) (550 1750))
)
net(6 name(BULK)
rect(diff_cont (-110 -2160) (220 220))
rect(ptie (-510 -450) (800 680))
)
# Outgoing pins and their connections to nets
pin(1)
pin(2 name(IN))
pin(3 name(OUT))
pin(4 name(VSS))
pin(5 name(VDD))
pin(6 name(BULK))
# Devices and their connections
device(1 D$PMOS
device(D$PMOS$1 location(800 0))
connect(0 S S)
connect(1 S D)
connect(0 G G)
connect(1 G G)
connect(0 D D)
connect(1 D S)
connect(0 B B)
connect(1 B B)
location(-400 3200)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 5)
terminal(B 1)
)
device(3 D$NMOS
device(D$NMOS$1 location(800 0))
connect(0 S S)
connect(1 S D)
connect(0 G G)
connect(1 G G)
connect(0 D D)
connect(1 D S)
connect(0 B B)
connect(1 B B)
location(-400 -400)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 4)
terminal(B 6)
)
)
circuit(INV2PAIR
# Circuit boundary
rect((0 -1640) (5740 7820))
# Nets with their geometries
net(1 name(BULK))
net(2)
net(3)
net(4)
net(5)
net(6)
net(7)
# Outgoing pins and their connections to nets
pin(1 name(BULK))
pin(2)
pin(3)
pin(4)
pin(5)
pin(6)
pin(7)
# Subcircuits and their connections
circuit(1 INV2 location(1700 800)
pin(0 7)
pin(1 5)
pin(2 4)
pin(3 3)
pin(4 2)
pin(5 1)
)
circuit(2 INV2 location(4340 800)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
# Circuit boundary
rect((-1720 -2440) (26880 7820))
# Nets with their geometries
net(1 name(FB)
rect(metal1 (-1700 1620) (360 360))
rect(via1 (-305 -305) (250 250))
rect(via1 (23190 -250) (250 250))
rect(metal2 (-23765 -325) (23840 400))
rect(metal2_lbl (-22121 -201) (2 2))
)
net(2 name(OSC)
rect(via1 (24435 1675) (250 250))
rect(metal2 (-325 -325) (400 400))
rect(metal2_lbl (-201 -201) (2 2))
)
net(3 name(VDD)
rect(metal1 (-180 3900) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal2_lbl (-23941 -2221) (2 2))
)
net(4 name(VSS)
rect(metal1 (-180 -2220) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal1 (2280 -1120) (360 1120))
rect(metal2_lbl (-23941 1099) (2 2))
)
net(5)
net(6)
net(7)
net(8)
net(9)
net(10)
net(11)
net(12)
# Outgoing pins and their connections to nets
pin(1 name(FB))
pin(2 name(OSC))
pin(3 name(VDD))
pin(4 name(VSS))
# Subcircuits and their connections
circuit(1 INV2PAIR location(19420 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 1)
pin(4 10)
pin(5 2)
pin(6 3)
)
circuit(2 INV2PAIR location(-1700 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 8)
pin(4 1)
pin(5 9)
pin(6 3)
)
circuit(3 INV2PAIR location(3580 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 7)
pin(4 9)
pin(5 12)
pin(6 3)
)
circuit(4 INV2PAIR location(8860 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 6)
pin(4 12)
pin(5 11)
pin(6 3)
)
circuit(5 INV2PAIR location(14140 -800)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 5)
pin(4 11)
pin(5 10)
pin(6 3)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INV2
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 5)
terminal(B 1)
)
device(2 NMOS
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(G 2)
terminal(D 4)
terminal(B 6)
)
)
circuit(INV2PAIR
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('6'))
net(6 name('5'))
net(7 name('101'))
net(8 name('8'))
net(9 name('102'))
net(10 name('7'))
net(11 name('103'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
# Subcircuits and their connections
circuit(1 INV2PAIR name($1)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 1)
pin(4 5)
pin(5 2)
pin(6 3)
)
circuit(2 INV2PAIR name($2)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 1)
pin(4 1)
pin(5 6)
pin(6 3)
)
circuit(3 INV2PAIR name($3)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 7)
pin(4 6)
pin(5 8)
pin(6 3)
)
circuit(4 INV2PAIR name($4)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 9)
pin(4 8)
pin(5 10)
pin(6 3)
)
circuit(5 INV2PAIR name($5)
pin(0 4)
pin(1 3)
pin(2 4)
pin(3 11)
pin(4 10)
pin(5 5)
pin(6 3)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(() INV2PAIRX mismatch
xref(
)
)
circuit(INV2 INV2 match
xref(
net(1 1 match)
net(6 6 match)
net(2 2 match)
net(3 3 match)
net(5 5 match)
net(4 4 match)
pin(0 0 match)
pin(5 5 match)
pin(1 1 match)
pin(2 2 match)
pin(4 4 match)
pin(3 3 match)
device(3 2 match)
device(1 1 match)
)
)
circuit(INV2PAIR INV2PAIR nomatch
xref(
net(2 2 mismatch)
net(3 3 mismatch)
net(5 4 match)
net(4 5 mismatch)
net(6 6 match)
net(7 7 mismatch)
net(1 1 mismatch)
pin(1 1 match)
pin(2 2 match)
pin(4 3 match)
pin(3 4 match)
pin(5 5 match)
pin(6 6 match)
pin(0 0 match)
circuit(2 () mismatch)
circuit(1 1 mismatch)
)
)
circuit(RINGO RINGO nomatch
xref(
net(() 7 mismatch)
net(() 9 mismatch)
net(() 11 mismatch)
net(() 6 mismatch)
net(() 8 mismatch)
net(5 () mismatch)
net(6 () mismatch)
net(7 () mismatch)
net(9 () mismatch)
net(11 () mismatch)
net(12 () mismatch)
net(10 1 mismatch)
net(8 10 mismatch)
net(1 5 mismatch)
net(2 2 match)
net(3 3 match)
net(4 4 match)
pin(() 0 match)
pin(0 () match)
pin(1 1 match)
pin(2 2 match)
pin(3 3 match)
circuit(() 2 mismatch)
circuit(() 3 mismatch)
circuit(() 4 mismatch)
circuit(() 5 mismatch)
circuit(2 () mismatch)
circuit(3 () mismatch)
circuit(4 () mismatch)
circuit(5 () mismatch)
circuit(1 1 match)
)
)
)

908
testdata/lvs/ringo_device_subcircuits.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,908 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (610 300))
)
net(2
rect(l11 (5550 2950) (900 300))
)
net(3
rect(l11 (7350 2950) (900 300))
)
net(4
rect(l11 (9150 2950) (900 300))
)
net(5
rect(l11 (10950 2950) (900 300))
)
net(6
rect(l11 (12750 2950) (900 300))
)
net(7
rect(l11 (14550 2950) (900 300))
)
net(8
rect(l11 (16350 2950) (900 300))
)
net(9
rect(l11 (18150 2950) (900 300))
)
net(10
rect(l11 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-24850 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l10 (-24850 -800) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(XPMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 XPMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 XPMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 XPMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

1013
testdata/lvs/ringo_layout_var.lvsdb.2 vendored Normal file
View File

File diff suppressed because it is too large Load Diff

908
testdata/lvs/ringo_simple.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,908 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (610 300))
)
net(2
rect(l11 (5550 2950) (900 300))
)
net(3
rect(l11 (7350 2950) (900 300))
)
net(4
rect(l11 (9150 2950) (900 300))
)
net(5
rect(l11 (10950 2950) (900 300))
)
net(6
rect(l11 (12750 2950) (900 300))
)
net(7
rect(l11 (14550 2950) (900 300))
)
net(8
rect(l11 (16350 2950) (900 300))
)
net(9
rect(l11 (18150 2950) (900 300))
)
net(10
rect(l11 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-24850 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l10 (-24850 -800) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

908
testdata/lvs/ringo_simple_device_scaling.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,908 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.5)
param(W 3)
param(AS 2.55)
param(AD 1.35)
param(PS 7.7)
param(PD 3.9)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.5)
param(W 3)
param(AS 1.35)
param(AD 2.55)
param(PS 3.9)
param(PD 7.7)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.5)
param(W 1.9)
param(AS 1.615)
param(AD 0.855)
param(PS 5.5)
param(PD 2.8)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.5)
param(W 1.9)
param(AS 0.855)
param(AD 1.615)
param(PS 2.8)
param(PD 5.5)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.5)
param(W 3)
param(AS 2.55)
param(AD 2.55)
param(PS 7.7)
param(PD 7.7)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.5)
param(W 1.9)
param(AS 1.615)
param(AD 1.615)
param(PS 5.5)
param(PD 5.5)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (610 300))
)
net(2
rect(l11 (5550 2950) (900 300))
)
net(3
rect(l11 (7350 2950) (900 300))
)
net(4
rect(l11 (9150 2950) (900 300))
)
net(5
rect(l11 (10950 2950) (900 300))
)
net(6
rect(l11 (12750 2950) (900 300))
)
net(7
rect(l11 (14550 2950) (900 300))
)
net(8
rect(l11 (16350 2950) (900 300))
)
net(9
rect(l11 (18150 2950) (900 300))
)
net(10
rect(l11 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-24850 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l10 (-24850 -800) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.5)
param(W 3)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.5)
param(W 3)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.5)
param(W 1.9)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.5)
param(W 1.9)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.5)
param(W 3)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.5)
param(W 1.9)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

912
testdata/lvs/ringo_simple_dmos.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,912 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l4 '1/0')
layer(l5 '5/0')
layer(l10 '8/0')
layer(l13 '9/0')
layer(l14 '10/0')
layer(l15 '11/0')
layer(l9)
layer(l3)
layer(l1)
layer(l11)
layer(l8)
layer(l6)
layer(l12)
# Mask layer connectivity
connect(l4 l4 l11)
connect(l5 l5 l10)
connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
connect(l13 l10 l13 l14)
connect(l14 l13 l14 l15)
connect(l15 l14 l15)
connect(l9 l9)
connect(l3 l10 l3)
connect(l1 l10 l1)
connect(l11 l4 l10 l11)
connect(l8 l10 l8)
connect(l6 l10 l6)
connect(l12 l10 l12)
# Global nets and connectivity
global(l9 SUBSTRATE)
global(l12 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l3 (125 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (-550 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l3 (-575 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l3 (-550 -750) (425 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l8 (125 -475) (450 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (-550 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l8 (-575 -475) (450 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -790) (300 1700))
rect(l13 (-1350 0) (2400 800))
rect(l13 (-1151 -401) (2 2))
rect(l3 (-251 -2151) (425 1500))
rect(l3 (-450 -1500) (425 1500))
)
net(2 name(OUT)
rect(l10 (1810 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-1580 3760) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (1220 920) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l13 (-110 1390) (300 1400))
polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l13 (-141 -501) (2 2))
rect(l13 (-1751 1099) (300 1400))
rect(l13 (1100 -1700) (300 300))
rect(l13 (-300 0) (300 1400))
rect(l1 (-1750 -1450) (425 1500))
rect(l1 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (2400 800))
rect(l13 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l8 (1000 1660) (425 950))
rect(l8 (-450 -950) (425 950))
)
net(5
rect(l4 (-100 4500) (2600 3500))
)
net(6 name(B)
rect(l5 (1425 2860) (250 1940))
rect(l5 (-345 -950) (300 300))
rect(l5 (-205 650) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-285 1050) (180 180))
rect(l13 (-71 -91) (2 2))
rect(l13 (-171 -151) (300 300))
)
net(7 name(A)
rect(l5 (725 2860) (250 1940))
rect(l5 (-325 -1850) (300 300))
rect(l5 (-225 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-265 150) (180 180))
rect(l13 (-91 -91) (2 2))
rect(l13 (-151 -151) (300 300))
)
net(8 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(5)
pin(6 name(B))
pin(7 name(A))
pin(8 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 7)
terminal(D 2)
terminal(B 5)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 5)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 4)
terminal(G 7)
terminal(D 3)
terminal(B 8)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 4)
terminal(G 6)
terminal(D 2)
terminal(B 8)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (410 6260) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -240) (300 1400))
rect(l13 (-650 300) (1800 800))
rect(l13 (-1450 -1100) (300 300))
rect(l13 (299 399) (2 2))
rect(l3 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -4120) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -790) (300 4790))
rect(l13 (-151 -2501) (2 2))
rect(l1 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (1800 800))
rect(l13 (-851 -401) (2 2))
rect(l8 (-651 859) (425 950))
)
net(4
rect(l4 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l5 (725 2860) (250 1940))
rect(l5 (-525 -1850) (300 300))
rect(l5 (-25 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-465 150) (180 180))
rect(l13 (-91 -91) (2 2))
rect(l13 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l13 (4040 2950) (610 300))
)
net(2
rect(l13 (5550 2950) (900 300))
)
net(3
rect(l13 (7350 2950) (900 300))
)
net(4
rect(l13 (9150 2950) (900 300))
)
net(5
rect(l13 (10950 2950) (900 300))
)
net(6
rect(l13 (12750 2950) (900 300))
)
net(7
rect(l13 (14550 2950) (900 300))
)
net(8
rect(l13 (16350 2950) (900 300))
)
net(9
rect(l13 (18150 2950) (900 300))
)
net(10
rect(l13 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l13 (21750 2950) (900 300))
rect(l13 (-19530 590) (320 320))
rect(l13 (17820 -320) (320 320))
rect(l14 (-18400 -260) (200 200))
rect(l14 (17940 -200) (200 200))
rect(l15 (-18040 -300) (17740 400))
rect(l15 (-17921 -201) (2 2))
rect(l15 (-221 -201) (400 400))
rect(l15 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l4 (500 4500) (1400 3500))
rect(l4 (-1900 -3500) (600 3500))
rect(l4 (23300 -3500) (1400 3500))
rect(l4 (-100 -3500) (600 3500))
rect(l10 (-24690 -1240) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l13 (-21741 859) (2 2))
rect(l13 (-2351 -451) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-101 -351) (2 2))
rect(l13 (-1251 -401) (600 800))
rect(l13 (23400 -800) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-101 -351) (2 2))
rect(l13 (549 -401) (600 800))
rect(l11 (-24850 -1500) (500 1500))
rect(l11 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l13 (23440 3840) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-101 -101) (2 2))
rect(l15 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l13 (2440 2940) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-101 -101) (2 2))
rect(l15 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l10 (1110 1610) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-21741 -391) (2 2))
rect(l13 (-1901 -401) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-551 -401) (2 2))
rect(l13 (-1251 -401) (600 800))
rect(l13 (23850 -750) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-551 -401) (2 2))
rect(l13 (549 -401) (600 800))
rect(l12 (-24850 -800) (500 1500))
rect(l12 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 nomatch
xref(
net(4 8 mismatch)
net(5 4 mismatch)
net(7 6 match)
net(6 5 match)
net(2 2 mismatch)
net(8 7 mismatch)
net(1 1 mismatch)
net(3 3 mismatch)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(4 4 match)
device(3 3 mismatch)
device(2 2 match)
device(1 1 mismatch)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

965
testdata/lvs/ringo_simple_dummy_device.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,965 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS$1
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$2
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (27600 7650))
# Nets with their geometries
net(1
rect(l4 (26050 2800) (525 550))
rect(l4 (-525 -300) (300 300))
rect(l4 (-25 -2000) (250 1450))
rect(l8 (-465 310) (180 180))
rect(l11 (-240 -240) (300 300))
)
net(2
rect(l11 (4040 2950) (610 300))
)
net(3
rect(l11 (5550 2950) (900 300))
)
net(4
rect(l11 (7350 2950) (900 300))
)
net(5
rect(l11 (9150 2950) (900 300))
)
net(6
rect(l11 (10950 2950) (900 300))
)
net(7
rect(l11 (12750 2950) (900 300))
)
net(8
rect(l11 (14550 2950) (900 300))
)
net(9
rect(l11 (16350 2950) (900 300))
)
net(10
rect(l11 (18150 2950) (900 300))
)
net(11
rect(l11 (19950 2950) (900 300))
)
net(12 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(13 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l8 (-26490 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l9 (-26650 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(14 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(16 name(VSS)
rect(l8 (26010 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (520 -730) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-25780 -890) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (1260 -40) (300 1360))
rect(l11 (400 -1360) (300 1360))
rect(l11 (-24001 -1711) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l6 (-1025 400) (425 950))
rect(l6 (-1100 -950) (425 950))
rect(l10 (-25375 -2150) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(12 name(FB))
pin(13 name(VDD))
pin(14 name(OUT))
pin(15 name(ENABLE))
pin(16 name(VSS))
# Devices and their connections
device(1 D$NMOS
location(26450 2075)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 16)
terminal(G 1)
terminal(D 16)
terminal(B 16)
)
# Subcircuits and their connections
circuit(3 ND2X1 location(1800 0)
pin(0 13)
pin(1 2)
pin(2 16)
pin(3 13)
pin(4 12)
pin(5 15)
pin(6 16)
)
circuit(4 INVX1 location(4200 0)
pin(0 13)
pin(1 3)
pin(2 16)
pin(3 13)
pin(4 2)
pin(5 16)
)
circuit(5 INVX1 location(6000 0)
pin(0 13)
pin(1 4)
pin(2 16)
pin(3 13)
pin(4 3)
pin(5 16)
)
circuit(6 INVX1 location(7800 0)
pin(0 13)
pin(1 5)
pin(2 16)
pin(3 13)
pin(4 4)
pin(5 16)
)
circuit(7 INVX1 location(9600 0)
pin(0 13)
pin(1 6)
pin(2 16)
pin(3 13)
pin(4 5)
pin(5 16)
)
circuit(8 INVX1 location(11400 0)
pin(0 13)
pin(1 7)
pin(2 16)
pin(3 13)
pin(4 6)
pin(5 16)
)
circuit(9 INVX1 location(13200 0)
pin(0 13)
pin(1 8)
pin(2 16)
pin(3 13)
pin(4 7)
pin(5 16)
)
circuit(10 INVX1 location(15000 0)
pin(0 13)
pin(1 9)
pin(2 16)
pin(3 13)
pin(4 8)
pin(5 16)
)
circuit(11 INVX1 location(16800 0)
pin(0 13)
pin(1 10)
pin(2 16)
pin(3 13)
pin(4 9)
pin(5 16)
)
circuit(12 INVX1 location(18600 0)
pin(0 13)
pin(1 11)
pin(2 16)
pin(3 13)
pin(4 10)
pin(5 16)
)
circuit(13 INVX1 location(20400 0)
pin(0 13)
pin(1 12)
pin(2 16)
pin(3 13)
pin(4 11)
pin(5 16)
)
circuit(14 INVX1 location(22200 0)
pin(0 13)
pin(1 14)
pin(2 16)
pin(3 13)
pin(4 12)
pin(5 16)
)
)
)
# Reference netlist
reference(
# Device class section
class(NMOS MOS4)
class(PMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
net(16 name(DUMMY))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Devices and their connections
device(1 NMOS
name($1)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 16)
terminal(D 1)
terminal(B 1)
)
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(2 6 match)
net(11 15 match)
net(3 7 match)
net(4 8 match)
net(5 9 match)
net(6 10 match)
net(7 11 match)
net(8 12 match)
net(9 13 match)
net(10 14 match)
net(1 16 match)
net(15 4 match)
net(12 3 match)
net(14 5 match)
net(13 2 match)
net(16 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
device(1 1 match)
circuit(4 2 match)
circuit(5 3 match)
circuit(6 4 match)
circuit(7 5 match)
circuit(8 6 match)
circuit(9 7 match)
circuit(10 8 match)
circuit(11 9 match)
circuit(12 10 match)
circuit(13 11 match)
circuit(14 12 match)
circuit(3 1 match)
)
)
)

927
testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,927 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (28300 7650))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (1160 300))
)
net(2
rect(l11 (6050 2950) (900 300))
)
net(3
rect(l11 (7850 2950) (900 300))
)
net(4
rect(l11 (9650 2950) (900 300))
)
net(5
rect(l11 (11450 2950) (900 300))
)
net(6
rect(l11 (13250 2950) (900 300))
)
net(7
rect(l11 (15050 2950) (900 300))
)
net(8
rect(l11 (16850 2950) (900 300))
)
net(9
rect(l11 (18650 2950) (900 300))
)
net(10
rect(l11 (20450 2950) (900 300))
)
net(11 name(FB)
rect(l11 (22250 2950) (2900 300))
rect(l11 (-21980 590) (320 320))
rect(l11 (18570 -320) (320 320))
rect(l12 (-19150 -260) (200 200))
rect(l12 (18690 -200) (200 200))
rect(l13 (-18840 -300) (18890 400))
rect(l13 (-19071 -201) (2 2))
rect(l13 (-171 -201) (400 400))
rect(l13 (18490 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (22600 4500) (1400 3500))
rect(l3 (-23500 -3500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (25800 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-5090 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (25720 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-4891 1009) (2 2))
rect(l11 (2798 -52) (2 2))
rect(l11 (-22152 -102) (2 2))
rect(l11 (19749 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-22751 -401) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (25900 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-5250 -1500) (500 1500))
rect(l9 (-22600 -1500) (500 1500))
rect(l9 (25400 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (25990 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-151 -101) (2 2))
rect(l13 (-151 -201) (400 400))
)
net(14 name(ENABLE)
rect(l11 (2490 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-151 -101) (2 2))
rect(l13 (-151 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (27010 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-3980 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (24709 -291) (2 2))
rect(l11 (-3852 -2) (2 2))
rect(l11 (-19202 -102) (2 2))
rect(l11 (23999 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l11 (-5150 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-22301 -351) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l10 (26250 -800) (500 1500))
rect(l10 (-4300 -1500) (500 1500))
rect(l10 (-22600 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4700 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6500 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(8300 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(10100 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11900 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13700 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15500 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(17300 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(19100 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20900 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(24700 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

828
testdata/lvs/ringo_simple_io.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,828 @@
#%lvsdb-klayout
J(
W(RINGO)
U(0.001)
L(l3 '1/0')
L(l4 '5/0')
L(l8 '8/0')
L(l11 '9/0')
L(l12 '10/0')
L(l13 '11/0')
L(l7)
L(l2)
L(l9)
L(l6)
L(l10)
C(l3 l3 l9)
C(l4 l4 l8)
C(l8 l4 l8 l11 l2 l9 l6 l10)
C(l11 l8 l11 l12)
C(l12 l11 l12 l13)
C(l13 l12 l13)
C(l7 l7)
C(l2 l8 l2)
C(l9 l3 l8 l9)
C(l6 l8 l6)
C(l10 l8 l10)
G(l7 SUBSTRATE)
G(l10 SUBSTRATE)
D(D$PMOS PMOS
T(S
R(l2 (-550 -750) (425 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l2 (125 -750) (450 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$PMOS$1 PMOS
T(S
R(l2 (-575 -750) (450 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l2 (125 -750) (425 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$PMOS$2 PMOS
T(S
R(l2 (-550 -750) (425 1500))
)
T(G
R(l4 (-125 -750) (250 1500))
)
T(D
R(l2 (125 -750) (425 1500))
)
T(B
R(l3 (-125 -750) (250 1500))
)
)
D(D$NMOS NMOS
T(S
R(l6 (-550 -475) (425 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l6 (125 -475) (450 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
D(D$NMOS$1 NMOS
T(S
R(l6 (-575 -475) (450 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l6 (125 -475) (425 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
D(D$NMOS$2 NMOS
T(S
R(l6 (-550 -475) (425 950))
)
T(G
R(l4 (-125 -475) (250 950))
)
T(D
R(l6 (125 -475) (425 950))
)
T(B
R(l7 (-125 -475) (250 950))
)
)
X(ND2X1
R((-100 400) (2600 7600))
N(1 I(VDD)
R(l8 (1110 5160) (180 180))
R(l8 (-180 920) (180 180))
R(l8 (-180 -730) (180 180))
R(l11 (-240 -790) (300 1700))
R(l11 (-1350 0) (2400 800))
R(l11 (-1151 -401) (2 2))
R(l2 (-276 -2151) (425 1500))
R(l2 (-400 -1500) (425 1500))
)
N(2 I(OUT)
R(l8 (1810 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-1580 3760) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (1220 920) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
R(l11 (-110 1390) (300 1400))
Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
R(l11 (-141 -501) (2 2))
R(l11 (-1751 1099) (300 1400))
R(l11 (1100 -1700) (300 300))
R(l11 (-300 0) (300 1400))
R(l2 (-375 -1450) (425 1500))
R(l2 (-1800 -1500) (425 1500))
R(l6 (950 -4890) (425 950))
)
N(3 I(VSS)
R(l8 (410 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -1300) (300 1360))
R(l11 (-650 -2160) (2400 800))
R(l11 (-1151 -401) (2 2))
R(l6 (-951 859) (425 950))
)
N(4
R(l3 (-100 4500) (2600 3500))
)
N(5 I(B)
R(l4 (1425 2860) (250 1940))
R(l4 (-345 -950) (300 300))
R(l4 (-205 650) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-285 1050) (180 180))
R(l11 (-71 -91) (2 2))
R(l11 (-171 -151) (300 300))
)
N(6 I(A)
R(l4 (725 2860) (250 1940))
R(l4 (-325 -1850) (300 300))
R(l4 (-225 1550) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-265 150) (180 180))
R(l11 (-91 -91) (2 2))
R(l11 (-151 -151) (300 300))
)
N(7 I(SUBSTRATE))
N(8
R(l6 (975 1660) (425 950))
R(l6 (-400 -950) (425 950))
)
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4)
P(5 I(B))
P(6 I(A))
P(7 I(SUBSTRATE))
D(1 D$PMOS
Y(850 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.6375)
E(AD 0.3375)
E(PS 3.85)
E(PD 1.95)
T(S 2)
T(G 6)
T(D 1)
T(B 4)
)
D(2 D$PMOS$1
Y(1550 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.3375)
E(AD 0.6375)
E(PS 1.95)
E(PD 3.85)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(3 D$NMOS
Y(850 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.40375)
E(AD 0.21375)
E(PS 2.75)
E(PD 1.4)
T(S 3)
T(G 6)
T(D 8)
T(B 7)
)
D(4 D$NMOS$1
Y(1550 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.21375)
E(AD 0.40375)
E(PS 1.4)
E(PD 2.75)
T(S 8)
T(G 5)
T(D 2)
T(B 7)
)
)
X(INVX1
R((-100 400) (2000 7600))
N(1 I(VDD)
R(l8 (410 6260) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -730) (180 180))
R(l11 (-240 -240) (300 1400))
R(l11 (-650 300) (1800 800))
R(l11 (-1450 -1100) (300 300))
R(l11 (299 399) (2 2))
R(l2 (-651 -2151) (425 1500))
)
N(2 I(OUT)
R(l8 (1110 5160) (180 180))
R(l8 (-180 920) (180 180))
R(l8 (-180 -730) (180 180))
R(l8 (-180 -4120) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -790) (300 4790))
R(l11 (-151 -2501) (2 2))
R(l2 (-226 1049) (425 1500))
R(l6 (-425 -4890) (425 950))
)
N(3 I(VSS)
R(l8 (410 1770) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-240 -1300) (300 1360))
R(l11 (-650 -2160) (1800 800))
R(l11 (-851 -401) (2 2))
R(l6 (-651 859) (425 950))
)
N(4
R(l3 (-100 4500) (2000 3500))
)
N(5 I(IN)
R(l4 (725 2860) (250 1940))
R(l4 (-525 -1850) (300 300))
R(l4 (-25 1550) (250 2000))
R(l4 (-250 -2000) (250 2000))
R(l4 (-250 -5390) (250 1450))
R(l8 (-465 150) (180 180))
R(l11 (-91 -91) (2 2))
R(l11 (-151 -151) (300 300))
)
N(6 I(SUBSTRATE))
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4)
P(5 I(IN))
P(6 I(SUBSTRATE))
D(1 D$PMOS$2
Y(850 5800)
E(L 0.25)
E(W 1.5)
E(AS 0.6375)
E(AD 0.6375)
E(PS 3.85)
E(PD 3.85)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(2 D$NMOS$2
Y(850 2135)
E(L 0.25)
E(W 0.95)
E(AS 0.40375)
E(AD 0.40375)
E(PS 2.75)
E(PD 2.75)
T(S 3)
T(G 5)
T(D 2)
T(B 6)
)
)
X(RINGO
R((0 350) (25800 7650))
N(1
R(l11 (4040 2950) (610 300))
)
N(2
R(l11 (5550 2950) (900 300))
)
N(3
R(l11 (7350 2950) (900 300))
)
N(4
R(l11 (9150 2950) (900 300))
)
N(5
R(l11 (10950 2950) (900 300))
)
N(6
R(l11 (12750 2950) (900 300))
)
N(7
R(l11 (14550 2950) (900 300))
)
N(8
R(l11 (16350 2950) (900 300))
)
N(9
R(l11 (18150 2950) (900 300))
)
N(10
R(l11 (19950 2950) (900 300))
)
N(11 I(FB)
R(l11 (21750 2950) (900 300))
R(l11 (-19530 590) (320 320))
R(l11 (17820 -320) (320 320))
R(l12 (-18400 -260) (200 200))
R(l12 (17940 -200) (200 200))
R(l13 (-18040 -300) (17740 400))
R(l13 (-17921 -201) (2 2))
R(l13 (-221 -201) (400 400))
R(l13 (17740 -400) (400 400))
)
N(12 I(VDD)
R(l3 (500 4500) (1400 3500))
R(l3 (-1900 -3500) (600 3500))
R(l3 (23300 -3500) (1400 3500))
R(l3 (-100 -3500) (600 3500))
R(l8 (-24690 -1240) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (23220 370) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l11 (-21741 859) (2 2))
R(l11 (-2351 -451) (1200 800))
R(l11 (-750 -1450) (300 1400))
R(l11 (-101 -351) (2 2))
R(l11 (-1251 -401) (600 800))
R(l11 (23400 -800) (1200 800))
R(l11 (-750 -1450) (300 1400))
R(l11 (-101 -351) (2 2))
R(l11 (549 -401) (600 800))
R(l9 (-24850 -1500) (500 1500))
R(l9 (22900 -1500) (500 1500))
)
N(13 I(OUT)
R(l11 (23440 3840) (320 320))
R(l12 (-260 -260) (200 200))
R(l13 (-101 -101) (2 2))
R(l13 (-201 -201) (400 400))
)
N(14 I(ENABLE)
R(l11 (2440 2940) (320 320))
R(l12 (-260 -260) (200 200))
R(l13 (-101 -101) (2 2))
R(l13 (-201 -201) (400 400))
)
N(15 I(VSS)
R(l8 (1110 1610) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
R(l8 (23220 370) (180 180))
R(l8 (-180 -1280) (180 180))
R(l8 (-180 370) (180 180))
R(l11 (-21741 -391) (2 2))
R(l11 (-1901 -401) (300 1400))
R(l11 (-750 -1450) (1200 800))
R(l11 (-551 -401) (2 2))
R(l11 (-1251 -401) (600 800))
R(l11 (23850 -750) (300 1400))
R(l11 (-750 -1450) (1200 800))
R(l11 (-551 -401) (2 2))
R(l11 (549 -401) (600 800))
R(l10 (-24850 -800) (500 1500))
R(l10 (22900 -1500) (500 1500))
)
P(11 I(FB))
P(12 I(VDD))
P(13 I(OUT))
P(14 I(ENABLE))
P(15 I(VSS))
X(1 ND2X1 Y(1800 0)
P(0 12)
P(1 1)
P(2 15)
P(3 12)
P(4 11)
P(5 14)
P(6 15)
)
X(2 INVX1 Y(4200 0)
P(0 12)
P(1 2)
P(2 15)
P(3 12)
P(4 1)
P(5 15)
)
X(3 INVX1 Y(6000 0)
P(0 12)
P(1 3)
P(2 15)
P(3 12)
P(4 2)
P(5 15)
)
X(4 INVX1 Y(7800 0)
P(0 12)
P(1 4)
P(2 15)
P(3 12)
P(4 3)
P(5 15)
)
X(5 INVX1 Y(9600 0)
P(0 12)
P(1 5)
P(2 15)
P(3 12)
P(4 4)
P(5 15)
)
X(6 INVX1 Y(11400 0)
P(0 12)
P(1 6)
P(2 15)
P(3 12)
P(4 5)
P(5 15)
)
X(7 INVX1 Y(13200 0)
P(0 12)
P(1 7)
P(2 15)
P(3 12)
P(4 6)
P(5 15)
)
X(8 INVX1 Y(15000 0)
P(0 12)
P(1 8)
P(2 15)
P(3 12)
P(4 7)
P(5 15)
)
X(9 INVX1 Y(16800 0)
P(0 12)
P(1 9)
P(2 15)
P(3 12)
P(4 8)
P(5 15)
)
X(10 INVX1 Y(18600 0)
P(0 12)
P(1 10)
P(2 15)
P(3 12)
P(4 9)
P(5 15)
)
X(11 INVX1 Y(20400 0)
P(0 12)
P(1 11)
P(2 15)
P(3 12)
P(4 10)
P(5 15)
)
X(12 INVX1 Y(22200 0)
P(0 12)
P(1 13)
P(2 15)
P(3 12)
P(4 11)
P(5 15)
)
)
)
H(
X(ND2X1
N(1 I(VDD))
N(2 I(OUT))
N(3 I(VSS))
N(4 I(NWELL))
N(5 I(B))
N(6 I(A))
N(7 I(BULK))
N(8 I('1'))
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4 I(NWELL))
P(5 I(B))
P(6 I(A))
P(7 I(BULK))
D(1 PMOS
I($1)
E(L 0.25)
E(W 1.5)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(G 6)
T(D 1)
T(B 4)
)
D(2 PMOS
I($2)
E(L 0.25)
E(W 1.5)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(3 NMOS
I($3)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 3)
T(G 6)
T(D 8)
T(B 7)
)
D(4 NMOS
I($4)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 8)
T(G 5)
T(D 2)
T(B 7)
)
)
X(INVX1
N(1 I(VDD))
N(2 I(OUT))
N(3 I(VSS))
N(4 I(NWELL))
N(5 I(IN))
N(6 I(BULK))
P(1 I(VDD))
P(2 I(OUT))
P(3 I(VSS))
P(4 I(NWELL))
P(5 I(IN))
P(6 I(BULK))
D(1 PMOS
I($1)
E(L 0.25)
E(W 1.5)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 1)
T(G 5)
T(D 2)
T(B 4)
)
D(2 NMOS
I($2)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 3)
T(G 5)
T(D 2)
T(B 6)
)
)
X(RINGO
N(1 I(VSS))
N(2 I(VDD))
N(3 I(FB))
N(4 I(ENABLE))
N(5 I(OUT))
N(6 I('1'))
N(7 I('2'))
N(8 I('3'))
N(9 I('4'))
N(10 I('5'))
N(11 I('6'))
N(12 I('7'))
N(13 I('8'))
N(14 I('9'))
N(15 I('10'))
P(1 I(VSS))
P(2 I(VDD))
P(3 I(FB))
P(4 I(ENABLE))
P(5 I(OUT))
X(1 ND2X1 I($1)
P(0 2)
P(1 6)
P(2 1)
P(3 2)
P(4 3)
P(5 4)
P(6 1)
)
X(2 INVX1 I($2)
P(0 2)
P(1 7)
P(2 1)
P(3 2)
P(4 6)
P(5 1)
)
X(3 INVX1 I($3)
P(0 2)
P(1 8)
P(2 1)
P(3 2)
P(4 7)
P(5 1)
)
X(4 INVX1 I($4)
P(0 2)
P(1 9)
P(2 1)
P(3 2)
P(4 8)
P(5 1)
)
X(5 INVX1 I($5)
P(0 2)
P(1 10)
P(2 1)
P(3 2)
P(4 9)
P(5 1)
)
X(6 INVX1 I($6)
P(0 2)
P(1 11)
P(2 1)
P(3 2)
P(4 10)
P(5 1)
)
X(7 INVX1 I($7)
P(0 2)
P(1 12)
P(2 1)
P(3 2)
P(4 11)
P(5 1)
)
X(8 INVX1 I($8)
P(0 2)
P(1 13)
P(2 1)
P(3 2)
P(4 12)
P(5 1)
)
X(9 INVX1 I($9)
P(0 2)
P(1 14)
P(2 1)
P(3 2)
P(4 13)
P(5 1)
)
X(10 INVX1 I($10)
P(0 2)
P(1 15)
P(2 1)
P(3 2)
P(4 14)
P(5 1)
)
X(11 INVX1 I($11)
P(0 2)
P(1 3)
P(2 1)
P(3 2)
P(4 15)
P(5 1)
)
X(12 INVX1 I($12)
P(0 2)
P(1 5)
P(2 1)
P(3 2)
P(4 3)
P(5 1)
)
)
)
Z(
X(INVX1 INVX1 1
Z(
N(4 4 1)
N(5 5 1)
N(2 2 1)
N(6 6 1)
N(1 1 1)
N(3 3 1)
P(3 3 1)
P(4 4 1)
P(1 1 1)
P(5 5 1)
P(0 0 1)
P(2 2 1)
D(2 2 1)
D(1 1 1)
)
)
X(ND2X1 ND2X1 1
Z(
N(8 8 1)
N(4 4 1)
N(6 6 1)
N(5 5 1)
N(2 2 1)
N(7 7 1)
N(1 1 1)
N(3 3 1)
P(3 3 1)
P(5 5 1)
P(4 4 1)
P(1 1 1)
P(6 6 1)
P(0 0 1)
P(2 2 1)
D(3 3 1)
D(4 4 1)
D(1 1 1)
D(2 2 1)
)
)
X(RINGO RINGO 1
Z(
N(1 6 1)
N(10 15 1)
N(2 7 1)
N(3 8 1)
N(4 9 1)
N(5 10 1)
N(6 11 1)
N(7 12 1)
N(8 13 1)
N(9 14 1)
N(14 4 1)
N(11 3 1)
N(13 5 1)
N(12 2 1)
N(15 1 1)
P(3 3 1)
P(0 2 1)
P(2 4 1)
P(1 1 1)
P(4 0 1)
X(2 2 1)
X(3 3 1)
X(4 4 1)
X(5 5 1)
X(6 6 1)
X(7 7 1)
X(8 8 1)
X(9 9 1)
X(10 10 1)
X(11 11 1)
X(12 12 1)
X(1 1 1)
)
)
)

908
testdata/lvs/ringo_simple_io2.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,908 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (610 300))
)
net(2
rect(l11 (5550 2950) (900 300))
)
net(3
rect(l11 (7350 2950) (900 300))
)
net(4
rect(l11 (9150 2950) (900 300))
)
net(5
rect(l11 (10950 2950) (900 300))
)
net(6
rect(l11 (12750 2950) (900 300))
)
net(7
rect(l11 (14550 2950) (900 300))
)
net(8
rect(l11 (16350 2950) (900 300))
)
net(9
rect(l11 (18150 2950) (900 300))
)
net(10
rect(l11 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-24850 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l10 (-24850 -800) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

907
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,907 @@
#%lvsdb-klayout
# Layout
layout(
top(top)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(nd2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INV
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(top
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (610 300))
)
net(2
rect(l11 (5550 2950) (900 300))
)
net(3
rect(l11 (7350 2950) (900 300))
)
net(4
rect(l11 (9150 2950) (900 300))
)
net(5
rect(l11 (10950 2950) (900 300))
)
net(6
rect(l11 (12750 2950) (900 300))
)
net(7
rect(l11 (14550 2950) (900 300))
)
net(8
rect(l11 (16350 2950) (900 300))
)
net(9
rect(l11 (18150 2950) (900 300))
)
net(10
rect(l11 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-24850 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l10 (-24850 -800) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 nd2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INV location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INV location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INV location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INV location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INV location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INV location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INV location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INV location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INV location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INV location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INV location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INV INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(nd2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(top RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

908
testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,908 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l2 (-276 -2151) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-141 -501) (2 2))
rect(l11 (-1751 1099) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-375 -1450) (425 1500))
rect(l2 (-1800 -1500) (425 1500))
rect(l6 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1151 -401) (2 2))
rect(l6 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-71 -91) (2 2))
rect(l11 (-171 -151) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (299 399) (2 2))
rect(l2 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-151 -2501) (2 2))
rect(l2 (-226 1049) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-851 -401) (2 2))
rect(l6 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-91 -91) (2 2))
rect(l11 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l11 (4040 2950) (610 300))
)
net(2
rect(l11 (5550 2950) (900 300))
)
net(3
rect(l11 (7350 2950) (900 300))
)
net(4
rect(l11 (9150 2950) (900 300))
)
net(5
rect(l11 (10950 2950) (900 300))
)
net(6
rect(l11 (12750 2950) (900 300))
)
net(7
rect(l11 (14550 2950) (900 300))
)
net(8
rect(l11 (16350 2950) (900 300))
)
net(9
rect(l11 (18150 2950) (900 300))
)
net(10
rect(l11 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17921 -201) (2 2))
rect(l13 (-221 -201) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-24690 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21741 859) (2 2))
rect(l11 (-2351 -451) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-101 -351) (2 2))
rect(l11 (549 -401) (600 800))
rect(l9 (-24850 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-101 -101) (2 2))
rect(l13 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-21741 -391) (2 2))
rect(l11 (-1901 -401) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (-1251 -401) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-551 -401) (2 2))
rect(l11 (549 -401) (600 800))
rect(l10 (-24850 -800) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(A))
net(6 name(B))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(A))
pin(6 name(B))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 5)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 6)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 5 match)
net(5 6 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 4 match)
pin(4 5 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

910
testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 vendored Normal file
View File

@ -0,0 +1,910 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l5 '5/0')
layer(l14 '8/0')
layer(l17 '9/0')
layer(l18 '10/0')
layer(l19 '11/0')
layer(l8)
layer(l4)
layer(l15)
layer(l9)
layer(l16)
# Mask layer connectivity
connect(l3 l3 l15)
connect(l5 l5 l14)
connect(l14 l5 l14 l17 l4 l15 l9 l16)
connect(l17 l14 l17 l18)
connect(l18 l17 l18 l19)
connect(l19 l18 l19)
connect(l8 l8)
connect(l4 l14 l4)
connect(l15 l3 l14 l15)
connect(l9 l14 l9)
connect(l16 l14 l16)
# Global nets and connectivity
global(l8 SUBSTRATE)
global(l16 SUBSTRATE)
# Device class section
class(PM MOS4)
class(NM MOS4)
class(PMHV MOS4)
class(NMHV MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PM PM
terminal(S
rect(l4 (-550 -750) (425 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l4 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PM$1 PM
terminal(S
rect(l4 (-575 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l4 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PM$2 PM
terminal(S
rect(l4 (-550 -750) (425 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l4 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NM NM
terminal(S
rect(l9 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l9 (125 -475) (450 950))
)
terminal(B
rect(l8 (-125 -475) (250 950))
)
)
device(D$NM$1 NM
terminal(S
rect(l9 (-575 -475) (450 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l9 (125 -475) (425 950))
)
terminal(B
rect(l8 (-125 -475) (250 950))
)
)
device(D$NM$2 NM
terminal(S
rect(l9 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l9 (125 -475) (425 950))
)
terminal(B
rect(l8 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l14 (1110 5160) (180 180))
rect(l14 (-180 920) (180 180))
rect(l14 (-180 -730) (180 180))
rect(l17 (-240 -790) (300 1700))
rect(l17 (-1350 0) (2400 800))
rect(l17 (-1151 -401) (2 2))
rect(l4 (-276 -2151) (425 1500))
rect(l4 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l14 (1810 1770) (180 180))
rect(l14 (-180 370) (180 180))
rect(l14 (-1580 3760) (180 180))
rect(l14 (-180 -730) (180 180))
rect(l14 (-180 -730) (180 180))
rect(l14 (1220 920) (180 180))
rect(l14 (-180 -1280) (180 180))
rect(l14 (-180 370) (180 180))
polygon(l17 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l17 (-110 1390) (300 1400))
polygon(l17 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l17 (-141 -501) (2 2))
rect(l17 (-1751 1099) (300 1400))
rect(l17 (1100 -1700) (300 300))
rect(l17 (-300 0) (300 1400))
rect(l4 (-375 -1450) (425 1500))
rect(l4 (-1800 -1500) (425 1500))
rect(l9 (950 -4890) (425 950))
)
net(3 name(VSS)
rect(l14 (410 1770) (180 180))
rect(l14 (-180 370) (180 180))
rect(l17 (-240 -1300) (300 1360))
rect(l17 (-650 -2160) (2400 800))
rect(l17 (-1151 -401) (2 2))
rect(l9 (-951 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l5 (1425 2860) (250 1940))
rect(l5 (-345 -950) (300 300))
rect(l5 (-205 650) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l14 (-285 1050) (180 180))
rect(l17 (-71 -91) (2 2))
rect(l17 (-171 -151) (300 300))
)
net(6 name(A)
rect(l5 (725 2860) (250 1940))
rect(l5 (-325 -1850) (300 300))
rect(l5 (-225 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l14 (-265 150) (180 180))
rect(l17 (-91 -91) (2 2))
rect(l17 (-151 -151) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l9 (975 1660) (425 950))
rect(l9 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PM
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PM$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NM
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NM$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l14 (410 6260) (180 180))
rect(l14 (-180 -730) (180 180))
rect(l14 (-180 -730) (180 180))
rect(l17 (-240 -240) (300 1400))
rect(l17 (-650 300) (1800 800))
rect(l17 (-1450 -1100) (300 300))
rect(l17 (299 399) (2 2))
rect(l4 (-651 -2151) (425 1500))
)
net(2 name(OUT)
rect(l14 (1110 5160) (180 180))
rect(l14 (-180 920) (180 180))
rect(l14 (-180 -730) (180 180))
rect(l14 (-180 -4120) (180 180))
rect(l14 (-180 370) (180 180))
rect(l17 (-240 -790) (300 4790))
rect(l17 (-151 -2501) (2 2))
rect(l4 (-226 1049) (425 1500))
rect(l9 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l14 (410 1770) (180 180))
rect(l14 (-180 370) (180 180))
rect(l17 (-240 -1300) (300 1360))
rect(l17 (-650 -2160) (1800 800))
rect(l17 (-851 -401) (2 2))
rect(l9 (-651 859) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l5 (725 2860) (250 1940))
rect(l5 (-525 -1850) (300 300))
rect(l5 (-25 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l14 (-465 150) (180 180))
rect(l17 (-91 -91) (2 2))
rect(l17 (-151 -151) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PM$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NM$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l17 (4040 2950) (610 300))
)
net(2
rect(l17 (5550 2950) (900 300))
)
net(3
rect(l17 (7350 2950) (900 300))
)
net(4
rect(l17 (9150 2950) (900 300))
)
net(5
rect(l17 (10950 2950) (900 300))
)
net(6
rect(l17 (12750 2950) (900 300))
)
net(7
rect(l17 (14550 2950) (900 300))
)
net(8
rect(l17 (16350 2950) (900 300))
)
net(9
rect(l17 (18150 2950) (900 300))
)
net(10
rect(l17 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l17 (21750 2950) (900 300))
rect(l17 (-19530 590) (320 320))
rect(l17 (17820 -320) (320 320))
rect(l18 (-18400 -260) (200 200))
rect(l18 (17940 -200) (200 200))
rect(l19 (-18040 -300) (17740 400))
rect(l19 (-17921 -201) (2 2))
rect(l19 (-221 -201) (400 400))
rect(l19 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l14 (-24690 -1240) (180 180))
rect(l14 (-180 370) (180 180))
rect(l14 (-180 -1280) (180 180))
rect(l14 (23220 370) (180 180))
rect(l14 (-180 370) (180 180))
rect(l14 (-180 -1280) (180 180))
rect(l17 (-21741 859) (2 2))
rect(l17 (-2351 -451) (1200 800))
rect(l17 (-750 -1450) (300 1400))
rect(l17 (-101 -351) (2 2))
rect(l17 (-1251 -401) (600 800))
rect(l17 (23400 -800) (1200 800))
rect(l17 (-750 -1450) (300 1400))
rect(l17 (-101 -351) (2 2))
rect(l17 (549 -401) (600 800))
rect(l15 (-24850 -1500) (500 1500))
rect(l15 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l17 (23440 3840) (320 320))
rect(l18 (-260 -260) (200 200))
rect(l19 (-101 -101) (2 2))
rect(l19 (-201 -201) (400 400))
)
net(14 name(ENABLE)
rect(l17 (2440 2940) (320 320))
rect(l18 (-260 -260) (200 200))
rect(l19 (-101 -101) (2 2))
rect(l19 (-201 -201) (400 400))
)
net(15 name(VSS)
rect(l14 (1110 1610) (180 180))
rect(l14 (-180 -1280) (180 180))
rect(l14 (-180 370) (180 180))
rect(l14 (23220 370) (180 180))
rect(l14 (-180 -1280) (180 180))
rect(l14 (-180 370) (180 180))
rect(l17 (-21741 -391) (2 2))
rect(l17 (-1901 -401) (300 1400))
rect(l17 (-750 -1450) (1200 800))
rect(l17 (-551 -401) (2 2))
rect(l17 (-1251 -401) (600 800))
rect(l17 (23850 -750) (300 1400))
rect(l17 (-750 -1450) (1200 800))
rect(l17 (-551 -401) (2 2))
rect(l17 (549 -401) (600 800))
rect(l16 (-24850 -800) (500 1500))
rect(l16 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

1095
testdata/lvs/ringo_simple_simplification.lvsdb.2 vendored Normal file
View File

File diff suppressed because it is too large Load Diff

1095
testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 vendored Normal file
View File

File diff suppressed because it is too large Load Diff