mirror of
https://github.com/KLayout/klayout.git
synced 2026-09-02 10:57:51 +02:00
Merge branch 'issue-482' into issue-471
This commit is contained in:
Matthias Koefferlein
Binary file not shown.
Vendored
+23
@@ -0,0 +1,23 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
* cell NAND2_WITH_DIODES
|
||||
* pin B
|
||||
* pin A
|
||||
* pin OUT
|
||||
* pin VDD
|
||||
* pin VSS
|
||||
.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
|
||||
* net 1 B
|
||||
* net 2 A
|
||||
* net 4 OUT
|
||||
* net 5 VDD
|
||||
* net 6 VSS
|
||||
* device instance $1 r0 *1 1.025,4.95 PMOS
|
||||
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
|
||||
* device instance $2 r0 *1 1.775,4.95 PMOS
|
||||
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
|
||||
* device instance $3 r0 *1 1.025,2 NMOS
|
||||
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
|
||||
* device instance $4 r0 *1 1.775,2 NMOS
|
||||
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
|
||||
.ENDS NAND2_WITH_DIODES
|
||||
Vendored
+84
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|
||||
|
||||
source($lvs_test_source, "NAND2_WITH_DIODES")
|
||||
|
||||
report_lvs($lvs_test_target_lvsdb, true)
|
||||
|
||||
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
|
||||
|
||||
schematic("nand2_split_gate_schematic.cir")
|
||||
|
||||
deep
|
||||
|
||||
# Reports generated
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(6, 0)
|
||||
metal1 = input(7, 0)
|
||||
metal1_lbl = labels(7, 1)
|
||||
via1 = input(8, 0)
|
||||
metal2 = input(9, 0)
|
||||
metal2_lbl = labels(9, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, metal1_lbl) # attaches labels
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
connect(metal2, metal2_lbl) # attaches labels
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Extract, simplify
|
||||
|
||||
netlist
|
||||
join_symmetric_nets("*")
|
||||
netlist.simplify
|
||||
|
||||
# Compare section
|
||||
|
||||
compare
|
||||
|
||||
Vendored
+407
@@ -0,0 +1,407 @@
|
||||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(NAND2_WITH_DIODES)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 'NWELL (1/0)')
|
||||
layer(l4 'POLY (5/0)')
|
||||
layer(l8 'CONTACT (6/0)')
|
||||
layer(l11 'METAL1 (7/0)')
|
||||
layer(l12 'METAL1_LABEL (7/1)')
|
||||
layer(l13 'VIA1 (8/0)')
|
||||
layer(l14 'METAL2 (9/0)')
|
||||
layer(l15 'METAL2_LABEL (9/1)')
|
||||
layer(l7)
|
||||
layer(l2)
|
||||
layer(l9)
|
||||
layer(l6)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l2 l9 l6 l10)
|
||||
connect(l11 l8 l11 l12 l13)
|
||||
connect(l12 l11 l12)
|
||||
connect(l13 l11 l13 l14)
|
||||
connect(l14 l13 l14 l15)
|
||||
connect(l15 l14 l15)
|
||||
connect(l7 l7)
|
||||
connect(l2 l8 l2)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l6 l8 l6)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l2 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (500 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l2 (-625 -750) (500 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l6 (-575 -450) (450 900))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -450) (250 900))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -450) (500 900))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -450) (250 900))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l6 (-625 -450) (500 900))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -450) (250 900))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -450) (450 900))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -450) (250 900))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(NAND2_WITH_DIODES
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 0) (3750 6150))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(B)
|
||||
rect(l4 (350 2750) (550 400))
|
||||
rect(l4 (0 -2050) (250 3100))
|
||||
rect(l4 (-250 0) (250 1650))
|
||||
rect(l4 (-250 -5800) (250 1050))
|
||||
rect(l4 (-250 300) (250 1050))
|
||||
rect(l8 (-700 400) (200 200))
|
||||
rect(l11 (-300 -300) (400 400))
|
||||
rect(l12 (-201 -201) (2 2))
|
||||
)
|
||||
net(2 name(A)
|
||||
rect(l4 (1900 3400) (550 400))
|
||||
rect(l4 (-800 -2700) (250 3100))
|
||||
rect(l4 (-250 0) (250 1650))
|
||||
rect(l4 (-250 -5800) (250 1050))
|
||||
rect(l4 (-250 300) (250 1050))
|
||||
rect(l8 (250 1050) (200 200))
|
||||
rect(l11 (-300 -300) (400 400))
|
||||
rect(l12 (-201 -201) (2 2))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (1300 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 650) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l11 (-250 -2150) (300 900))
|
||||
rect(l11 (-300 -900) (300 850))
|
||||
rect(l11 (-300 500) (300 900))
|
||||
rect(l11 (-300 -900) (300 850))
|
||||
rect(l6 (-400 -2200) (500 900))
|
||||
rect(l6 (-500 450) (500 900))
|
||||
)
|
||||
net(4 name(OUT)
|
||||
rect(l8 (2050 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 650) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-950 2000) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l11 (500 -5350) (300 850))
|
||||
rect(l11 (-300 -50) (300 1950))
|
||||
rect(l11 (-300 -1400) (300 850))
|
||||
rect(l11 (-300 300) (450 400))
|
||||
rect(l11 (-1200 -300) (1050 300))
|
||||
rect(l11 (-1050 1150) (300 1400))
|
||||
rect(l11 (-300 -2700) (300 1950))
|
||||
rect(l12 (699 -2001) (2 2))
|
||||
rect(l2 (-1101 1299) (500 1500))
|
||||
rect(l6 (250 -5500) (450 900))
|
||||
rect(l6 (-450 450) (450 900))
|
||||
)
|
||||
net(5 name(VDD)
|
||||
rect(l3 (0 2950) (3750 3200))
|
||||
rect(l8 (-3200 -1800) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (1300 -1200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (700 -800) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l11 (-2650 -1200) (300 1600))
|
||||
rect(l11 (1200 -1600) (300 1600))
|
||||
rect(l11 (600 -1200) (300 1200))
|
||||
rect(l13 (-2650 -800) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (1300 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (700 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l14 (-3150 -850) (3750 1000))
|
||||
rect(l15 (-101 -851) (2 2))
|
||||
rect(l2 (-3201 -851) (450 1500))
|
||||
rect(l2 (1000 -1500) (450 1500))
|
||||
rect(l9 (400 -1200) (600 1200))
|
||||
)
|
||||
net(6 name(VSS)
|
||||
rect(l8 (550 1650) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -2050) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (2200 -550) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l11 (-2650 -50) (300 1350))
|
||||
rect(l11 (-300 -2400) (300 1050))
|
||||
rect(l11 (2100 -1050) (300 1200))
|
||||
rect(l13 (-2650 -1100) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (2200 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l14 (-3150 -850) (3750 1000))
|
||||
rect(l15 (-101 -851) (2 2))
|
||||
rect(l6 (-3201 1399) (450 900))
|
||||
rect(l6 (-450 -2250) (450 900))
|
||||
rect(l10 (1850 -900) (600 1200))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(B))
|
||||
pin(2 name(A))
|
||||
pin(4 name(OUT))
|
||||
pin(5 name(VDD))
|
||||
pin(6 name(VSS))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(1025 4950)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.675)
|
||||
param(AD 0.375)
|
||||
param(PS 3.9)
|
||||
param(PD 2)
|
||||
terminal(S 5)
|
||||
terminal(G 1)
|
||||
terminal(D 4)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1775 4950)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.375)
|
||||
param(AD 0.675)
|
||||
param(PS 2)
|
||||
param(PD 3.9)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 5)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
device(D$NMOS location(0 -1350))
|
||||
connect(0 S S)
|
||||
connect(1 S S)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D D)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(1025 2000)
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0.81)
|
||||
param(AD 0.45)
|
||||
param(PS 5.4)
|
||||
param(PD 2.8)
|
||||
terminal(S 6)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 6)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
device(D$NMOS$1 location(0 -1350))
|
||||
connect(0 S S)
|
||||
connect(1 S S)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D D)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(1775 2000)
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0.45)
|
||||
param(AD 0.81)
|
||||
param(PS 2.8)
|
||||
param(PD 5.4)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 4)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(NAND2_WITH_DIODES
|
||||
|
||||
# Nets
|
||||
net(1 name(A))
|
||||
net(2 name(B))
|
||||
net(3 name(OUT))
|
||||
net(4 name(VSS))
|
||||
net(5 name(VDD))
|
||||
net(6 name($1))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(A))
|
||||
pin(2 name(B))
|
||||
pin(3 name(OUT))
|
||||
pin(4 name(VSS))
|
||||
pin(5 name(VDD))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name('1')
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 5)
|
||||
terminal(G 2)
|
||||
terminal(D 3)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(2 PMOS
|
||||
name('2')
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 5)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(3 NMOS
|
||||
name('3')
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 6)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(4 NMOS
|
||||
name('4')
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 6)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 4)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(NAND2_WITH_DIODES NAND2_WITH_DIODES match
|
||||
xref(
|
||||
net(3 6 match)
|
||||
net(2 1 match)
|
||||
net(1 2 match)
|
||||
net(4 3 match)
|
||||
net(5 5 match)
|
||||
net(6 4 match)
|
||||
pin(1 0 match)
|
||||
pin(0 1 match)
|
||||
pin(2 2 match)
|
||||
pin(3 4 match)
|
||||
pin(4 3 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Vendored
BIN
Binary file not shown.
+7
@@ -0,0 +1,7 @@
|
||||
|
||||
.SUBCKT NAND2_WITH_DIODES A B OUT VSS VDD
|
||||
M1 VDD B OUT VDD PMOS L=0.25U W=1.5U
|
||||
M2 VDD A OUT VDD PMOS L=0.25U W=1.5U
|
||||
M3 VSS B $1 VSS NMOS L=0.25U W=1.8U
|
||||
M4 $1 A OUT VSS NMOS L=0.25U W=1.8U
|
||||
.ENDS
|
||||
Vendored
+54
@@ -90,6 +90,13 @@ class DBNetlist_TestClass < TestBase
|
||||
nl.each_circuit { |i| names << i.name }
|
||||
assert_equal(names, [ c.name, cc.name ])
|
||||
|
||||
assert_equal(nl.circuits_by_name("X*").collect { |c| c.name }, [ "XYZ" ])
|
||||
assert_equal(nl.circuits_by_name("???").collect { |c| c.name }, [ "XYZ", "UVW" ])
|
||||
assert_equal(nl.circuits_by_name("*").collect { |c| c.name }, [ "XYZ", "UVW" ])
|
||||
assert_equal(nl.circuits_by_name("P*").collect { |c| c.name }, [])
|
||||
assert_equal(nl.circuits_by_name("x*").collect { |c| c.name }, [])
|
||||
assert_equal(nl.circuits_by_name("").collect { |c| c.name }, [])
|
||||
|
||||
# same as _destroy
|
||||
nl.remove(c)
|
||||
|
||||
@@ -1015,6 +1022,53 @@ END
|
||||
assert_equal(nl2.to_s, <<"END")
|
||||
circuit RINGO (IN=(null),OSC=(null),VSS=(null),VDD=(null));
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
||||
def test_13_JoinNets
|
||||
|
||||
nl = RBA::Netlist::new
|
||||
|
||||
dc = RBA::DeviceClassMOS3Transistor::new
|
||||
dc.name = "NMOS"
|
||||
nl.add(dc)
|
||||
|
||||
dc = RBA::DeviceClassMOS3Transistor::new
|
||||
dc.name = "PMOS"
|
||||
nl.add(dc)
|
||||
|
||||
nl.from_s(<<"END")
|
||||
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
|
||||
subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);
|
||||
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);
|
||||
subcircuit PTRANS SC3 ($1=$5,$2=OUT,$3=$2);
|
||||
subcircuit NTRANS SC4 ($1=$4,$2=OUT,$3=$2);
|
||||
end;
|
||||
circuit PTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device PMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);
|
||||
end;
|
||||
circuit NTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device NMOS $1 (S=$1,D=$2,G=$3) (L=0.25,W=0.95);
|
||||
end;
|
||||
END
|
||||
|
||||
c = nl.circuit_by_name("INV2")
|
||||
c.join_nets(c.net_by_name("IN"), c.net_by_name("OUT"))
|
||||
|
||||
assert_equal(nl.to_s, <<"END")
|
||||
circuit INV2 (IN=IN,$2=$2,OUT=IN,$4=$4,$5=$5);
|
||||
subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);
|
||||
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);
|
||||
subcircuit PTRANS SC3 ($1=$5,$2=IN,$3=$2);
|
||||
subcircuit NTRANS SC4 ($1=$4,$2=IN,$3=$2);
|
||||
end;
|
||||
circuit PTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
end;
|
||||
circuit NTRANS ($1=$1,$2=$2,$3=$3);
|
||||
device NMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
||||
Vendored
+51
@@ -1015,6 +1015,57 @@ END
|
||||
|
||||
end
|
||||
|
||||
def test_11
|
||||
|
||||
nls = <<END
|
||||
circuit RESCUBE (A=A,B=B);
|
||||
device RES $1 (A=A,B=$1) (R=1000);
|
||||
device RES $2 (A=A,B=$2) (R=1000);
|
||||
device RES $3 (A=A,B=$3) (R=1000);
|
||||
device RES $4 (A=$1,B=$4) (R=1000);
|
||||
device RES $5 (A=$2,B=$4) (R=1000);
|
||||
device RES $6 (A=$2,B=$5) (R=1000);
|
||||
device RES $7 (A=$3,B=$5) (R=1000);
|
||||
device RES $8 (A=$3,B=$6) (R=1000);
|
||||
device RES $9 (A=$1,B=$6) (R=1000);
|
||||
device RES $9 (A=$4,B=B) (R=1000);
|
||||
device RES $10 (A=$5,B=B) (R=1000);
|
||||
device RES $11 (A=$6,B=B) (R=1000);
|
||||
end;
|
||||
END
|
||||
|
||||
nl = RBA::Netlist::new
|
||||
prep_nl(nl, nls)
|
||||
|
||||
comp = RBA::NetlistComparer::new
|
||||
comp.join_symmetric_nets(nl.circuit_by_name("RESCUBE"))
|
||||
|
||||
assert_equal(nl.to_s, <<END)
|
||||
circuit RESCUBE (A=A,B=B);
|
||||
device RES $1 (A=A,B=$1) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $2 (A=A,B=$1) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $3 (A=A,B=$1) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $4 (A=$1,B=$4) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $5 (A=$1,B=$4) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $6 (A=$1,B=$4) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $7 (A=$1,B=$4) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $8 (A=$1,B=$4) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $9 (A=$1,B=$4) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $10 (A=$4,B=B) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $11 (A=$4,B=B) (R=1000,L=0,W=0,A=0,P=0);
|
||||
device RES $12 (A=$4,B=B) (R=1000,L=0,W=0,A=0,P=0);
|
||||
end;
|
||||
END
|
||||
|
||||
nl.combine_devices
|
||||
assert_equal(nl.to_s, <<END)
|
||||
circuit RESCUBE (A=A,B=B);
|
||||
device RES $10 (A=A,B=B) (R=833.333333333,L=0,W=0,A=0,P=0);
|
||||
end;
|
||||
END
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
load("test_epilogue.rb")
|
||||
|
||||
Reference in New Issue
Block a user