mirror of
https://github.com/KLayout/klayout.git
synced 2026-08-29 09:20:45 +02:00
Merge branch 'master' into editor-hooks
This commit is contained in:
Matthias Koefferlein
Vendored
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@@ -29,7 +29,7 @@ J(
|
||||
G(l14 SUBSTRATE)
|
||||
H(W B('Must-connect nets GND must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
|
||||
H(W B('Must-connect nets R must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
|
||||
H(W B('Must-connect nets R of circuit INV2 must be connected further up in the hierarchy - this is an error at chip top level.\nInstance path: INVCHAIN:$1[r0 *1 0,0]/INV2') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
|
||||
H(W B('Must-connect nets R of circuit INV2 must be connected further up in the hierarchy - this is an error at chip top level.\nInstance path: INVCHAIN/INV2[r0 0,0]:$1') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
|
||||
K(PMOS MOS3)
|
||||
K(NMOS MOS3)
|
||||
D(D$PMOS PMOS
|
||||
|
||||
+1
-1
@@ -29,7 +29,7 @@ J(
|
||||
G(l14 SUBSTRATE)
|
||||
H(W B('Must-connect nets GND must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
|
||||
H(W B('Must-connect nets R must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
|
||||
H(W B('Must-connect nets R of circuit INV2 must be connected further up in the hierarchy - this is an error at chip top level.\nInstance path: INVCHAIN:$1[r0 *1 0,0]/INV2') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
|
||||
H(W B('Must-connect nets R of circuit INV2 must be connected further up in the hierarchy - this is an error at chip top level.\nInstance path: INVCHAIN/INV2[r0 0,0]:$1') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
|
||||
K(PMOS MOS3)
|
||||
K(NMOS MOS3)
|
||||
D(D$PMOS PMOS
|
||||
|
||||
Vendored
+1
-1
@@ -29,7 +29,7 @@ J(
|
||||
G(l14 SUBSTRATE)
|
||||
H(W B('Must-connect nets VSSTOP must be connected further up in the hierarchy - this is an error at chip top level') C(TOP) X('must-connect'))
|
||||
H(W B('Must-connect nets VDD must be connected further up in the hierarchy - this is an error at chip top level') C(TOP) X('must-connect'))
|
||||
H(W B('Must-connect nets VSS of circuit INV2 must be connected further up in the hierarchy - this is an error at chip top level.\nInstance path: INVCHAIN:$2[r0 *1 0,0]/INV2') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
|
||||
H(W B('Must-connect nets VSS of circuit INV2 must be connected further up in the hierarchy - this is an error at chip top level.\nInstance path: INVCHAIN/INV2[r0 0,0]:$2') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
|
||||
K(PMOS MOS3)
|
||||
K(NMOS MOS3)
|
||||
D(D$PMOS PMOS
|
||||
|
||||
Vendored
+13
@@ -0,0 +1,13 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT TOP A Q VDD SUBSTRATE|VSS
|
||||
X$1 SUBSTRATE|VSS VDD VDD \$1 Q SUBSTRATE|VSS INV
|
||||
X$2 SUBSTRATE|VSS VDD VDD A \$1 SUBSTRATE|VSS INV
|
||||
.ENDS TOP
|
||||
|
||||
.SUBCKT INV \$1 \$2 \$3 \$4 \$5 SUBSTRATE
|
||||
M$1 \$2 \$4 \$5 \$3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
M$2 \$1 \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
.ENDS INV
|
||||
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+217
@@ -0,0 +1,217 @@
|
||||
#%l2n-klayout
|
||||
W(TOP)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '3/0')
|
||||
L(l15 '3/1')
|
||||
L(l8 '4/0')
|
||||
L(l11 '5/0')
|
||||
L(l12 '6/0')
|
||||
L(l16 '6/1')
|
||||
L(l13 '7/0')
|
||||
L(l14 '8/0')
|
||||
L(l17 '8/1')
|
||||
L(l7)
|
||||
L(l10)
|
||||
L(l2)
|
||||
L(l9)
|
||||
L(l6)
|
||||
C(l3 l3 l10)
|
||||
C(l4 l4 l15 l11)
|
||||
C(l15 l4 l15)
|
||||
C(l8 l8 l12 l10 l2 l9 l6)
|
||||
CS(l8 l10 l2 l9 l6)
|
||||
C(l11 l4 l11 l12)
|
||||
CS(l11 l4)
|
||||
C(l12 l8 l11 l12 l16 l13)
|
||||
C(l16 l12 l16)
|
||||
C(l13 l12 l13 l14)
|
||||
C(l14 l13 l14 l17)
|
||||
C(l17 l14 l17)
|
||||
C(l7 l7)
|
||||
C(l10 l3 l8 l10)
|
||||
CS(l10 l3)
|
||||
C(l2 l8 l2)
|
||||
C(l9 l8 l9)
|
||||
C(l6 l8 l6)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l9 SUBSTRATE)
|
||||
GS(l9 SUBSTRATE)
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - VDD') C(TOP) Q('(0.6,3.95;0.6,4.85;4.5,4.85;4.5,3.95)'))
|
||||
H(B('\tPartial net #2: TOP - $I4') C(TOP) Q('(5.1,3.95;5.1,4.85;9,4.85;9,3.95)'))
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - VSS') C(TOP) Q('(0.6,1.15;0.6,2.05;4.5,2.05;4.5,1.15)'))
|
||||
H(B('\tPartial net #2: TOP - $I1') C(TOP) Q('(5.1,1.15;5.1,2.05;9,2.05;9,1.15)'))
|
||||
K(PMOS MOS4)
|
||||
K(NMOS MOS4)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l6 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l6 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3000 4600))
|
||||
N(1
|
||||
R(l8 (290 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l14 (-2025 -775) (3000 900))
|
||||
R(l6 (-1375 -925) (775 950))
|
||||
)
|
||||
N(2
|
||||
R(l8 (290 2490) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l14 (-2025 -775) (3000 900))
|
||||
R(l2 (-1375 -925) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l3 (-1500 1800) (3000 2000))
|
||||
)
|
||||
N(4
|
||||
R(l4 (-125 -250) (250 2500))
|
||||
R(l4 (-250 -3050) (250 1600))
|
||||
R(l4 (-250 1200) (250 1600))
|
||||
)
|
||||
N(5
|
||||
R(l8 (-510 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (-220 2180) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -3530) (360 2840))
|
||||
R(l12 (-360 -2800) (360 760))
|
||||
R(l12 (-360 2040) (360 760))
|
||||
R(l2 (-680 -855) (775 950))
|
||||
R(l6 (-775 -3750) (775 950))
|
||||
)
|
||||
N(6 I(SUBSTRATE))
|
||||
P(1)
|
||||
P(2)
|
||||
P(3)
|
||||
P(4)
|
||||
P(5)
|
||||
P(6 I(SUBSTRATE))
|
||||
D(1 D$PMOS
|
||||
Y(0 2800)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 5)
|
||||
T(G 4)
|
||||
T(D 2)
|
||||
T(B 3)
|
||||
)
|
||||
D(2 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 5)
|
||||
T(G 4)
|
||||
T(D 1)
|
||||
T(B 6)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((600 800) (8880 4600))
|
||||
N(1
|
||||
R(l4 (2920 2600) (2880 400))
|
||||
R(l11 (-300 -300) (200 200))
|
||||
R(l12 (-300 -300) (690 400))
|
||||
)
|
||||
N(2 I(A)
|
||||
R(l4 (6600 2600) (2880 400))
|
||||
R(l15 (-2380 -200) (0 0))
|
||||
)
|
||||
N(3 I(Q)
|
||||
R(l12 (1810 2600) (690 400))
|
||||
R(l16 (-400 -200) (0 0))
|
||||
)
|
||||
N(4 I(VDD)
|
||||
R(l3 (4000 3400) (1600 2000))
|
||||
R(l3 (-5000 -2000) (1000 2000))
|
||||
R(l3 (6400 -2000) (1000 2000))
|
||||
R(l8 (-8000 -900) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (7200 200) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-7900 -350) (800 900))
|
||||
R(l12 (6600 -900) (800 900))
|
||||
R(l13 (-7900 -350) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l13 (7200 200) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-8000 -350) (1000 900))
|
||||
R(l14 (6400 -900) (1000 900))
|
||||
R(l17 (-4800 -450) (0 0))
|
||||
)
|
||||
N(5 I('SUBSTRATE,VSS')
|
||||
R(l8 (1000 1700) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (7200 200) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-7900 -350) (800 900))
|
||||
R(l12 (6600 -900) (800 900))
|
||||
R(l13 (-7900 -350) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l13 (7200 200) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-8000 -350) (1000 900))
|
||||
R(l14 (6400 -900) (1000 900))
|
||||
R(l17 (-4800 -550) (0 0))
|
||||
)
|
||||
P(2 I(A))
|
||||
P(3 I(Q))
|
||||
P(4 I(VDD))
|
||||
P(5 I('SUBSTRATE,VSS'))
|
||||
X(1 INV Y(3000 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 4)
|
||||
P(3 1)
|
||||
P(4 3)
|
||||
P(5 5)
|
||||
)
|
||||
X(2 INV Y(6600 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 4)
|
||||
P(3 2)
|
||||
P(4 1)
|
||||
P(5 5)
|
||||
)
|
||||
)
|
||||
Vendored
+92
@@ -0,0 +1,92 @@
|
||||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
Vendored
+13
@@ -0,0 +1,13 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT TOP A Q VDD SUBSTRATE|VSS
|
||||
X$1 SUBSTRATE|VSS VDD VDD \$1 Q SUBSTRATE|VSS INV
|
||||
X$2 SUBSTRATE|VSS VDD VDD A \$1 SUBSTRATE|VSS INV
|
||||
.ENDS TOP
|
||||
|
||||
.SUBCKT INV \$1 \$2 \$3 \$4 \$5 SUBSTRATE
|
||||
M$1 \$2 \$4 \$5 \$3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
M$2 \$1 \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
.ENDS INV
|
||||
Vendored
BIN
Binary file not shown.
Vendored
+213
@@ -0,0 +1,213 @@
|
||||
#%l2n-klayout
|
||||
W(TOP)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '3/0')
|
||||
L(l15 '3/1')
|
||||
L(l8 '4/0')
|
||||
L(l11 '5/0')
|
||||
L(l12 '6/0')
|
||||
L(l16 '6/1')
|
||||
L(l13 '7/0')
|
||||
L(l14 '8/0')
|
||||
L(l17 '8/1')
|
||||
L(l7)
|
||||
L(l10)
|
||||
L(l2)
|
||||
L(l9)
|
||||
L(l6)
|
||||
C(l3 l3 l10)
|
||||
C(l4 l4 l15 l11)
|
||||
C(l15 l4 l15)
|
||||
C(l8 l8 l12 l10 l2 l9 l6)
|
||||
CS(l8 l10 l2 l9 l6)
|
||||
C(l11 l4 l11 l12)
|
||||
CS(l11 l4)
|
||||
C(l12 l8 l11 l12 l16 l13)
|
||||
C(l16 l12 l16)
|
||||
C(l13 l12 l13 l14)
|
||||
C(l14 l13 l14 l17)
|
||||
C(l17 l14 l17)
|
||||
C(l7 l7)
|
||||
C(l10 l3 l8 l10)
|
||||
CS(l10 l3)
|
||||
C(l2 l8 l2)
|
||||
C(l9 l8 l9)
|
||||
C(l6 l8 l6)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l9 SUBSTRATE)
|
||||
GS(l9 SUBSTRATE)
|
||||
K(PMOS MOS4)
|
||||
K(NMOS MOS4)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l6 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l6 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3000 4600))
|
||||
N(1
|
||||
R(l8 (290 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l14 (-2025 -775) (3000 900))
|
||||
R(l6 (-1375 -925) (775 950))
|
||||
)
|
||||
N(2
|
||||
R(l8 (290 2490) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l14 (-2025 -775) (3000 900))
|
||||
R(l2 (-1375 -925) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l3 (-1500 1800) (3000 2000))
|
||||
)
|
||||
N(4
|
||||
R(l4 (-125 -250) (250 2500))
|
||||
R(l4 (-250 -3050) (250 1600))
|
||||
R(l4 (-250 1200) (250 1600))
|
||||
)
|
||||
N(5
|
||||
R(l8 (-510 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (-220 2180) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -3530) (360 2840))
|
||||
R(l12 (-360 -2800) (360 760))
|
||||
R(l12 (-360 2040) (360 760))
|
||||
R(l2 (-680 -855) (775 950))
|
||||
R(l6 (-775 -3750) (775 950))
|
||||
)
|
||||
N(6 I(SUBSTRATE))
|
||||
P(1)
|
||||
P(2)
|
||||
P(3)
|
||||
P(4)
|
||||
P(5)
|
||||
P(6 I(SUBSTRATE))
|
||||
D(1 D$PMOS
|
||||
Y(0 2800)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 5)
|
||||
T(G 4)
|
||||
T(D 2)
|
||||
T(B 3)
|
||||
)
|
||||
D(2 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 5)
|
||||
T(G 4)
|
||||
T(D 1)
|
||||
T(B 6)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((600 800) (8880 4600))
|
||||
N(1
|
||||
R(l4 (2920 2600) (2880 400))
|
||||
R(l11 (-300 -300) (200 200))
|
||||
R(l12 (-300 -300) (690 400))
|
||||
)
|
||||
N(2 I(A)
|
||||
R(l4 (6600 2600) (2880 400))
|
||||
R(l15 (-2380 -200) (0 0))
|
||||
)
|
||||
N(3 I(Q)
|
||||
R(l12 (1810 2600) (690 400))
|
||||
R(l16 (-400 -200) (0 0))
|
||||
)
|
||||
N(4 I(VDD)
|
||||
R(l3 (4000 3400) (1600 2000))
|
||||
R(l3 (-5000 -2000) (1000 2000))
|
||||
R(l3 (6400 -2000) (1000 2000))
|
||||
R(l8 (-8000 -900) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (7200 200) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-7900 -350) (800 900))
|
||||
R(l12 (6600 -900) (800 900))
|
||||
R(l13 (-7900 -350) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l13 (7200 200) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-4400 -350) (1200 900))
|
||||
R(l14 (-4800 -900) (1000 900))
|
||||
R(l14 (6400 -900) (1000 900))
|
||||
R(l17 (-4800 -450) (0 0))
|
||||
)
|
||||
N(5 I('SUBSTRATE,VSS')
|
||||
R(l8 (1000 1700) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (7200 200) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-7900 -350) (800 900))
|
||||
R(l12 (6600 -900) (800 900))
|
||||
R(l13 (-7900 -350) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l13 (7200 200) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-4400 -350) (1200 900))
|
||||
R(l14 (-4800 -900) (1000 900))
|
||||
R(l14 (6400 -900) (1000 900))
|
||||
R(l17 (-4800 -550) (0 0))
|
||||
)
|
||||
P(2 I(A))
|
||||
P(3 I(Q))
|
||||
P(4 I(VDD))
|
||||
P(5 I('SUBSTRATE,VSS'))
|
||||
X(1 INV Y(3000 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 4)
|
||||
P(3 1)
|
||||
P(4 3)
|
||||
P(5 5)
|
||||
)
|
||||
X(2 INV Y(6600 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 4)
|
||||
P(3 2)
|
||||
P(4 1)
|
||||
P(5 5)
|
||||
)
|
||||
)
|
||||
Vendored
+92
@@ -0,0 +1,92 @@
|
||||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
Vendored
+21
@@ -0,0 +1,21 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT TOP A Q VDD SUBSTRATE|VSS
|
||||
X$1 SUBSTRATE|VSS VDD VDD \$1 Q SUBSTRATE|VSS INV
|
||||
X$2 SUBSTRATE|VSS VDD VDD A \$1 SUBSTRATE|VSS INV
|
||||
.ENDS TOP
|
||||
|
||||
.SUBCKT INV \$1 \$2 \$3 \$4 \$5 SUBSTRATE
|
||||
X$1 \$5 \$1 \$4 SUBSTRATE NTRANS
|
||||
X$2 \$5 \$2 \$4 \$3 PTRANS
|
||||
.ENDS INV
|
||||
|
||||
.SUBCKT PTRANS \$1 \$3 \$5 \$I3
|
||||
M$1 \$3 \$5 \$1 \$I3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
.ENDS PTRANS
|
||||
|
||||
.SUBCKT NTRANS \$1 \$3 \$5 SUBSTRATE
|
||||
M$1 \$3 \$5 \$1 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
.ENDS NTRANS
|
||||
Vendored
BIN
Binary file not shown.
Vendored
+257
@@ -0,0 +1,257 @@
|
||||
#%l2n-klayout
|
||||
W(TOP)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '3/0')
|
||||
L(l15 '3/1')
|
||||
L(l8 '4/0')
|
||||
L(l11 '5/0')
|
||||
L(l12 '6/0')
|
||||
L(l16 '6/1')
|
||||
L(l13 '7/0')
|
||||
L(l14 '8/0')
|
||||
L(l17 '8/1')
|
||||
L(l7)
|
||||
L(l10)
|
||||
L(l2)
|
||||
L(l9)
|
||||
L(l6)
|
||||
C(l3 l3 l10)
|
||||
C(l4 l4 l15 l11)
|
||||
C(l15 l4 l15)
|
||||
C(l8 l8 l12 l10 l2 l9 l6)
|
||||
CS(l8 l10 l2 l9 l6)
|
||||
C(l11 l4 l11 l12)
|
||||
CS(l11 l4)
|
||||
C(l12 l8 l11 l12 l16 l13)
|
||||
C(l16 l12 l16)
|
||||
C(l13 l12 l13 l14)
|
||||
C(l14 l13 l14 l17)
|
||||
C(l17 l14 l17)
|
||||
C(l7 l7)
|
||||
C(l10 l3 l8 l10)
|
||||
CS(l10 l3)
|
||||
C(l2 l8 l2)
|
||||
C(l9 l8 l9)
|
||||
C(l6 l8 l6)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l9 SUBSTRATE)
|
||||
GS(l9 SUBSTRATE)
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - VDD') C(TOP) Q('(0.6,3.95;0.6,4.85;4.5,4.85;4.5,3.95)'))
|
||||
H(B('\tPartial net #2: TOP - $I4') C(TOP) Q('(5.1,3.95;5.1,4.85;9,4.85;9,3.95)'))
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - VSS') C(TOP) Q('(0.6,1.15;0.6,2.05;4.5,2.05;4.5,1.15)'))
|
||||
H(B('\tPartial net #2: TOP - $I1') C(TOP) Q('(5.1,1.15;5.1,2.05;9,2.05;9,1.15)'))
|
||||
K(PMOS MOS4)
|
||||
K(NMOS MOS4)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l6 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l6 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(NTRANS
|
||||
R((-1000 -800) (2000 1600))
|
||||
N(1
|
||||
R(l8 (-510 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l6 (-680 -855) (775 950))
|
||||
)
|
||||
N(2
|
||||
R(l8 (290 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l6 (-455 -855) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l4 (-125 -800) (250 1600))
|
||||
)
|
||||
N(4 I(SUBSTRATE))
|
||||
P(1)
|
||||
P(2)
|
||||
P(3)
|
||||
P(4 I(SUBSTRATE))
|
||||
D(1 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 1)
|
||||
T(G 3)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
)
|
||||
X(PTRANS
|
||||
R((-1000 -800) (2000 1600))
|
||||
N(1
|
||||
R(l8 (-510 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l2 (-680 -855) (775 950))
|
||||
)
|
||||
N(2
|
||||
R(l8 (290 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -690) (360 760))
|
||||
R(l2 (-455 -855) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l4 (-125 -800) (250 1600))
|
||||
)
|
||||
N(4)
|
||||
P(1)
|
||||
P(2)
|
||||
P(3)
|
||||
P(4)
|
||||
D(1 D$PMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 1)
|
||||
T(G 3)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3000 4600))
|
||||
N(1
|
||||
R(l13 (275 -325) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l14 (-2025 -775) (3000 900))
|
||||
)
|
||||
N(2
|
||||
R(l13 (275 2475) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l14 (-2025 -775) (3000 900))
|
||||
)
|
||||
N(3
|
||||
R(l3 (-1500 1800) (3000 2000))
|
||||
)
|
||||
N(4
|
||||
R(l4 (-125 -250) (250 2500))
|
||||
)
|
||||
N(5
|
||||
R(l12 (-580 -420) (360 2840))
|
||||
)
|
||||
N(6 I(SUBSTRATE))
|
||||
P(1)
|
||||
P(2)
|
||||
P(3)
|
||||
P(4)
|
||||
P(5)
|
||||
P(6 I(SUBSTRATE))
|
||||
X(1 NTRANS Y(0 0)
|
||||
P(0 5)
|
||||
P(1 1)
|
||||
P(2 4)
|
||||
P(3 6)
|
||||
)
|
||||
X(2 PTRANS Y(0 2800)
|
||||
P(0 5)
|
||||
P(1 2)
|
||||
P(2 4)
|
||||
P(3 3)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((600 800) (8880 4600))
|
||||
N(1
|
||||
R(l4 (2920 2600) (2880 400))
|
||||
R(l11 (-300 -300) (200 200))
|
||||
R(l12 (-300 -300) (690 400))
|
||||
)
|
||||
N(2 I(A)
|
||||
R(l4 (6600 2600) (2880 400))
|
||||
R(l15 (-2380 -200) (0 0))
|
||||
)
|
||||
N(3 I(Q)
|
||||
R(l12 (1810 2600) (690 400))
|
||||
R(l16 (-400 -200) (0 0))
|
||||
)
|
||||
N(4 I(VDD)
|
||||
R(l3 (4000 3400) (1600 2000))
|
||||
R(l3 (-5000 -2000) (1000 2000))
|
||||
R(l3 (6400 -2000) (1000 2000))
|
||||
R(l8 (-8000 -900) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (7200 200) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-7900 -350) (800 900))
|
||||
R(l12 (6600 -900) (800 900))
|
||||
R(l13 (-7900 -350) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l13 (7200 200) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-8000 -350) (1000 900))
|
||||
R(l14 (6400 -900) (1000 900))
|
||||
R(l17 (-4800 -450) (0 0))
|
||||
)
|
||||
N(5 I('SUBSTRATE,VSS')
|
||||
R(l8 (1000 1700) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (7200 200) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-7900 -350) (800 900))
|
||||
R(l12 (6600 -900) (800 900))
|
||||
R(l13 (-7900 -350) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l13 (7200 200) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-8000 -350) (1000 900))
|
||||
R(l14 (6400 -900) (1000 900))
|
||||
R(l17 (-4800 -550) (0 0))
|
||||
)
|
||||
P(2 I(A))
|
||||
P(3 I(Q))
|
||||
P(4 I(VDD))
|
||||
P(5 I('SUBSTRATE,VSS'))
|
||||
X(1 INV Y(3000 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 4)
|
||||
P(3 1)
|
||||
P(4 3)
|
||||
P(5 5)
|
||||
)
|
||||
X(2 INV Y(6600 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 4)
|
||||
P(3 2)
|
||||
P(4 1)
|
||||
P(5 5)
|
||||
)
|
||||
)
|
||||
Vendored
+92
@@ -0,0 +1,92 @@
|
||||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
Vendored
+13
@@ -0,0 +1,13 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT TOP A Q SUBSTRATE
|
||||
X$1 \$5 \$1 Q SUBSTRATE INV
|
||||
X$2 \$5 A \$1 SUBSTRATE INV
|
||||
.ENDS TOP
|
||||
|
||||
.SUBCKT INV \$2 \$4 \$5 SUBSTRATE
|
||||
M$1 \$2 \$4 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
M$2 SUBSTRATE \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
|
||||
+ PS=3.45U PD=3.45U
|
||||
.ENDS INV
|
||||
Vendored
BIN
Binary file not shown.
Vendored
+192
@@ -0,0 +1,192 @@
|
||||
#%l2n-klayout
|
||||
W(TOP)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '3/0')
|
||||
L(l15 '3/1')
|
||||
L(l8 '4/0')
|
||||
L(l11 '5/0')
|
||||
L(l12 '6/0')
|
||||
L(l16 '6/1')
|
||||
L(l13 '7/0')
|
||||
L(l14 '8/0')
|
||||
L(l17)
|
||||
L(l7)
|
||||
L(l10)
|
||||
L(l2)
|
||||
L(l9)
|
||||
L(l6)
|
||||
C(l3 l3 l10)
|
||||
C(l4 l4 l15 l11)
|
||||
C(l15 l4 l15)
|
||||
C(l8 l8 l12 l10 l2 l9 l6)
|
||||
CS(l8 l10 l2 l9 l6)
|
||||
C(l11 l4 l11 l12)
|
||||
CS(l11 l4)
|
||||
C(l12 l8 l11 l12 l16 l13)
|
||||
C(l16 l12 l16)
|
||||
C(l13 l12 l13 l14)
|
||||
C(l14 l13 l14 l17)
|
||||
C(l17 l14 l17)
|
||||
C(l7 l7)
|
||||
C(l10 l3 l8 l10)
|
||||
CS(l10 l3)
|
||||
C(l2 l8 l2)
|
||||
C(l9 l8 l9)
|
||||
C(l6 l8 l6)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l9 SUBSTRATE)
|
||||
GS(l9 SUBSTRATE)
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP/INV[r0 3,1.6]:$1 - $2') C(TOP) Q('(1.5,3.95;1.5,4.85;5.3,4.85;5.3,3.95)'))
|
||||
H(B('\tPartial net #2: TOP/INV[r0 7.7,1.6]:$2 - $2') C(TOP) Q('(6.2,3.95;6.2,4.85;10,4.85;10,3.95)'))
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP/INV[r0 3,1.6]:$1 - $1') C(TOP) Q('(1.5,1.15;1.5,2.05;5.3,2.05;5.3,1.15)'))
|
||||
H(B('\tPartial net #2: TOP/INV[r0 7.7,1.6]:$2 - $1') C(TOP) Q('(6.2,1.15;6.2,2.05;10,2.05;10,1.15)'))
|
||||
K(PMOS MOS4)
|
||||
K(NMOS MOS4)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l6 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l6 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3800 4600))
|
||||
N(1 I(SUBSTRATE)
|
||||
R(l8 (1700 100) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (-1610 -210) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (890 -760) (800 900))
|
||||
R(l12 (-1980 -830) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l6 (-2175 -925) (775 950))
|
||||
)
|
||||
N(2
|
||||
R(l3 (-1500 1800) (3000 2000))
|
||||
R(l3 (-200 -2000) (1000 2000))
|
||||
R(l8 (-2010 -1310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (1190 -210) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-1680 -280) (360 760))
|
||||
R(l12 (820 -830) (800 900))
|
||||
R(l13 (-1925 -775) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l10 (-700 -950) (400 1000))
|
||||
R(l2 (-1875 -975) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l4 (-125 -250) (250 2500))
|
||||
R(l4 (-250 -3050) (250 1600))
|
||||
R(l4 (-250 1200) (250 1600))
|
||||
)
|
||||
N(4
|
||||
R(l8 (-510 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (-220 2180) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -3530) (360 2840))
|
||||
R(l12 (-360 -2800) (360 760))
|
||||
R(l12 (-360 2040) (360 760))
|
||||
R(l2 (-680 -855) (775 950))
|
||||
R(l6 (-775 -3750) (775 950))
|
||||
)
|
||||
P(2)
|
||||
P(3)
|
||||
P(4)
|
||||
P(1 I(SUBSTRATE))
|
||||
D(1 D$PMOS
|
||||
Y(0 2800)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 4)
|
||||
T(G 3)
|
||||
T(D 2)
|
||||
T(B 2)
|
||||
)
|
||||
D(2 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 4)
|
||||
T(G 3)
|
||||
T(D 1)
|
||||
T(B 1)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((1500 800) (9080 4600))
|
||||
N(1
|
||||
R(l4 (2920 2600) (3980 400))
|
||||
R(l11 (-300 -300) (200 200))
|
||||
R(l12 (-300 -300) (690 400))
|
||||
)
|
||||
N(2 I(A)
|
||||
R(l4 (7700 2600) (2880 400))
|
||||
R(l15 (-2380 -200) (0 0))
|
||||
)
|
||||
N(3 I(Q)
|
||||
R(l12 (1810 2600) (690 400))
|
||||
R(l16 (-400 -200) (0 0))
|
||||
)
|
||||
N(4
|
||||
R(l3 (4000 3400) (2700 2000))
|
||||
)
|
||||
N(5 I(SUBSTRATE))
|
||||
P(2 I(A))
|
||||
P(3 I(Q))
|
||||
P(5 I(SUBSTRATE))
|
||||
X(1 INV Y(3000 1600)
|
||||
P(0 4)
|
||||
P(1 1)
|
||||
P(2 3)
|
||||
P(3 5)
|
||||
)
|
||||
X(2 INV Y(7700 1600)
|
||||
P(0 4)
|
||||
P(1 2)
|
||||
P(2 1)
|
||||
P(3 5)
|
||||
)
|
||||
)
|
||||
Vendored
+93
@@ -0,0 +1,93 @@
|
||||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
# for debugging: _make_soft_connection_diodes(true)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
Vendored
+13
@@ -0,0 +1,13 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT TOP A Q VDD SUBSTRATE|VSS
|
||||
X$1 SUBSTRATE|VSS VDD \$1 Q INV
|
||||
X$2 SUBSTRATE|VSS VDD A \$1 INV
|
||||
.ENDS TOP
|
||||
|
||||
.SUBCKT INV SUBSTRATE \$2 \$4 \$5
|
||||
M$1 \$2 \$4 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
|
||||
+ PD=3.45U
|
||||
M$2 SUBSTRATE \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
|
||||
+ PS=3.45U PD=3.45U
|
||||
.ENDS INV
|
||||
Vendored
BIN
Binary file not shown.
Vendored
+196
@@ -0,0 +1,196 @@
|
||||
#%l2n-klayout
|
||||
W(TOP)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '3/0')
|
||||
L(l15 '3/1')
|
||||
L(l8 '4/0')
|
||||
L(l11 '5/0')
|
||||
L(l12 '6/0')
|
||||
L(l16 '6/1')
|
||||
L(l13 '7/0')
|
||||
L(l14 '8/0')
|
||||
L(l17 '8/1')
|
||||
L(l7)
|
||||
L(l10)
|
||||
L(l2)
|
||||
L(l9)
|
||||
L(l6)
|
||||
C(l3 l3 l10)
|
||||
C(l4 l4 l15 l11)
|
||||
C(l15 l4 l15)
|
||||
C(l8 l8 l12 l10 l2 l9 l6)
|
||||
CS(l8 l10 l2 l9 l6)
|
||||
C(l11 l4 l11 l12)
|
||||
CS(l11 l4)
|
||||
C(l12 l8 l11 l12 l16 l13)
|
||||
C(l16 l12 l16)
|
||||
C(l13 l12 l13 l14)
|
||||
C(l14 l13 l14 l17)
|
||||
C(l17 l14 l17)
|
||||
C(l7 l7)
|
||||
C(l10 l3 l8 l10)
|
||||
CS(l10 l3)
|
||||
C(l2 l8 l2)
|
||||
C(l9 l8 l9)
|
||||
C(l6 l8 l6)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l9 SUBSTRATE)
|
||||
GS(l9 SUBSTRATE)
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - VDD') C(TOP) Q('(1.5,3.95;1.5,4.85;5.3,4.85;5.3,3.95)'))
|
||||
H(B('\tPartial net #2: TOP - $I7') C(TOP) Q('(6.2,3.95;6.2,4.85;10,4.85;10,3.95)'))
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - VSS') C(TOP) Q('(1.5,1.15;1.5,2.05;5.3,2.05;5.3,1.15)'))
|
||||
H(B('\tPartial net #2: TOP - $I6') C(TOP) Q('(6.2,1.15;6.2,2.05;10,2.05;10,1.15)'))
|
||||
K(PMOS MOS4)
|
||||
K(NMOS MOS4)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l6 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l6 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3800 4600))
|
||||
N(1 I(SUBSTRATE)
|
||||
R(l8 (1700 100) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (-1610 -210) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (890 -760) (800 900))
|
||||
R(l12 (-1980 -830) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l6 (-2175 -925) (775 950))
|
||||
)
|
||||
N(2
|
||||
R(l3 (-1500 1800) (3000 2000))
|
||||
R(l3 (-200 -2000) (1000 2000))
|
||||
R(l8 (-2010 -1310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (1190 -210) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-1680 -280) (360 760))
|
||||
R(l12 (820 -830) (800 900))
|
||||
R(l13 (-1925 -775) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l10 (-700 -950) (400 1000))
|
||||
R(l2 (-1875 -975) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l4 (-125 -250) (250 2500))
|
||||
R(l4 (-250 -3050) (250 1600))
|
||||
R(l4 (-250 1200) (250 1600))
|
||||
)
|
||||
N(4
|
||||
R(l8 (-510 -310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (-220 2180) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-290 -3530) (360 2840))
|
||||
R(l12 (-360 -2800) (360 760))
|
||||
R(l12 (-360 2040) (360 760))
|
||||
R(l2 (-680 -855) (775 950))
|
||||
R(l6 (-775 -3750) (775 950))
|
||||
)
|
||||
P(1 I(SUBSTRATE))
|
||||
P(2)
|
||||
P(3)
|
||||
P(4)
|
||||
D(1 D$PMOS
|
||||
Y(0 2800)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 4)
|
||||
T(G 3)
|
||||
T(D 2)
|
||||
T(B 2)
|
||||
)
|
||||
D(2 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 4)
|
||||
T(G 3)
|
||||
T(D 1)
|
||||
T(B 1)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((1500 800) (9080 4600))
|
||||
N(1
|
||||
R(l4 (2920 2600) (3980 400))
|
||||
R(l11 (-300 -300) (200 200))
|
||||
R(l12 (-300 -300) (690 400))
|
||||
)
|
||||
N(2 I(A)
|
||||
R(l4 (7700 2600) (2880 400))
|
||||
R(l15 (-2380 -200) (0 0))
|
||||
)
|
||||
N(3 I(Q)
|
||||
R(l12 (1810 2600) (690 400))
|
||||
R(l16 (-400 -200) (0 0))
|
||||
)
|
||||
N(4 I(VDD)
|
||||
R(l3 (4000 3400) (2700 2000))
|
||||
R(l17 (-2500 -1000) (0 0))
|
||||
)
|
||||
N(5 I('SUBSTRATE,VSS')
|
||||
R(l17 (4200 1500) (0 0))
|
||||
)
|
||||
P(2 I(A))
|
||||
P(3 I(Q))
|
||||
P(4 I(VDD))
|
||||
P(5 I('SUBSTRATE,VSS'))
|
||||
X(1 INV Y(3000 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 1)
|
||||
P(3 3)
|
||||
)
|
||||
X(2 INV Y(7700 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 2)
|
||||
P(3 1)
|
||||
)
|
||||
)
|
||||
Vendored
+93
@@ -0,0 +1,93 @@
|
||||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
# for debugging: _make_soft_connection_diodes(true)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
Vendored
+13
@@ -0,0 +1,13 @@
|
||||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT TOP A Q VDD SUBSTRATE|VSS
|
||||
X$1 Q SUBSTRATE|VSS VDD \$1 INV
|
||||
X$2 \$1 SUBSTRATE|VSS VDD A INV
|
||||
.ENDS TOP
|
||||
|
||||
.SUBCKT INV \$1 SUBSTRATE \$4 \$6
|
||||
M$1 \$4 \$6 \$1 \$4 PMOS L=0.25U W=0.95U AS=1.02125P AD=0.73625P PS=4.05U
|
||||
+ PD=3.45U
|
||||
M$2 SUBSTRATE \$6 \$1 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
|
||||
+ PS=3.45U PD=3.45U
|
||||
.ENDS INV
|
||||
Vendored
BIN
Binary file not shown.
Vendored
+201
@@ -0,0 +1,201 @@
|
||||
#%l2n-klayout
|
||||
W(TOP)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '3/0')
|
||||
L(l15 '3/1')
|
||||
L(l8 '4/0')
|
||||
L(l11 '5/0')
|
||||
L(l12 '6/0')
|
||||
L(l16 '6/1')
|
||||
L(l13 '7/0')
|
||||
L(l14 '8/0')
|
||||
L(l17 '8/1')
|
||||
L(l7)
|
||||
L(l10)
|
||||
L(l2)
|
||||
L(l9)
|
||||
L(l6)
|
||||
C(l3 l3 l10)
|
||||
C(l4 l4 l15 l11)
|
||||
C(l15 l4 l15)
|
||||
C(l8 l8 l12 l10 l2 l9 l6)
|
||||
CS(l8 l10 l2 l9 l6)
|
||||
C(l11 l4 l11 l12)
|
||||
CS(l11 l4)
|
||||
C(l12 l8 l11 l12 l16 l13)
|
||||
C(l16 l12 l16)
|
||||
C(l13 l12 l13 l14)
|
||||
C(l14 l13 l14 l17)
|
||||
C(l17 l14 l17)
|
||||
C(l7 l7)
|
||||
C(l10 l3 l8 l10)
|
||||
CS(l10 l3)
|
||||
C(l2 l8 l2)
|
||||
C(l9 l8 l9)
|
||||
C(l6 l8 l6)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l9 SUBSTRATE)
|
||||
GS(l9 SUBSTRATE)
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - $2') C(TOP) Q('(6.54,2.6;6.54,4.78;6.9,4.78;6.9,2.6)'))
|
||||
H(B('\tPartial net #2: TOP - $I3') C(TOP) Q('(7.12,1.18;7.12,4.78;7.48,4.78;7.48,1.18)'))
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - Q') C(TOP) Q('(1.81,1.18;1.81,4.78;2.78,4.78;2.78,1.18)'))
|
||||
H(B('\tPartial net #2: TOP - $I2') C(TOP) Q('(1.84,4.02;1.84,4.78;2.2,4.78;2.2,4.02)'))
|
||||
K(PMOS MOS4)
|
||||
K(NMOS MOS4)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-1200 -475) (1075 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l6 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l6 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3800 4600))
|
||||
N(1
|
||||
R(l8 (-1090 2490) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (360 -3420) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (-220 2180) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-870 -690) (360 760))
|
||||
R(l12 (220 -3600) (360 2840))
|
||||
R(l12 (-360 -2800) (360 760))
|
||||
R(l12 (-360 2040) (360 760))
|
||||
R(l2 (-980 -855) (1075 950))
|
||||
R(l6 (-775 -3750) (775 950))
|
||||
)
|
||||
N(2 I(SUBSTRATE)
|
||||
R(l8 (1700 100) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (-1610 -210) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (890 -760) (800 900))
|
||||
R(l12 (-1980 -830) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l6 (-2175 -925) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l3 (-1500 1800) (3000 2000))
|
||||
R(l3 (-200 -2000) (1000 2000))
|
||||
R(l8 (-2010 -1310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (1190 -210) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-1680 -280) (360 760))
|
||||
R(l12 (820 -830) (800 900))
|
||||
R(l13 (-1925 -775) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l10 (-700 -950) (400 1000))
|
||||
R(l2 (-1875 -975) (775 950))
|
||||
)
|
||||
N(4
|
||||
R(l4 (-125 -250) (250 2500))
|
||||
R(l4 (-250 -3050) (250 1600))
|
||||
R(l4 (-250 1200) (250 1600))
|
||||
)
|
||||
P(1)
|
||||
P(2 I(SUBSTRATE))
|
||||
P(3)
|
||||
P(4)
|
||||
D(1 D$PMOS
|
||||
Y(0 2800)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 1.02125)
|
||||
E(AD 0.73625)
|
||||
E(PS 4.05)
|
||||
E(PD 3.45)
|
||||
T(S 1)
|
||||
T(G 4)
|
||||
T(D 3)
|
||||
T(B 3)
|
||||
)
|
||||
D(2 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 1)
|
||||
T(G 4)
|
||||
T(D 2)
|
||||
T(B 2)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((1500 800) (9080 4600))
|
||||
N(1
|
||||
R(l4 (2920 2600) (3980 400))
|
||||
R(l11 (-300 -300) (200 200))
|
||||
R(l12 (-260 -300) (360 1600))
|
||||
)
|
||||
N(2 I(A)
|
||||
R(l4 (7700 2600) (2880 400))
|
||||
R(l15 (-2380 -200) (0 0))
|
||||
)
|
||||
N(3 I(Q)
|
||||
R(l12 (1810 2600) (690 400))
|
||||
R(l16 (-400 -200) (0 0))
|
||||
)
|
||||
N(4 I(VDD)
|
||||
R(l3 (4000 3400) (2700 2000))
|
||||
R(l14 (-1500 -1450) (1200 900))
|
||||
R(l17 (-2200 -450) (0 0))
|
||||
)
|
||||
N(5 I('SUBSTRATE,VSS')
|
||||
R(l14 (5200 1150) (1200 900))
|
||||
R(l17 (-2200 -550) (0 0))
|
||||
)
|
||||
P(2 I(A))
|
||||
P(3 I(Q))
|
||||
P(4 I(VDD))
|
||||
P(5 I('SUBSTRATE,VSS'))
|
||||
X(1 INV Y(3000 1600)
|
||||
P(0 3)
|
||||
P(1 5)
|
||||
P(2 4)
|
||||
P(3 1)
|
||||
)
|
||||
X(2 INV Y(7700 1600)
|
||||
P(0 1)
|
||||
P(1 5)
|
||||
P(2 4)
|
||||
P(3 2)
|
||||
)
|
||||
)
|
||||
Vendored
+93
@@ -0,0 +1,93 @@
|
||||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
# for debugging: _make_soft_connection_diodes(true)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
Vendored
+111
@@ -0,0 +1,111 @@
|
||||
|
||||
source($lvs_test_source)
|
||||
|
||||
# will get pretty big:
|
||||
# report_lvs($lvs_test_target_lvsdb, true)
|
||||
|
||||
target_netlist($lvs_test_target_cir, write_spice(true), "Extracted by KLayout")
|
||||
|
||||
schematic("vexriscv_schematic.cir.gz")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
pactive = input(4, 0)
|
||||
nactive = input(3, 0)
|
||||
ntie = input(5, 0)
|
||||
ptie = input(6, 0)
|
||||
|
||||
poly = input(7, 0)
|
||||
cont = input(10, 0)
|
||||
metal1 = input(11, 0)
|
||||
via1 = input(14, 0)
|
||||
metal2 = input(16, 0)
|
||||
via2 = input(18, 0)
|
||||
metal3 = input(19, 0)
|
||||
via3 = input(21, 0)
|
||||
metal4 = input(22, 0)
|
||||
via4 = input(25, 0)
|
||||
metal5 = input(26, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
poly_cont = cont & poly
|
||||
diff_cont = cont - poly
|
||||
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(poly_cont, poly)
|
||||
connect(poly_cont, metal1)
|
||||
connect(diff_cont, metal1)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(ntie, nwell)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
connect(metal2, via2)
|
||||
connect(via2, metal3)
|
||||
connect(metal3, via3)
|
||||
connect(via3, metal4)
|
||||
connect(metal4, via4)
|
||||
connect(via4, metal5)
|
||||
|
||||
# Global
|
||||
soft_connect_global(ptie, "BULK")
|
||||
connect_global(bulk, "BULK")
|
||||
|
||||
# Implicit
|
||||
connect_implicit("VDD")
|
||||
connect_implicit("VSS")
|
||||
|
||||
# Compare section
|
||||
|
||||
same_device_classes("PMOS", "TP")
|
||||
same_device_classes("NMOS", "TN")
|
||||
|
||||
# Ignore all caps from the schematic
|
||||
same_device_classes(nil, "CAP")
|
||||
|
||||
# Increase the default complexity from 100 to 200
|
||||
# This is required because the clock tree is incorrect and exhibits manifold ambiguities
|
||||
# (the netlists are just samples, not necessarily functional).
|
||||
# The algorithm needs enough freedom to follow all these branches and different variants.
|
||||
max_branch_complexity(200)
|
||||
|
||||
schematic.combine_devices
|
||||
|
||||
netlist.combine_devices
|
||||
|
||||
align
|
||||
|
||||
if ! compare
|
||||
raise "Netlists don't match"
|
||||
else
|
||||
puts "Congratulations! Netlists match."
|
||||
end
|
||||
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# encoding: UTF-8
|
||||
|
||||
# KLayout Layout Viewer
|
||||
# Copyright (C) 2006-2024 Matthias Koefferlein
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
if !$:.member?(File::dirname($0))
|
||||
$:.push(File::dirname($0))
|
||||
end
|
||||
|
||||
load("test_prologue.rb")
|
||||
|
||||
class DBHierNetworkProcessor_TestClass < TestBase
|
||||
|
||||
# Connectivity
|
||||
def test_1_Connectivity
|
||||
|
||||
conn = RBA::Connectivity::new
|
||||
|
||||
assert_equal(conn.to_s, "")
|
||||
|
||||
conn.connect(1)
|
||||
assert_equal(conn.to_s, "1:1")
|
||||
|
||||
conn.connect(0, 1)
|
||||
assert_equal(conn.to_s, "0:1\n1:0,1")
|
||||
|
||||
conn.soft_connect(0, 2)
|
||||
assert_equal(conn.to_s, "0:1,2-S\n1:0,1\n2:0+S")
|
||||
|
||||
gid1 = conn.connect_global(0, "GLOBAL1")
|
||||
assert_equal(gid1, 0)
|
||||
assert_equal(conn.global_net_name(gid1), "GLOBAL1")
|
||||
assert_equal(conn.global_net_id("GLOBAL1"), 0)
|
||||
assert_equal(conn.to_s, "0:1,2-S\nG0:0\n1:0,1\n2:0+S")
|
||||
|
||||
conn.soft_connect_global(1, "GLOBAL1")
|
||||
assert_equal(conn.to_s, "0:1,2-S\nG0:0\n1:0,1\nG1:0-S\n2:0+S")
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
load("test_epilogue.rb")
|
||||
Reference in New Issue
Block a user